NJRC NJU6657

NJU6657
Preliminary
88-common x 272-segment
Bitmap LCD Driver
GENERAL DESCRIPTION
The NJU6657 is a bitmap LCD driver to display graphics or
characters.
It contains 23,936 bits display data RAM, microprocessor
interface circuits, instruction decoder, 88-common and
272-segment drivers.
The bit image display data is transferred to the display data
RAM by serial or 8-bit parallel interface.
88 x 272 dots graphics or 17-character 5-line by 16 x 16 dots
character with icon are displayed by NJU6657 itself.
The NJU6657 contains a built-in OSC circuit for reducing
external components.
The wide operating voltage from 2.7 to 5.5V and low operating
current are suitable for battery-powered applications.
PACKAGE OUTLINE
NJU6657CJ
FEATURES
Direct Correspondence between Display Data RAM and LCD Pixel
Display Data RAM – 23,936 bits
225 LCD Drivers – 88-common and 272-segment
Direct Microprocessor Interface for both of 68 and 80 type MPU
Serial Interface (SDA, SCL, A0, CSB)
Programmable Bias selection : 1/5,1/7,1/8,1/9,1/10 bias
Useful Instruction Set
Display On/Off Cont, Initial Display Line Set, Page Address Set, Column Address Set, Status Read,
Display Data Read/Write, ADC Select, Common Direction Register Set, Inverse Display,
Entire Display On/Off, Partial Select, n-line Inverse Drive Register Set, Dummy Period Set, Read Modify Write,
End, Internal Oscillation Circuit ON/OFF, Oscillation Frequency Set, Bias Select, Power Control set,
EVR Register Set, Voltage Booster Circuits Multiple Select, Voltage Booster Circuits Clock Select, Temperture
Sensor ON/OFF, Soft Reset, Power Save.
Power Supply Circuits for LCD Incorporated
Voltage Booster Circuits (12-time Maximum),
Voltage Adjust Circuits, Voltage Follower x 4
High Precision Voltage Regulator Incorporated (VREF=+3%, Ta=25OC )
Precision Electrical Variable Resistance (400-step)
VLCD Temperature Coefficient
:-0.00 to –0.15%/OC
Low Power Consumption 130uA(Typ.).
Operating Voltage (All the voltages are based on VSS=0V.)
- Logic Operating Voltage
: VDD=2.7V to 5.5V
- Voltage Booster Operating Voltage
: VEE=VDD to 5.5V
- LCD Driving Voltage
: VLCD= 4.8 to 28.8V(External Voltage: 36.0V)
Rectangle outlook for COG
Package Outline : Bump-chip
C-MOS Technology (Substrate : P)
Ver.2012-11-22
-1-
NJU6657
Preliminary
163
192
PAD LOCATION
・・・・・・
Alignment
mark2
193
Alignment
mark3
・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・
X
Y
・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・
162
ITEM
Chip Size
SIZE
X
Y
17.76
1.97
UNIT
mm
Chip Tchickness
625±30
um
Bump Pich
50(min)
um
Bump Size
Bump Height
No. 1 to 162
79
86
um
No. 163 to 192
122
30
um
No. 193 to 514
30
122
um
No. 515 to 544
122
30
um
17.5
um
１
514
Alignment
mark3
Alignment
mark1
-2-
544
515
・・・・・・
Ver.2012-11-22
NJU6657
Preliminary
Alignment Mark 1
(-8645µm, -854µm)
45µm
Alignment Mark 2
(8645µm, 768µm)
45µm
18µm
Alignment Mark 3
(8645µm, -854µm)
(-8645µm, 768µm)
25µm
50µm
25µm
50µm
Ver.2012-11-22
-3-
NJU6657
Preliminary
PAD COORDINATES
Chip Size 17.76 x 1.97mm(Chip Center X=0um, Y=0um)
PAD No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
-4-
Terminal
DUMMY0
DUMMY1
DUMMY2
DUMMY3
DUMMY4
DUMMY5
DUMMY6
BUSY
DUMMY7
OSC1
DUMMY8
DUMMY9
CSB
RSTB
A0
VPDN
WRB
RDB
VPUP
D7/SDA
D6/SCL
D0
D1
D2
D3
D4
D5
D6/SCL
D7/SDA
VPDN
CLS
VPUP
CSEL
VPDN
SEL68
VPUP
PS
VPDN
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSE
VSSE
VSSE
VSSE
X=µm
-8050
-7950
-7850
-7750
-7650
-7550
-7450
-7350
-7250
-7150
-7050
-6950
-6850
-6750
-6650
-6550
-6450
-6350
-6250
-6150
-6050
-5950
-5850
-5750
-5650
-5550
-5450
-5350
-5250
-5150
-5050
-4950
-4850
-4750
-4650
-4550
-4450
-4350
-4250
-4150
-4050
-3950
-3850
-3750
-3650
-3550
-3450
-3350
-3250
-3150
Y=µm
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
PAD No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Terminal
VSSE
VSSE
VSSE
VSSE
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VST1
C1P
C1P
C1P
C1P
C1P
C1P
C1N
C1N
C1N
C1N
C1N
C1N
VST1
VST1
VST1
VST1
VST1R
VST1R
VST1R
VST1R
VDCIN
VDCIN
VDCIN
X=µm
-3050
-2950
-2850
-2750
-2650
-2550
-2450
-2350
-2250
-2150
-2050
-1950
-1850
-1750
-1650
-1550
-1450
-1350
-1250
-1150
-1050
-950
-850
-750
-650
-550
-450
-350
-250
-150
-50
50
150
250
350
450
550
650
750
850
950
1050
1150
1250
1350
1450
1550
1650
1750
1850
Y=µm
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
Ver.2012-11-22
NJU6657
Preliminary
PAD No.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Ver.2012-11-22
Terminal
VDCIN
VDCOUT
VDCOUT
VDCOUT
VDCOUT
C2P
C2P
C2P
C2N
C2N
C2N
C4P
C4P
C4P
C6P
C6P
C6P
DUMMY10
C5P
C5P
C5P
C3N
C3N
C3N
C3P
C3P
C3P
VDCOUT
VDCOUT
VDCIN
VDCIN
VLCD
VLCD
VLCD
V1
V1
V1
V2
V2
V2
V3
V3
V3
V4
V4
V4
VSSA
VSSA
VSS
VSS
X=µm
1950
2050
2150
2250
2350
2450
2550
2650
2750
2850
2950
3050
3150
3250
3350
3450
3550
3650
3750
3850
3950
4050
4150
4250
4350
4450
4550
4650
4750
4850
4950
5050
5150
5250
5350
5450
5550
5650
5750
5850
5950
6050
6150
6250
6350
6450
6550
6650
6750
6850
Y=µm
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
PAD No.
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
Terminal
TEST2
TEST1
TSV
TEST3
TEST4
DUMMY11
DUMMY12
DUMMY13
DUMMY14
DUMMY15
DUMMY16
DUMMY17
DUMMY18
DUMMY19
COM43
COM42
COM41
COM40
COM39
COM38
COM37
COM36
COM35
COM34
COM33
COM32
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
DUMMY20
DUMMY21
DUMMY22
DUMMY23
DUMMY24
DUMMY25
DUMMY26
COM18
COM17
COM16
COM15
X=µm
6950
7050
7150
7250
7350
7450
7550
7650
7750
7850
7950
8050
8596.1
8596.1
8596.1
8596.1
8596.1
8596.1
8596.1
8596.1
8596.1
8596.1
8596.1
8596.1
8596.1
8596.1
8596.1
8596.1
8596.1
8596.1
8596.1
8596.1
8596.1
8596.1
8596.1
8596.1
8596.1
8596.1
8596.1
8596.1
8596.1
8596.1
8025
7975
7925
7875
7825
7775
7725
7675
Y=µm
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-853.8
-768.8
-718.8
-668.8
-618.8
-568.8
-518.8
-468.8
-418.8
-368.8
-318.8
-268.8
-218.8
-168.8
-118.8
-68.8
-18.8
31.2
81.2
131.2
181.2
231.2
281.2
331.2
381.2
431.2
481.2
531.2
581.2
631.2
681.2
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
-5-
NJU6657
Preliminary
PAD No.
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
-6-
Terminal
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
X=µm
7625
7575
7525
7475
7425
7375
7325
7275
7225
7175
7125
7075
7025
6975
6925
6875
6825
6775
6725
6675
6625
6575
6525
6475
6425
6375
6325
6275
6225
6175
6125
6075
6025
5975
5925
5875
5825
5775
5725
5675
5625
5575
5525
5475
5425
5375
5325
5275
5225
5175
Y=µm
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
PAD No.
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
Terminal
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
X=µm
5125
5075
5025
4975
4925
4875
4825
4775
4725
4675
4625
4575
4525
4475
4425
4375
4325
4275
4225
4175
4125
4075
4025
3975
3925
3875
3825
3775
3725
3675
3625
3575
3525
3475
3425
3375
3325
3275
3225
3175
3125
3075
3025
2975
2925
2875
2825
2775
2725
2675
Y=µm
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
Ver.2012-11-22
NJU6657
Preliminary
PAD No.
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
Ver.2012-11-22
Terminal
SEG85
SEG86
SEG87
SEG88
SEG89
SEG90
SEG91
SEG92
SEG93
SEG94
SEG95
SEG96
SEG97
SEG98
SEG99
SEG100
SEG101
SEG102
SEG103
SEG104
SEG105
SEG106
SEG107
SEG108
SEG109
SEG110
SEG111
SEG112
SEG113
SEG114
SEG115
SEG116
SEG117
SEG118
SEG119
SEG120
SEG121
SEG122
SEG123
SEG124
SEG125
SEG126
SEG127
SEG128
SEG129
SEG130
SEG131
SEG132
SEG133
SEG134
X=µm
2625
2575
2525
2475
2425
2375
2325
2275
2225
2175
2125
2075
2025
1975
1925
1875
1825
1775
1725
1675
1625
1575
1525
1475
1425
1375
1325
1275
1225
1175
1125
1075
1025
975
925
875
825
775
725
675
625
575
525
475
425
375
325
275
225
175
Y=µm
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
PAD No.
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
Terminal
SEG135
DUMMY27
DUMMY28
DUMMY29
DUMMY30
SEG136
SEG137
SEG138
SEG139
SEG140
SEG141
SEG142
SEG143
SEG144
SEG145
SEG146
SEG147
SEG148
SEG149
SEG150
SEG151
SEG152
SEG153
SEG154
SEG155
SEG156
SEG157
SEG158
SEG159
SEG160
SEG161
SEG162
SEG163
SEG164
SEG165
SEG166
SEG167
SEG168
SEG169
SEG170
SEG171
SEG172
SEG173
SEG174
SEG175
SEG176
SEG177
SEG178
SEG179
SEG180
X=µm
125
75
25
-25
-75
-125
-175
-225
-275
-325
-375
-425
-475
-525
-575
-625
-675
-725
-775
-825
-875
-925
-975
-1025
-1075
-1125
-1175
-1225
-1275
-1325
-1375
-1425
-1475
-1525
-1575
-1625
-1675
-1725
-1775
-1825
-1875
-1925
-1975
-2025
-2075
-2125
-2175
-2225
-2275
-2325
Y=µm
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
-7-
NJU6657
Preliminary
PAD No.
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
-8-
Terminal
SEG181
SEG182
SEG183
SEG184
SEG185
SEG186
SEG187
SEG188
SEG189
SEG190
SEG191
SEG192
SEG193
SEG194
SEG195
SEG196
SEG197
SEG198
SEG199
SEG200
SEG201
SEG202
SEG203
SEG204
SEG205
SEG206
SEG207
SEG208
SEG209
SEG210
SEG211
SEG212
SEG213
SEG214
SEG215
SEG216
SEG217
SEG218
SEG219
SEG220
SEG221
SEG222
SEG223
SEG224
SEG225
SEG226
SEG227
SEG228
SEG229
SEG230
X=µm
-2375
-2425
-2475
-2525
-2575
-2625
-2675
-2725
-2775
-2825
-2875
-2925
-2975
-3025
-3075
-3125
-3175
-3225
-3275
-3325
-3375
-3425
-3475
-3525
-3575
-3625
-3675
-3725
-3775
-3825
-3875
-3925
-3975
-4025
-4075
-4125
-4175
-4225
-4275
-4325
-4375
-4425
-4475
-4525
-4575
-4625
-4675
-4725
-4775
-4825
Y=µm
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
PAD No.
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
Terminal
SEG231
SEG232
SEG233
SEG234
SEG235
SEG236
SEG237
SEG238
SEG239
SEG240
SEG241
SEG242
SEG243
SEG244
SEG245
SEG246
SEG247
SEG248
SEG249
SEG250
SEG251
SEG252
SEG253
SEG254
SEG255
SEG256
SEG257
SEG258
SEG259
SEG260
SEG261
SEG262
SEG263
SEG264
SEG265
SEG266
SEG267
SEG268
SEG269
SEG270
SEG271
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
X=µm
-4875
-4925
-4975
-5025
-5075
-5125
-5175
-5225
-5275
-5325
-5375
-5425
-5475
-5525
-5575
-5625
-5675
-5725
-5775
-5825
-5875
-5925
-5975
-6025
-6075
-6125
-6175
-6225
-6275
-6325
-6375
-6425
-6475
-6525
-6575
-6625
-6675
-6725
-6775
-6825
-6875
-6925
-6975
-7025
-7075
-7125
-7175
-7225
-7275
-7325
Y=µm
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
Ver.2012-11-22
NJU6657
Preliminary
PAD No.
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
Ver.2012-11-22
Terminal
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
DUMMY31
DUMMY32
DUMMY33
DUMMY34
DUMMY35
DUMMY36
DUMMY37
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COM80
COM81
COM82
COM83
COM84
COM85
COM86
COM87
DUMMY38
DUMMY39
X=µm
-7375
-7425
-7475
-7525
-7575
-7625
-7675
-7725
-7775
-7825
-7875
-7925
-7975
-8025
-8596.1
-8596.1
-8596.1
-8596.1
-8596.1
-8596.1
-8596.1
-8596.1
-8596.1
-8596.1
-8596.1
-8596.1
-8596.1
-8596.1
-8596.1
-8596.1
-8596.1
-8596.1
-8596.1
-8596.1
-8596.1
-8596.1
-8596.1
-8596.1
-8596.1
-8596.1
-8596.1
-8596.1
-8596.1
-8596.1
Y=µm
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
702.3
681.2
631.2
581.2
531.2
481.2
431.2
381.2
331.2
281.2
231.2
181.2
131.2
81.2
31.2
-18.8
-68.8
-118.8
-168.8
-218.8
-268.8
-318.8
-368.8
-418.8
-468.8
-518.8
-568.8
-618.8
-668.8
-718.8
-768.8
PAD No.
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
Terminal
X=µm
Y=µm
-9-
NJU6657
Preliminary
BLOCK DIAGRAM
VLCD
V1
V2
V3
V4
VDCIN
VEE
VSSE
C1+
C1VST1
VST1R
C2+
C2C3+
C3C4+
C5+
C6+
VDCOUT
V7 to D0
PS
SEL68
A0
RDB/E
WRB/RW
RSTB
SEG0 to SEG271
COM0 to COM87
SEG Driver
COM Driver
DD RAM
Temp. Sensor
TSV
Oscilation
Circuit
CLS
Power
Supply
Circuit
OSC1
BUSY
I/F
Logic Circuit
VDD
VSS
- 10 -
Ver.2012-11-22
NJU6657
Preliminary
TERMINAL DISCRIPTION(Power Supply)
No.
61 to 68
39 to 46
149, 150
69 to 76
Symbol
VDD
VSS
I/O
Power
GND
VEE
Power
47 to 54
VSSE
Power
102 to 105, VDCOUT
128, 129
Power
98 to 101,
130,131
132 to 134
135 to 137
138 to 140
141 to 143
144 to 146
55 to 60,
147,148
78 to 83
84 to 89
77,
90 to 93
VDCIN
Power
VLCD
V1
V2
V3
V4
VSSA
Power/
Out
C1P
C1N
VST1
Out
94 to 97
VST1R
Ver.2012-11-22
Power/
Out
Power/
Out
FUNCTION
Power supply Terminal
GND Terminal
Voltage booster input
･When the internal voltage booster is not used, This terminal connected VDD.
Voltage booster input
This terminal is internally connected to the VSS level.
2nd voltage booster output. This terminal must be connected VDCIN.
When the internal voltage booster used, the capacitor between VSS terminal must be
connected.
Note: It recommends using 102 to 105 terminals, when the external power supply
used.
Voltage booster input, This terminal connected VDCIN
Note: It recommends using 98 to 101 terminals, when the external power supply used.
LCD driving voltage
・When the internal voltage booster is not used, external LCD driving voltages
(V1 to V4, VSSA and VLCD) should be supplied onto these terminals. The
external voltages should be maintained with the following relationship.
VDCIN>V0>V1>V2>V3>V4>VSSA
・When the internal voltage booster is used, the capacitors between these
terminals (VLCD and V1 to V4) and VSS terminal must be connected.
Capacitor connection terminal for the 1st voltage booster
1st voltage booster output for high voltage circuits
The capacitor between VSS terminal must be connected.
1st voltage booster used, 2nd voltage booster is not used:
VST1=VST1R=VDCOUT=VDCIN
1st voltage booster is not used, 2nd voltage booster used:
OPEN or VST1R=VST1
1st voltage booster is not used, In the case of use by a voltage regulating function of a
2nd voltage booster circuit:
Please supply an external power supply from this terminal.
Note: It recommends using 90 to 93 terminals, when the external power supply used.
1st and 2nd booster are not used:
OPEN
2nd voltage booster output for high voltage circuits
OPEN or The capacitor between VSS terminal must be connected.
1st voltage booster used, 2nd voltage booster is not used:
VST1=VST1R=VDCOUT=VDCIN
1st voltage booster is not used, 2nd voltage booster used:
Please supply an external power supply from this terminal.
1st voltage booster is not used, In the case of use by a voltage regulating function of a
2nd voltage booster circuit:
The capacitor between VSS terminal must be used.
1st and 2nd booster are not used:
The capacitor between VSS terminal must be connected or OPEN.
- 11 -
NJU6657
Preliminary
No.
106∼108
109∼111
125∼127
122∼124
112∼114
119∼121
115∼117
Symbol
C2P
C2N
C3P
C3N
C4P
C5P
C6P
I/O
O
FUNCTION
2nd voltage boostor capacitor connection terminal
TERMINAL DESCRIPTION(FIX)
No.
19,32,36
Symbol
VPUP
I/O
Power/
O
16,30,34,
38
VPDN
Power/
O
- 12 -
FUNCTION
This terminal is internally connected to VDD level.
･This terminal is used to fix the VDD level.
When the not used normally open.
This terminal is internally connected to VSS level.
･Thisterminal is used to fix the VSS level.
When the not used normally open.
Ver.2012-11-22
NJU6657
Preliminary
TERMINAL DESCRIPTION(INTERFACE)
No.
20,29
21,28
27
26
25
24
23
22
Symbol
D7/SDA
D6/SCL
D5
D4
D3
D2
D1
D0
I/O
I/O
37
PS
I
SEL68
I
CSB
I
35
13
15
A0
I
18
RDB
(E)
I
17
WRB
(R/W)
I
14
RESB
I
Ver.2012-11-22
FUNCTION
Data I/O terminal
In the parallel interface mode (P/S=“H”)
D7 to D0: 8-bit bi-directional bus
In the serial interface mode (P/S=”L”)
D7: Serial data bi-directional bus(SDA)
D6: Serial clk input terminal(SCL)
D0 to D5: Hi-Z
When CSB=”H” status, the D5 to D0 terminals are in the high impedance status
therefore those terminals should be fixed to VDD or VSS.
Parallel / Serial interface mode select
P/S =”L”: Serial interface
P/S =”H”: Parallel interface
In the serial interface mode (P/S=”L”)
RAM Data and status read operation do not work in mode of serial intrerface.
MPU interface type select
This teminal must be fixed VDD or VSS.
SEL68 =L: 80 series parallel / 3 wire-serial
H:68 series parallel / 5wire-serial
Chip select
Active “0”
Data Input/Output are avaibal during CSB=”L”
Resister select
･The data on the D0 to D7 is distinguished between Display data and Instruction data
by status of A0.
A0 L: Instruction command
H: Display data
<In case of 80 Type MPU> (PS=”H”,SEL68=”L”)
RDb signal of 80 type MPU input terminal. Active “L”
During this signal is “L”, D0 to D7 terminals output.
<In case of 68 Type MPU> (PS=”H”,SEL68=”H”)
Enable signal of 68 type MPU input terminal. Active “H”
<In case of 80Type MPU> (PS=”H”,SEL68=”L”)
Connect to the 80 type MPU WRb signal. Active “L”
The data on the data bus input synchronizing the rise edge of this signal.
<In case of 68 Type MPU>(PS=”H”,SEL68=”H”)
The read/write control signal of 68 type MPU input terminal.
RW L: Write
H: Read
Reset terminal.
When the RESB terminal goes to “L”, the initialization is performed.
- 13 -
NJU6657
Preliminary
TERMINAL DISCRIPTION(LCD DRIVER)
No.
SYMBOL
165∼189, C0∼C87
197∼215,
492∼510,
518∼542
I/O
O
FUNCTION
LCD driving signal output terminals(Common)
Common output terminals
The following output voltages are selected by the combination of alternating (FR)
signal and Common scanning data.
Scan Data
H
L
FR
Output Voltage
H
L
H
L
VLCD
VSS
V1
V4
216∼351,
356∼491
S0∼S271
O
LCD driving signal output terminals(Segment)
Segment output terminals
The following output voltages are selected by the combination of alternating (FR)
signal and display data in the RAM.
Output Voltage
RAM Data
FR
Normal
Reverse
H
VLCD
V2
H
L
VSS
V3
H
V2
VLCD
L
L
V3
VSS
1∼7,
9,11,12,
118,
156∼164,
190∼196,
352∼355,
511∼517,
543,544
DUMMYx
-
Dummy Terminals.
Normally Open.
- 14 -
Ver.2012-11-22
NJU6657
Preliminary
TERMINAL DISCRIPTION(OTHER TERMINAL)
No.
10
SYMBOL
OSC1
I/O
I
31
CLS
I
33
CSEL
I
153
TSV
O
8
152
BUSY
TEST1
O
O
151
TEST2
O
154
TEST3
I
155
TEST4
I
Ver.2012-11-22
FUNCTION
External clock input terminal
In internal oscillation operation, this terminal must connect to VDD or VSS.
Terminal to select whether or enable or disable the display clock internal oscillation
circuit.
CLS=”H” : Internal oscillation circuit is enable.
CLS=”L” : Internal oscillation circuit is disabled. (requires external clock)
When CLS=”L”, input the display clock through the OSC1 terminal.
Common driver output select terminal
“L” : Both sides wiring mode
“H”: Comb wiring mode
Thermo sensor analog voltage output terminal
In case of not used, this terminal is open.
Busy flag terminal
TEST terminal
Normaly open
TEST terminal
Normaly open
TEST terminal
Normaly open
TEST terminal
Normaly open
- 15 -
NJU6657
Preliminary
FUNCTIONAL DESCRIPTION
(1) Discription for each blocks
(1-1) Selection of Parallel or Serial interface
NJU6657 interfaces with MPU by 8-bit bi-directional data bus (D7 to D0) or serial interface(SDA, SCL).
The 8-bit parallel or serial interface is determined by a condition of the PS terminal connecting to “H” or “L” level.
The PS terminal is used to select parallel or serial interface mode as shown in the following table. In the parallel interface
mode, the SEL terminal is used to select 68- or 80-type MPU interface type.
In the serial interface mode, the SEL terminal used to select 5 wire serial or 3 wire serial interfase type.
In case of the serial interface, status and RAM data read out operation is impossible.
PS
H
L
SEL
H
L
H
L
MPU type
68 type MPU
80 type MPU
5 wire serial
3 wire serial
CSB
CSB
CSB
CSB
CSB
A0
A0
A0
A0
-
RDB
E
RDB
-
WRB
WR
WRB
WR
-
D7
D6
D5 to D0
Data
Data
SDA
SDA
SCL
SCL
Note 1
Note 1
Note 1) “-“: Fix to “VDD” or “VSS”.
(1-2) Data recognition
In the parallel interface mode, the data from MPU is interpreted as display data or instruction according to the combination
of the A0, RDB, and WRB(R/W) signals.
A0
L
L
H
H
- 16 -
68 type
RW
1
0
1
0
80 type
RDB
0
1
0
1
WRB
1
0
1
0
Function
Status read
Write into the Register(Instruction)
Read Display Data
Write Display Data
Ver.2012-11-22
NJU6657
Preliminary
(1-3) Parallel interface
While the chip select is active (CSB=”L”), the data from MPU can be written into the DDRAM or the instruction
register. When the A0 is “L”, the data is interpreted as display data whitch is stored in the DDRAM. The display data is
latched at the rising edge of the WRB signal in the 80-series MPU mode, or at the falling edge of the E signal in the
68-series MPU mode.
A0
H
L
Data
Display RAM data
Internal command register
In the DDRAM read sequence, be sure to execute a dummy read right after setting an address or right after
writing display data or instruction. The data from MPU is temporarily held in the internal bus-holder, then released
on the internal data-bus, therefore a dummy data is read out by the 1st “Display Data Read” instruction. After that,
the display data is read out from a specified address by the 2nd instruction. Note that the “Display Data Read”
instruction cannot be used in the serial inter face.
80-series parallel data transmission (PS=”H”, SEL68=”L”)
<Write>
RS
(Note) When the DDRAM data writing, CSb should be changed to "H" once every 2-byte.
CSb
WRb
D7 to D0
(Data bus direction)
Input
<Read>
RS
CSb
RDb
D7 to D0
1st reading out is dummy.
(Data bus direction)
Ver.2012-11-22
Input
Outpu
Input
Outpu
Input
Outpu
Input
The data bus is output at CSB=”L” and RDB=”L”.
- 17 -
NJU6657
Preliminary
68-series parallel data transmission (PS=”H”, SEL68=”H”)
<Write>
RS
(Note) When the DDRAM data writing, CSb should be changed to "H" once every 2-byte.
RW
CSb
E
D7 to D0
(Data bus
Input
<Read>
RS
RW
CSb
E
D7~D0
1st
(Data bus
- 18 -
reading
out
is
Input
Outpu
Input
Outpu
Input
Outpu
Input
The data bus is output at RW=”H”, CSb=”L” and E=”H”.
Ver.2012-11-22
NJU6657
Preliminary
(1-4) 5 wire serial Interface
While the chip select is active (CSB=”L”), the SDA and SCL are enabled. While the chip select is inactive
(CSB=”H”), the SDA and SCL are disabled, and the internal shift register and the internal counter are being initilized.
8-bit serial data on the SDA is latched at the rising edge of the SCL signal in order of D7, D6, …, and D0, and
converted into 8-bit parallel data at the timing of the internal signal produced from the 8th SCL signal. The data on
the SDA is interpreted as display data instruction according to the A0.
A0
H
L
Data
Display RAM data
Internal command register
Note that the SCL should be set to “L” right after data transmission or during non-access because the serial
interface is susceptible to external noises which may cause malfunctions. For added safety, inactivate the chip select
(CSB=”H”) temporary whenever 8-bit data transmission is completed.
Serial data transmission (PS=”L”, SEL=”L”)
<Write>
RW
(Data bus directio
Input
The data bus is Input at RW=”L”.
RS
CSb
SCL
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
SDA
<Read>
RW
(Data bus
Output
Input
The data bus is output at RW=”H” and CSb=”L”.
RS
CSb
SCL
Ver.2012-11-22
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
SDA
- 19 -
NJU6657
Preliminary
(1-5) 3 wire serial Interface
While the chip select is active (CSB=”L”), the SDA and SCL are enabled. While the chip select is not active
(CSB=”H”), the SDA and SCL are disabled, and the internal shift register and the internal counter are being
initialized. 9-bit serial data on the SDA is lached at the rising edge of the SCL signal in order of A0, D7, D6, … , and
then converted into 9-bit parallel data at the timing of the internal signal produced from the 9th SCL signal. The data
on the SDA is interpreted as display data or instruction according to the combination of the A0 bit status.
Note that the SCL should be set to “L” right after data transmission or during non-access because the serial
interface is susceptible to external noises which may cause malfunctions. For added safety, inactivate the chip-select
(CSB=”H”) temporary whwnever 9-bit data transmission is completed.
3wire Serial data transmission (PS=”L”, SEL=”H”)
RW
(Data bus directio
Input
The data bus is Input at RW=”L”.
CSb
SCL
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
SDA
(1-6) Write to Internal Register
The writing internal register, therre are two byte and 1byte instruction.
In two byte instruction, 1st byte specifies “Mode Set”. The relation of CSB and Data is shown in below.
And then Moreover, it is also possible to write in the instruction of plurality with CSB=L continuously, in order to judge
automatically distinction of a 1-byte instruction or a 2-byte instruction inside.
Note) 2 Byte instruction: Between byte data CSB="L".
Note) It is possible for data continuously at the CSB=”L” condition.
CSB
A0
WRB
D7~0
RAM
RAM Data
Mode
data
2 Byte
Instruction
Mode
Mode
data
Mode
Mode
data
1 Byte
Instruction
st
Note) The 1 byte is knowledge of “mode set” at falling edge of the CSB condition.
- 20 -
Ver.2012-11-22
NJU6657
Preliminary
(1-7) Busy Flag (BF)
While the internal circuits are operating, the busy flag(BF) is “1”, and any instruction excepting for the status read
are inhibited.
The busy flag goes to “1” from D7 terminal when status read instruction is executed.
When enough cycle time over than Tcyc indicated in “AC CHARACTERISTICS” is ensured, no need to check the
busy flag for reduction of the MPU loads.
(1-8) Initial display line register
The initial display line register assigns a DDRAM line address, which corresponds to COM0 by “initial display line
set” instruction. It is used for not only normal display but also vertical display scrolling and page swiching without
changing the contents of the DDRAM.
(1-9) Line counter
The line counter generates the line address of display data RAM by the count up operation synchronizing the
common cycle after the reset operation at the status change of internal FR signal.
(1-10) Column address counter
The coulumn address counter is 8-bit pre-settable counter addressing the column address of display data RAM as
shown in Fig. 1. It is incremented (+1) by the display data read / write instruction execution.
The column address counter is independent of the page register.
By the address inverse instruction, the column address decoder inverse the column address of display data RAM
corresponding to the segment driver.
(1-11) Page register
The page register gives a page address of display data RAM as shown in Fig. 1. When the MPU accesses the data
with the page change, the page address set instruction is required.
Page address “8”(D4 to D0 = “0100”) is Icon RAM area, the data only for the D0 is valid.
(1-12) Display data RAM
Display data RAM is the bit map RAM consisting of 23,936 bits to memorize the display data corresponding to
each pixel of LCD panel. The each bit in the display data RAM corresponds to the each pixel of the LCD panel
and controls the display by following bit data.
When normal display : On=”1”, Off=”0”
When inverse display : On=”0”, Off=”1”
The display data RAM outputs 272-bit parallel data in the area addressed by the line counter, and these data are set
into the display data latch.
The access operation from MPU to the display data RAM and the data output from the display data RAM are so
controlled to operate independently that the data rewriting does not influence with any malufunctions to the
display.
Ver.2012-11-22
- 21 -
NJU6657
Preliminary
Page Address
Line
Address
Display Pattern
Data
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
D0
D1
D2
P3,P2,P1,P0
(0,0,0,0)
D3
PAGE 0
D4
D5
D6
D7
P3,P2,P1,P0
(0,0,0,1)
D0
■
■
D1
■
■
D2
■
D3
■
D4
■
D5
■
■
D6
■
■
■
■
■
■
■
PAGE 1
■
D7
D0
D1
D2
P3,P2,P1,P0
(0,0,1,0)
D3
PAGE 2
D4
D5
D6
D7
D0
D1
・
・
・
・
・
・
・
・
・
・
・
・
・
・
・
・
4DH
4EH
4FH
50H
51H
52H
53H
54H
55H
56H
57H
D6
D7
D0
D1
D2
P3,P2,P1,P0
(1,0,1,0)
D3
PAGE 10
D4
D5
D6
D7
Column
Address
ADC
D0="0" 000 001 002 003 004 005 006
D0="1" 10F 10E 10D 10C 10B 10A 109
Segment Drivers
0
1
2
3
4
5
6
---------------
10E
001
10F
000
270
271
Common
Driver
C80
C81
C82
C83
C84
C85
C86
C87
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
・
・
・
・
C69
C70
C71
C72
C73
C74
C75
C76
C77
C78
C79
For example the Initial display is 08H.
Fig.1 Display data RAM (DDRAM) Map
- 22 -
Ver.2012-11-22
NJU6657
Preliminary
(1-13) COMMON DRIVER OUTPUT SWITCHING
The common output order of NJU6657 is selected by CSEL terminal (Both sides wiring or Comb wiring). When the
CSEL="L", the COM0 to 43 connects on the lower half of the panel and the COM44 to 87 connects on the upper half.
When the CSEL="H", the COM is divided by 4, that is connected to the panel by the comb pattern.
< Wiring image >
(i) CSEL=”L” Both sides wiring mode
COM87
Panel
(CSEL="L")
COM44
COM43
COM0
COM44
COM0
NJU6657
COM87
COM43
(ii) CSEL=”H” Comb wiring mode
COM84∼COM87
COM76∼COM79
COM68∼COM71
COM60∼COM63
COM52∼COM55
COM44∼COM47
COM36∼COM39
COM28∼COM31
COM20∼COM23
COM12∼COM15
COM4∼COM7
Panel
(CSEL="H")
COM44
COM80∼COM83
COM72∼COM75
COM64∼COM67
COM56∼COM59
COM48∼COM51
COM40∼COM43
COM32∼COM35
COM24∼COM27
COM16∼COM19
COM8∼COM11
COM0∼COM3
COM0
NJU6657
COM87
COM43
The common direction register is selected by the “Common direction register set” is shown in Table.
INV
0
1
Table. Common direction
Status
Normal
Inverse
Common direction
COM0 -> COM87
COM87 -> COM0
(1-14) Display scroll function
NJU6657 is executed to the vertical smooth scroll display of 1-dot.
The Start line display set the line address shown Fig 1.
Ver.2012-11-22
- 23 -
NJU6657
Preliminary
(1-15) Partial display function
The partial display is executed by Partial select instruction.
This function reduces the LCD driving voltage and the power consumption when the duty set low like the clock display of
stand-by.
Page Address data Line Address
D0
00h
D1
01h
D2
02h
D3
03h
page0
D4
04h
D5
05h
D6
06h
D7
07h
D0
08h
D1
09h
D2
0Ah
D3
0Bh
page1
D4
0Ch
D5
0Dh
D6
0Eh
D7
0Fh
D0
10h
D1
11h
D2
12h
D3
13h
page2
D4
14h
D5
15h
D6
16h
D7
17h
D0
18h
D1
19h
D2
1Ah
D3
1Bh
page3
D4
1Ch
D5
1Dh
D6
1Eh
D7
1Fh
D0
20h
D1
21h
・
・
・
・
・
・
・
・
D6
4Eh
D7
4Fh
D0
50h
D1
51h
D2
52h
D3
53h
page10
D4
54h
D5
55h
D6
56h
D7
57h
SEG0
SEG25
Initialize Status: 1/88 Duty
COM0
COM10
COM29
COM87
COM Start COM Out
00h
COM0
01h
COM1
02h
COM2
03h
COM3
04h
COM4
05h
COM5
06h
COM6
07h
COM7
08h
COM8
09h
COM9
0Ah
COM10
0Bh
COM11
0Ch
COM12
0Dh
COM13
0Eh
COM14
0Fh
COM15
10h
COM16
11h
COM17
COM18
12h
13h
COM19
COM20
14h
15h
COM21
16h
COM22
17h
COM23
18h
COM24
19h
COM25
1Ah
COM26
1Bh
COM27
1Ch
COM28
1Dh
COM29
1Eh
COM30
1Fh
COM31
20h
COM32
21h
COM33
・
・
・
・
・
・
・
・
4Eh
COM78
4Fh
COM79
50h
COM80
51h
COM81
52h
COM82
53h
COM83
54h
COM84
55h
COM85
56h
COM86
57h
COM87
1/88 Duty
Display
Display Area
(Example１) Partial Select Command (Display line count=”04H”, COM Start position =”AH”)
SEG25
SEG0
Partial Select Command
Display line: 04H(20-line)
COM start position 0AH(COM10)
Setting.
COM0
Non
Active
Area
COM10
Active
Area
COM29
Non
Active
Area
COM87
Ver.2012-11-22
Page Addres data Line Address
00h
D0
01h
D1
02h
D2
03h
D3
page0
04h
D4
05h
D5
06h
D6
07h
D7
08h
D0
09h
D1
0Ah
D2
0Bh
D3
page1
0Ch
D4
0Dh
D5
0Eh
D6
0Fh
D7
10h
D0
11h
D1
12h
D2
13h
D3
page2
14h
D4
15h
D5
16h
D6
17h
D7
18h
D0
19h
D1
1Ah
D2
1Bh
D3
page3
1Ch
D4
1Dh
D5
1Eh
D6
1Fh
D7
20h
D0
21h
D1
・
・
・
・
・
・
・
・
4Eh
D6
4Fh
D7
50h
D0
51h
D1
52h
D2
53h
D3
page10
54h
D4
55h
D5
D6
56h
D7
57h
COM Start
Address COM Out
COM0
00h
COM1
01h
COM2
02h
COM3
03h
04h
COM4
05h
COM5
06h
COM6
07h
COM7
08h
COM8
09h
COM9
0Ah
COM10
0Bh
COM11
COM12
0Ch
COM13
0Dh
COM14
0Eh
COM15
0Fh
COM16
10h
COM17
11h
COM18
12h
COM19
13h
COM20
14h
COM21
15h
COM22
16h
17h
COM23
COM24
18h
COM25
19h
COM26
1Ah
COM27
1Bh
COM28
1Ch
COM29
1Dh
COM30
1Eh
COM31
1Fh
COM32
20h
COM33
21h
・
・
・
・
・
・
・
・
COM78
4Eh
COM79
4Fh
COM80
50h
COM81
51h
COM82
52h
COM83
53h
COM84
54h
COM85
55h
COM86
56h
COM87
57h
1/20 Duty
Display
Active Area
- 24 -
NJU6657
(Example 2) When both of Partial Select and Initial Display line set instruction are executed, the smmoth scroll
for vertical direction in partial display area.
SEG0
SEG25
Partial Select Command
Display line: 04H(20-line)
COM start position 0AH(COM10)
Initial Display Start Line Command
Line Address: 0AH
Setting.
COM0
Active
Area
COM11
Non
Active
Area
COM80
Active
Area
COM87
Page Addres data Line Address
D0
00h
D1
01h
D2
02h
D3
03h
page0
D4
04h
D5
05h
D6
06h
D7
07h
D0
08h
D1
09h
D2
0Ah
D3
0Bh
page1
D4
0Ch
D5
0Dh
D6
0Eh
D7
0Fh
D0
10h
D1
11h
D2
12h
D3
13h
page2
D4
14h
D5
15h
D6
16h
D7
17h
D0
18h
D1
19h
D2
1Ah
D3
1Bh
page3
D4
1Ch
D5
1Dh
D6
1Eh
D7
1Fh
D0
20h
D1
21h
・
・
・
・
・
・
・
・
D6
4Eh
D7
4Fh
D0
50h
D1
51h
D2
52h
D3
53h
page10
D4
54h
D5
55h
D6
56h
D7
57h
Start Line
Address Set
COM Start
Address COM Out
00h
COM0
COM1
01h
COM2
02h
COM3
03h
04h
COM4
05h
COM5
06h
COM6
COM7
07h
COM8
08h
COM9
09h
COM10
0Ah
0Bh
COM11
0Ch
COM12
0Dh
COM13
0Eh
COM14
0Fh
COM15
COM16
10h
COM17
11h
COM18
12h
COM19
13h
14h
COM20
15h
COM21
16h
COM22
COM23
17h
COM24
18h
COM25
19h
COM26
1Ah
1Bh
COM27
1Ch
COM28
1Dh
COM29
1Eh
COM30
1Fh
COM31
20h
COM32
21h
COM33
・
・
・
・
・
・
・
・
4Eh
COM78
4Fh
COM79
COM80
50h
COM81
51h
COM82
52h
COM83
53h
54h
COM84
55h
COM85
COM86
56h
COM87
57h
1/20 Duty
Display
Active Area
(Example 3) Partial Select Command (Display line count=”50H”, COM Start position=”AH”)
SEG25
SEG0
Partial Select Command
Display line: 04H(20-line)
COM start position 50H(COM80)
Initial Display Start Line Command
Line Address: 0AH
Setting.
COM0
Active
Area
COM11
Non
Active
Area
COM80
Active
Area
COM87
- 25 -
Page Address data Line Address
D0
00h
D1
01h
D2
02h
D3
03h
page0
D4
04h
D5
05h
D6
06h
D7
07h
D0
08h
D1
09h
D2
0Ah
D3
0Bh
page1
D4
0Ch
D5
0Dh
D6
0Eh
D7
0Fh
D0
10h
D1
11h
D2
12h
D3
13h
page2
D4
14h
D5
15h
D6
16h
D7
17h
D0
18h
D1
19h
D2
1Ah
D3
1Bh
page3
D4
1Ch
D5
1Dh
D6
1Eh
D7
1Fh
D0
20h
D1
21h
・
・
・
・
・
・
・
・
D6
4Eh
D7
4Fh
D0
50h
D1
51h
D2
52h
D3
53h
page10
D4
54h
D5
55h
D6
56h
D7
57h
COM Start
Address COM Out
00h
COM0
01h
COM1
02h
COM2
03h
COM3
04h
COM4
05h
COM5
06h
COM6
07h
COM7
08h
COM8
09h
COM9
0Ah
COM10
0Bh
COM11
0Ch
COM12
0Dh
COM13
0Eh
COM14
0Fh
COM15
10h
COM16
11h
COM17
12h
COM18
13h
COM19
14h
COM20
15h
COM21
16h
COM22
17h
COM23
18h
COM24
19h
COM25
1Ah
COM26
1Bh
COM27
COM28
1Ch
1Dh
COM29
1Eh
COM30
1Fh
COM31
20h
COM32
21h
COM33
・
・
・
・
・
・
・
・
4Eh
COM78
4Fh
COM79
50h
COM80
51h
COM81
COM82
52h
53h
COM83
COM84
54h
55h
COM85
56h
COM86
57h
COM87
1/20 Duty
Display
Display
Area
1/20 Duty
Display
Display
Area
Ver.2012-11-22
NJU6657
Preliminary
* Duty is changed automatically when Partial Display execution, but LCD Driving Voltage , Bias ratio, EVR
register are not changed. The optimum conditions should fix refering the result of actual display.
* The Dummy period Insertion position of Partial Display executed.
(Example 1) <display line count: 20-line, COM Start Position: COM10>
COM10→COM29→Dummy Time
(The dummy period is inserted in front of a COM display starting position.)
* The Dummy period Insertion position of when the overlap display and Partial Display executed.
(Example 2) <Display line count: 20-line, COM start Position: COM80>
COM80→COM87→COM0→COM11→Dummy Time
（When straddling the end of display position, the Dummy period is inserted in front of a
COM display starting position.）
Ver.2012-11-22
- 26 -
Confidential
NJU6657
Preliminary
(1-16) Reset circuit
The reset circuit initializes the LSI to the following status by using of the reset signal into the RESB terminal.
-Reset status using the RESB terminal:
1
2
3
4
5
6
7
8
9
PARAMETER
Display ON/OFF: OFF
Start display line set: Set to COM0
Page address set: Set to 0 page
Culumn address set: Set to
ADC select: Normal
Common direction: Normal
Display normal/inverse: normal
All display ON/OFF: OFF
Partial select
10
11
N-line inverse ON/OFF: OFF
N-line inverse register set
12
13
14
15
16
17
18
Dummy time set
Read modyfy write: OFF
Oscilator ON/OFF : ON
Internal oscillator frequency set:
43.1kHz
Bias ratio set: 1/10
Temperature coefficient: 0%/OC
Power controll: DC/DC, VREG, VF
19
20
21
22
23
24
E.V.R set : Min.
Boost. Voltage controll function set
Boost. Clock set
Temp. sensor ON/OFF : OFF
Discharge ON/OFF : OFF
Power save : OFF
Register name
D
SL6 to 0
PA3 to 0
AC7 to 0
ADC
SCAN
REV
ALLON
DN6 to 0
DST6 to 0
NLS
MIX
NL6 to 0
ST, DUM
RESET status
0
00H
0H
00H
0
0
0
0
48H
00H
0
0
00H
0,0
INTCK
SH1 to 0
OS4 to 0
BS2 to 0
TC2 to 0
DC1 to 0
VRG
VF
ER8 to 0
VU2 to 0
DCC2 to 0
TSON
DIS
1
10
10000
000
000
00
0
0
000H
0H
101
0
0
Int. No.
(1)
(2)
(3)
(4)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(18)
(19)
(20)
(21)
(22)
(23)(24)
(27)
(28)
(29)
(30)
(33)
The RESB terminal should be connected to MPU’s reset terminal, and the reset operation should be executed at
the same timing of the MPU reset. As described in the “BUS TIMING CHARACTERISTICS”, it is necessary to
input 1.0us(min.) or over “L” level signal into the RES terminal in order to carry out the reset operation. The LSI
will return to normal operation after about 1.5us(max.) from the rising edge of the reset signal.
The reset operation by RESb="L" initializes each register setting as above reset status, but the internal oscillation
circuit and output terminals (D0 to D7) are not affected.
The reset operation is necessary to avoid malfunctions.
Note 1) The “Reset” instruction in Table.4 can’t be substituted for the reset operation by using of the RESBterminal. It
executes above-mentioned only 11 to 20 items.
Note 2) The reset terminal is susceptible to external noise, so design PCB layout in consideration for the noise.
Note 3) In case of using external power supply for LCD driving voltage, the RESb terminal is required to be being “L”
level when the external power supply is turned-on.
Ver.2012-11-22
- 27 -
NJU6657
Preliminary
(1-17) LCD driving circuits
LCD drivers consist of 88-common drivers, 272-segment divers.
As shown in “ LCD driving waveform”, LCD driving waveforms are generated by the combination of display data,
common timing signal and internal FR timing signal.
(1-18) Display data latch circuit
The display data latch circuit temporally stores 272-bit display data transferred from the DDRAM in the synchronization
with the common timing signal, and then it transfers these stored data to the segment drivers.
“Display on/off”, “inverse display on/off” and “entire display on/off” instructions control only the contents of this latch
circuit, they can’t change the contents of the DDRAM.
In addition, the LCD display isn’t affected by the DDRAM accuses during its displaying because the data read-out
timing from this latch circuit to the segment drivers is independent of accessing timing to the DDRAM.
(1-19) Line counter and latch signal or latch Circuits
The clock line counter and latch signal to the latch circuits are generated from the internal display clock (CL). The line
address of display data RAM is renewed synchronizing with display clock (CL).
272bits display data are latched in display latch circuits synchronizing with display clock, and then output to the LCD
driving circuits. The display data transfer to the LCD driving circuits is executed independently with RAM access by the
MPU.
(1-20) Display timing generator
The display timing generates the timing signal for the display system by combination of the master clock CL and driving
signal FR ( refer to Fig.2 ) The frame signal FR and LCD alternative signal generate LCD driving waveform on the
2-frame alternative driving method or the n-line inverse driving method.
(1-21) Dummy selection period
Immediately after COM88 has been selected, the selection period equivalent to Display 1 line is provided as dummy.
Therefore, The relation between Display Lline count and Display Duty by setting of Partial Display.
The formula is shown below.
1
Duty=
1
=
(CL+Dummy)
(CL+1)
CL: Display line unit
- 28 -
Ver.2012-11-22
Ver.2012-11-22
n-line CLK
10Line
n-line CLK
10Line
n-line CLK
FR Signal
20 Line
1 Line
2 Line
20 Line
dummy Line
17 Line
16 Line
15 Line
14 Line
13 Line
12 Line
11 Line
10 Line
9 Line
8 Line
7 Line
6 Line
5 Line
19 Line
1/20duty, n-line inverse: 10, Dum m y Period: O N
19 Line
n-line CLK
18 Line
10Line
18 Line
FR Signal
17 Line
16 Line
15 Line
14 Line
n-line CLK
13 Line
12 Line
11 Line
10 Line
9 Line
10Line
8 Line
7 Line
6 Line
5 Line
4 Line
n-line CLK
4 Line
COM end line
3 Line
3 Line
2 Line
1 Line
20 Line
19 Line
18 Line
17 Line
16 Line
15 Line
14 Line
13 Line
12 Line
11 Line
10 Line
9 Line
8 Line
7 Line
6 Line
5 Line
4 Line
3 Line
20 Line
COM end line
1 Line
dummy Line
20 Line
19 Line
18 Line
COM end line
17 Line
16 Line
15 Line
14 Line
13 Line
12 Line
11 Line
10 Line
9 Line
8 Line
7 Line
6 Line
5 Line
4 Line
3 Line
2 Line
1 Line
dummy Line
20 Line
19 Line
18 Line
17 Line
16 Line
15 Line
14 Line
13 Line
12 Line
11 Line
10 Line
9 Line
8 Line
7 Line
6 Line
5 Line
4 Line
3 Line
2 Line
1 Line
dummy Line
COM end line
2 Line
1 Line
dummy Line
20 Line
10Line
19 Line
18 Line
17 Line
16 Line
15 Line
n-line CLK
14 Line
13 Line
12 Line
11 Line
10 Line
9 Line
8 Line
7 Line
6 Line
5 Line
4 Line
3 Line
2 Line
1 Line
20 Line
19 Line
18 Line
17 Line
16 Line
15 Line
14 Line
13 Line
12 Line
11 Line
10 Line
9 Line
8 Line
7 Line
6 Line
5 Line
4 Line
3 Line
2 Line
1 Line
20 Line
19 Line
18 Line
17 Line
16 Line
15 Line
14 Line
13 Line
12 Line
11 Line
10 Line
9 Line
8 Line
7 Line
6 Line
5 Line
4 Line
3 Line
2 Line
1 Line
20 Line
Confidential
NJU6657
Preliminary
(1-22) n-line inversion
NJU6657 sets the number of inversion line of the alternating signal for LCD to the optional values from 2 to 88.
The relation of the alternating signal, n-line inversion and dummy period are shown in below.
1/20duty, n-line inverse: OFF, Dum m y period O FF
FR Signal
COM end line
1/20duty, n-line inverse: OFF, Dum m y period: ON
FR Signal
1/20duty, n-line inverse: 10CLK, Dum m y period: OFF
COM end line
…
10Line
n-line CLK
- 29 -
NJU6657
Preliminary
(1-23) Common timing generation
The common timing is generated by display clock CL (refer to Fig.2)
87
88
1
2
3
4
5
6
7
8
85
86
87
88
1
2
3
4
5
CL
FR
VLCD
V1
C0
V4
VSS
VLCD
V1
C1
V4
VSS
RAM DATA
VLCD
V2
Sn
V3
VSS
Fig.2-1 2-frame alternating drive mode( N-line inverse set OFF)
87
88
1
2
3
4
5
6
7
8
85
86
87
88
1
2
3
4
5
CL
FR
VLCD
V1
C0
V4
VSS
VLCD
V1
C1
V4
VSS
RAM DATA
VLCD
V2
Sn
V3
Vss
Fig.2-2 n-line inverse drive mode (n=7, line inverting register set to 6 )
- 30 -
Ver.2012-11-22
Confidential
NJU6657
Preliminary
(1-24) OSCILLATION CIRCUIT
NJU6657 is equipped with the CR oscllation circuit, and generates internal clocks used for the display timing. The
generating method of the clock selects by the internal oscillation or external clock. When the internal oscillation circuit is
used, Oscillator starts after input of the Internal Oscillator ON/OFF command input. (INTCK=“H”)
In addition, oscillation frequency can be selected by programming the “Internal oscillation frequency control” instruction
So that is possible to optimize the Display duty.
When CLS=”L”, oscillation stops, and display clock is input from the OSC1 terminal.
When external oscillation circuit is operating by setting CLS terminal gives priority more than the operation of the
internal oscillation circuit.
CLS Terminal
L
L
H
H
INTCK
0
1
0
1
Ext. Input Status
Available
Available (Priority)
Not available
Not available
Internal Oscillator
Inactive
Active
Inactive
Active
When external clock input, the divide value is reflection setting by “Interanal oscillation circuit frequency set”
instruction. The divide set is normally using select by the 1 divide (“SH1 to 0 = “00”)
When partial display function used, the divide value changing by divide set instruction.
When frame frequency changes by partial display etc by external clock used.
You shuld be changing external clock frequency and also possible to have you change or to change oscillating frequency
using a divide setup.
The set to each of frequency value is shown in below. ( also in case of External CLK operation.)
Selllect of frame frequency
Boost
Divide
OSC1
( Ext. CLK Input )
Boost CLK
Sellect of display line
Divide
Caluculate of Boost clock frequency
Use to OS4 to OS0 register value.
"Refer to P.60"
DCC2 to 0 register
sellect to divide
value
SH1 to 0
sellect to divide
value
CLS
OS4 to 0 register
sellect to
frequency
Fix to OSC frequency
(Fix to OS4 to OS0 and SH1 to SH0
register value.)
OSC
Frequency
(I t CLK)
CR OSC
INTCK
Caluculate of frequency * refer P56
BLOCK DIAGRAM
End
Ver.2012-11-22
- 31 -
NJU6657
Preliminary
(1-25) Thermal Sensor Circuit
The NJU6657 has the built-in thermal sensor circuit equipped with the pin to output the analog voltage, which represents
the –4.19[mV/℃](typ) temprature gradient. When the TSON=”1” ,from Thermal Sensor command ON/OFF.
The suitable tone LCD display is enabled in a wide temprature range by inputting the electronic control resister value
sent from the MPU for the thermal sensor output value to control the LCD drive voltage.
* Note
When the resistance component R exists between the system GND and the IC’s VSS terminal, the IC’s substrate
potential VSS viewed from the system GND drops as follows:
⊿V=IR ( I: Supply Current by the NJU6657)
VDD
VDDL2
VDDL2
I/F
DD
RAM
Analog
Sensor
TSV
TSVBS
VSS
∆V=IR
- 32 -
System GND
Ver.2012-11-22
Confidential
NJU6657
Preliminary
(1-26)Power supply circuit
The internal power circuits are composed of boost voltage converter, adjust voltage circuit and voltage followers.
Each portion of the internal power circuits is controlled by “Power Control Set” instruction as shown in Table below.
In addition, the combination of power supply circuits is described as shown in Table.
When the External power supply used, the bias voltage of V1 to V4 and VLCD for the LCD should be supplied from
outside, terminals C1+, C1-, C2+, C2-, C3+, C3-, C4+, C5+ and C6+ should be open.
When the Internal power supply used, the stabilize capacitor of V1 to V4 and VLCD should be connection.
A0
0
RDB WRB
1
0
D7
0
*
D6
0
*
D5
1
*
D4
0
*
Power supply combinations
Status
DC1 DC0 VRG
1) All internal power
supply circuit
VF
D3
0
D2
1
D1
0
D0
1
DC1
DC0
VRG
VF
2nd Boost 1st Boost Adjust V
COMMAND
Mode Set
Internal Power Cont.
VF
Ext. Power
1
1
1
1
ON
ON
ON
ON
VEE
0
1
1
1
OFF
ON
ON
ON
VEE
1
0
1
1
ON
OFF
ON
ON
VST1R
0
0
1
1
OFF
OFF
ON
ON
VDCIN
5) Voltage followers only
0
0
0
1
OFF
OFF
OFF
OFF
VLCD
6) External power
supply only
0
0
0
0
OFF
OFF
OFF
OFF
VLCD to V4
2) 1st Boostor,
Adjust voltage circuit and
Voltage followers only
3) 2nd Boostor ,
Adjust voltage circuit and
Voltage followers only
4) Voltage Reg.
and Voltage followers
only
* Capacitor input terminals: C1+,C1-,C2+,C2-,C3+,C3-,C4+,C5+,C6+
* Do not use other combinations except examples in table Power supply combinations.
The internal LCD power supply is designed to drive small LCD panels. Thus, if the IC is used to drive a large panel,
make sure whether it works with the internal power supply or needs an external power supply.
The selections of external components for the LCD bias circuit, the voltage booster and the feedback loop depend on
panel sizes, so make sure what are the best values in the particular application.
Ver.2012-11-22
- 33 -
NJU6657
Preliminary
C4+
C5+
C6+
C3+
C3‐
C1+
C1‐
C2+
C2‐
■BLOCK DIAGRAM (Power Supply)
VEE
VST1
VST1R
1st Boostor
2nd Boostor
VDCOUT
Boost Voltage
Adjust Circuit
Boost Circuit
VDCIN
Adjust Voltage Circuit
VLCD
EVR
V1
Vref.
V2
V3
V4
VF Circuit
- 34 -
Ver.2012-11-22
Confidential
NJU6657
Preliminary
(1-27-1) Voltage Regulator Circuit
VLCD voltage genetator produces the VDCIN voltage.
The NJU6657 has consist of voltage regulator and EVR circuit. The EVR, variable with 400-step, is used to fine-tune
the LCD driving voltage (VLCD) by setting the “EVR Control Instruction”.
(a) EVR
The “EVR Control Instruction” sets 9-bit data into the EVR register to determine the output voltage.
The relation of EVR register and EVR value is shown in table.
ER8
0
0
:
:
1
ER7
0
0
:
:
1
ER6
0
0
:
:
0
ER5
0
0
:
:
0
ER4
0
0
:
:
1
ER3
0
0
:
:
0
ER2
0
0
:
:
0
ER1
0
0
:
:
0
ER0
0
1
:
:
0
EVR
0
1
:
:
400
VLCD
Min.(4.8[V]) ( Default )
:
:
:
Max.(28.8[V])
VLCD = Va+(EVR×ΔVb)
Va = 4.8[V]
ΔVb = 60[mV]
Default
EVR Step
* Example: EVR=250
VLCD = 4.8+(250×0.06) = 19.8[V]
The relation of EVR value and LCD driving voltage is shown in graph.
35
30
VLCD [V]
25
20
15
10
5
0
0
50
100
150
200
250
300
350
400
EVR Set Value
Note1) When using voltage follower circuit, you should be bigger than set to EVR=20(ER=”000010100”,VLCD=6[V])
Ver.2012-11-22
- 35 -
NJU6657
Preliminary
(b) Temperature Gradient Selection Circuit
The circuit is used for selecting the temperature gradient characteristics of the LCD driving voltage.
The set “Temperature Gradient Slect” instruction allows selection of temperature gradient characteristics from 6 stetes.
The Teprature gradient value is refer to shown in table.
Selecting temperature gradient characteristics matching temperature characteristics to be used enables you to configure
the system without an external add-on device for correcting temperature characteristics.
A0
0
RDB WRB
1
0
D7
0
*
D6
1
*
D5
0
*
D4
0
*
D3
1
*
D2
1
TC2
D1
1
TC1
D0
0
TC0
Command
Mode Set
Temprature Gradient Select
TC2
TC1
TC0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
Temperature Gradient Value
[%/℃]
-0.000 ( Default )
-0.050
-0.075
-0.100
-0.125
-0.150
When using this function, you should be reviced LCD driving voltage at Ta=25OC.
* Example) EVR=250, Ta=25OC, Temperature Gradient Value=0,0,0
In case of changing temperature to +40OC.
VLCD = [Va+(EVR×ΔVb)]×[1+(temp-25)×(incline/100)]
= [4.8+(250×0.06)]×[1+(40-25)×(-0.1/100)]
= 19.503 [V]
(1-27-2) Voltage Follower Circuit
Each LCD driving voltage (V1, V2, V3, V4) is generated by the high impedance bleeder resistance buffered by voltage
follower OP-AMP. The bias voltage is selected by the instruction.
A0
0
RDB WRB
1
0
D7
1
*
D6
0
*
D5
1
*
D4
0
*
D3
0
*
D2
0
BS2
D1
1
BS1
D0
0
BS0
BS2
0
0
0
0
1
1
1
BS1
0
0
1
1
0
0
1
BS0
0
1
0
1
0
1
0
Bias Ratio
1/10 (Default)
1/9
1/8
1/7
1/6
1/5
1/4
Command
Mode Set
Bias Ratio Set
The external capacitor connected each of bias terminals needed for stabilizing bias voltage.
And the value of capactors are determined depending on the actual LCD panel display evaluation.
- 36 -
Ver.2012-11-22
NJU6657
Preliminary
(1-27-3) Voltage boost Circuit
(a) 1st Boost Circuit (2-time Boost)
The 1st Boost circuit outputs the positive Voltage(VSS Common) boosted 2 times of VEE-VSS from the VST1 terminal
with connecting the two capacitors between C1+ and C1-, VST1 and VSS.
The purpose of 1st Boost circuit is two reason, 1st is input voltage less than 5V or Using 2nd Boost circuit depends on
voltage shortage. The 1st Boost circuit only used, the VST1 terminal with connecting VDCOUT and VDCIN outside.
-External Capacitor Connection of 1st Voltage Booster
VST1=10V
C1+
C1VST1
+
VEE=5V
VSS=0V
1st Booster
VDCOUT
VDCIN
+
VSS
Ver.2012-11-22
- 37 -
NJU6657
Preliminary
(b) 2nd Booster Circuit ( 6-time Boost)
The 2nd Boost circuit outputs the positive Voltage(VSS Common) boosted 6 times of VST1-VSS from the VDCOUT
terminal with connecting the six capacitors between C2+ and C2-, C3+ and C3-, C4+ and C2-, C5+ and C3-, C6+ and C2-,
and VSS and VDCOUT. The boosting time is selected out of 2 times to 6 by changing the external capacitors connection.
The VDCOUT and VDCIN terminal should be connecting outside.
When the input voltage of voltage boost circuit is over than 5.5V, the 2nd boost circuit should be using only.
The boosted voltage of VSS-VDCOUT
must be 36V less.
Please adjust the input voltage.
VDCOUT=36V
VDCOUT=24V
VST1R=6
VSS=0V
VST1R=6
2nd Booster (4-time Boost)
VSS=0V
2nd Booster (6-time Boost)
- External Capacitor Connection of 2nd Voltage Booster (Power Supply = VST1R)
3-time Boost
2-time Boost
C4+
C2+
C2C6+
C3+
C3C5+
VDCOUT
VDCIN
C4+
C2+
C2C6+
+
C3+
C3C5+
OPEN
VDCOUT
VDCIN
+
C4+
C2C2+
C6+
+
+
C3+
C3C5+
VDCOUT
VDCIN
+
VSS
VSS
5-time Boost
C4+
C2C2+
C6+
C3+
C3C5+
VDCOUT
VDCIN
VSS
- 38 -
4-time Boost
+
+
+
+
VSS
6-time Boost
+
+
+
C4+
C2C2+
C6+
+
C3+
C3C5+
+
VDCOUT
VDCIN
+
+
+
+
+
+
VSS
Ver.2012-11-22
NJU6657
Preliminary
(c) Combination using of 1st boost and 2nd boost circuit
The combination of 1st boost and 2nd boost circuits the positive voltage(VSS common) boosted 4 to 12 times of
VEE-VSS from the VDCOUT terminal with connecting outside the VST1 and VST1R , VDCOUT and VDCIN terminals.
The relation of 1st boost circuit, 2nd boost circuit and Voltage adjust circuit is shown in below.
Connecting
Outside
The boosted voltage of VSS-VDCOUT
must be 36V less.
Please adjust the input voltage.
VDCOUT
VDCIN
2 to 6 x Boost
VLCD
VST1
Ext. Connect
VST1R
2 x Boost
VEE
VSS
1st Booster
Adjust Voltage
2nd Booster
-External Capacitor Connection of Voltage Booster
4-time Boost
6-time Boost
+
C1+
C1VST1
VST1R
VSS
C4+
C2+
C2C6+
C3+
C3C5+
VDCOUT
VDCIN
+
+
OPEN
VSS
+
C3+
C3C5+
+
+
+
C1+
C1VST1
VST1R
VSS
C4+
C2C2+
C6+
+
C3+
C3C5+
+
VDCOUT
VDCIN
+
VSS
C1+
C1VST1
VST1R
VSS
C4+
C2C2+
C6+
+
C3+
C3C5+
+
VDCOUT
VDCIN
VSS
+
+
+
+
VSS
12-time Boost
10-time Boost
Ver.2012-11-22
C1+
C1VST1
VST1R
VSS
C4+
C2+
C2C6+
VDCOUT
VDCIN
+
8-time Boost
+
+
+
+
+
C1+
C1VST1
VST1R
VSS
C4+
C2C2+
C6+
+
C3+
C3C5+
+
VDCOUT
VDCIN
+
+
+
+
+
+
VSS
- 39 -
NJU6657
Preliminary
(d) Adjust voltage boost function
The Adjust voltage boost circuit generates VST1R voltage by Adjust voltage boost set instruction.
Register value(VU2 to VU0) should be setting of according to use 2nd Booster condition.
When the this function used, using of 2nd Boost circuit and combination of 1st and 2nd Boost circuits.
The combination of the auto control function can’t used.
In using 2nd boost circuit only, the input voltage input to VST1 terminal. In using combination of 1st boost and 2nd
boost circuit used, the input voltage input to VEE terminal. In this time , each of the connect to capacitor between
VST1, VST1R and VSS terminals.
This function controls 2nd booster output voltage less than Maxmum voltage (36V)
If this function is used, it can set up VEE and VST1 voltage without considering Maxmum voltage.
This function is control by set to command “Adjust voltage boost instruction”.
The register value (VU2 to 0) set are before starting of 2nd boost circuit.
A0
0
RDB WRB
1
0
VU2
0
0
0
0
1
1
D7
1
*
D6
0
*
VU1
0
0
1
1
0
0
D5
0
*
VU0
0
1
0
1
0
1
D4
0
*
D3
1
*
D2
1
D1
0
D0
1
VU2
VU1
VU0
Instruction
Mode Set
Adjust Boost Voltage
2nd Booster
OFF ( Default )
2-time
3-time
4-time
5-time
6-time
The relation of 1st boost circuit, 2nd boost circuit and Voltage adjust circuit is shown in below.
Connecting
Outside
VDCOUT
VDCIN
2 to 6 time Boost
VLCD voltage
VST1
Int. REG
VST1R
VEE
VSS
2-time Boost
1st Booster
2nd Booster
Adjust voltage
The output voltage of a VST1R terminal generates voltage according to the number of stages of 2nd-Boost circuit.
The 2nd-Boost circuit controls less than maximum voltage. Therefore, in case of VEE=5.5V or VST1=15V condition,
VDCOUT voltage is less than 36V.
- 40 -
Ver.2012-11-22
NJU6657
Preliminary
- External Capacitor Connection of Voltage Booster
4-time Boost
6-time Boost
+
C1+
C1VST1
VSS
VST1R
C4+
C2+
C2C6+
C3+
C3C5+
VDCOUT
VDCIN
+
+
+
OPEN
VSS
+
C3+
C3C5+
+
+
+
+
C1+
C1VST1
VSS
VST1R
C4+
C2C2+
C6+
+
C3+
C3C5+
+
VDCOUT
VDCIN
+
VSS
C1+
C1VST1
VSS
VST1R
C4+
C2C2+
C6+
+
C3+
C3C5+
+
VDCOUT
VDCIN
VSS
+
+
+
+
+
VSS
12-time Boost
10-time Boost
Ver.2012-11-22
C1+
C1VST1
VSS
VST1R
C4+
C2+
C2C6+
VDCOUT
VDCIN
+
8-time Boost
C1+
C1VST1
VSS
VST1R
C4+
C2C2+
C6+
+
+
+
C3+
C3C5+
+
VDCOUT
VDCIN
+
+
+
+
+
+
+
+
+
+
+
VSS
- 41 -
NJU6657
Preliminary
(1-27-4)Discharge circuit
The NJU6657 incorporates a discharge circuit.
Discharge circuit is used to discharge out of the stabilizing capacitors placed on the VDCOUT, VDCIN, VLCD, V1 to
V4, VST1 and VST1R. This instruction prevents the unknown display at the power supply off. (refer to shown below)
VDCIN
VDCOUT
VDCIN
External
C
t
Adjust
Voltage
VLCD
VST1
Adjust
Booster
VST1R
1st
Boost
V1
VF
VEE
1st
Boost
V2
V3
V4
VSSE
VSS
(1-27-5)Attention of Power ON/OFF
To protect the LSI from overcurrent, the following sequences must be maintained to turn on and off the power supply.
(ⅰ) Power ON/OFF in using external LCD supply
・Power ON
First “VDD and VDDL ON”, next “Reset by RESb”, then “External LCD power supply ON”. When using only
internal voltage converter, first “VDD and VDDL ON”, next “Reset”, then “VDCIN ON”.
・Power OFF
First “Reset by RESb” or “Power save” instruction” to isolate external LCD bias voltage, next “VDD OFF”. For
more safety, placing a resistor in series on the VLCD or VDCIN line are recommended. That resistance is usually
between 50Ω
and 100Ω.
The value of resistance is fixed with the result of actual LCD display evaluation.
(ⅱ) Power ON/OFF in using internal LCD supply
・Power ON
First “VDD, VDDL and VEE ON”, next “Reset by RESb”, then “Internal LCD Power supply ON”. Be sure to
excute the “Display ON” instruction later than the completion of this power ON sequence. Otherwise, unexpected
pixels may be turned on instantly.
・Power OFF
First “Reset by RESb or “Power save” instruction, next “Dispcharge ON” next “VEE OFF” then “VDD OFF”. If
using different power sources for the VDD and the VEE individually, the VEE must be turned off after that, the VDD
can be turned off, waiting until the LCD bias voltgae (VLCD, V1, V2, V3 and V4) drop below the threshold level of
LCD pixels.
- 42 -
Ver.2012-11-22
NJU6657
Preliminary
-External Components for LCD Power Supply 1) Using Only Internal LCD Power Supply
(VEE=VDD, 12-time Boost)
C1+
+
CA2
2) Using Only Internal LCD Power Supply
(VEE=VDD, 12-time Boost, Adjust Boost circuit.)
C1VST1
VDD
VDCOUT
CA1
+
VDCOUT
CA1×2
+
C4+
+
C6+
VSS
VSSE
VSSA
C2-
CA2×3
+
C4+
+
C6+
C3+
+
CA2×2
C3-
C2+
+
VSSE
NJU6657
C2-
CA2×3
+
VST1R
+
NJU6657
C2+
VEE
VDCIN
+
VSS
+
CA1×2
VDD
+
VST1R
+
VST1
+
VEE
VDCIN
+
C1-
CA1×2
+
CA1×2
C1+
+
CA2
VSSA
C3+
+
CA2×2
C3-
+
+
C5+
CA3×5
C5+
CA3×5
VLCD
+
V1
+
V2
+
V3
+
+
V4
VLCD
+
V1
+
V2
+
V3
+
+
V4
Reference Values
CA1
1.0 ~ 4.7µF
CA2
1.0 ~ 4.7µF
CA3
0.47 ~ 1µF
Note 1) B grade capacitor is recommended for CA1 to CA3. Make sure what is the best capacitor value in the
particular application.
Note 2) Parasitic resistance on the power supply lines (VSS, VDD, VSSE, VEE, VDCIN, VLCD, V1 to V4) reduces
step-up efficiency of the voltage booster, and may have an impact on the LSI’s operation and display quality.
Note 3) When using 1st and 2nd boost circuits, the capactor value (connect between C1+/C1- and VST1 terminals) should
be bigger than capacitor value of 2nd boost circuit. ( Recommendation is 3-times. )
Ver.2012-11-22
- 43 -
NJU6657
Preliminary
-External Components for LCD Power Supply
3) Using Internal LCD Power Supply within
1st Boost, Adjust Voltage Circuit, VF Circuit
(VEE=VDD)
C1+
+
CA2
4) Using Internal LCD Power Supply within
2nd Boost, Adjust Voltage Circuit, VF Circuit.
(6-time Boost)
C1+
C1VDD
VST1
C1-
CA1×2
VDD
VST1
+
VDCOUT
VEE
+
+
External
Power
Circuit
CA1×2
VDCOUT
VDCIN
VST1R
VSS
C4+
C6+
VSSA
C2-
CA2×3
+
C4+
+
C6+
C3+
C3-
C2+
+
VSSE
NJU6657
C2-
VSS
VSSE
NJU6657
C2+
VEE
VDCIN
+
VST1R
+
CA1
CA1
VSSA
C3+
+
CA2×2
C3+
C5+
CA3×5
C5+
CA3×5
VLCD
+
V1
+
V2
+
V3
+
+
V4
VLCD
+
V1
+
V2
+
V3
+
+
V4
Reference Values
CA1
1.0 ~ 4.7µF
CA2
1.0 ~ 4.7µF
CA3
0.47 ~ 1µF
Note 1) B grade capacitor is recommended for CA1 to CA3. Make sure what is the best capacitor value in the
particular application.
Note 2) Parasitic resistance on the power supply lines (VSS, VDD, VSSE, VEE, VDCIN, VLCD, V1 to V4) reduces
step-up efficiency of the voltage booster, and may have an impact on the LSI’s operation and display quality.
- 44 -
Ver.2012-11-22
NJU6657
Preliminary
-External Components for LCD Power Supply
5) Using Internal LCD Power Supply within
2nd Boost, Adjust Voltage Circuit, VF Circuit
(6-time Boost, Adjust Boost Voltage circuit)
6) Using Internal LCD Power Supply within
Adjust Voltagae Circuit, VF Circuit
(VDCIN Ext. Input)
C1+
+
External CA2
Power
Circuit
C1+
C1VDD
VST1
C1-
CA1
VDD
VST1
+
VDCOUT
VEE
+
VDCIN
+
CA1×2
+
External
Power
Circuit
VDCOUT
VST1R
C2-
CA2×3
+
C4+
+
C6+
+
CA2×2
VSS
VSSE
C2+
VSSA
C2C4+
C6+
C3+
C3+
C3-
C3-
VSSE
NJU6657
C2+
NJU6657
VSS
+
VEE
VDCIN
VST1R
+
CA1
VSSA
+
C5+
C5+
CA3×5
CA3×5
VLCD
+
V1
+
V2
+
V3
+
+
V4
VLCD
+
V1
+
V2
+
V3
+
+
V4
Reference Values
CA1
1.0 ~ 4.7µF
CA2
1.0 ~ 4.7µF
CA3
0.47 ~ 1µF
Note 1) B grade capacitor is recommended for CA1 to CA3. Make sure what is the best capacitor value in the
particular application.
Note 2) Parasitic resistance on the power supply lines (VSS, VDD, VSSE, VEE, VDCIN, VLCD, V1 to V4) reduces
step-up efficiency of the voltage booster, and may have an impact on the LSI’s operation and display quality.
Ver.2012-11-22
- 45 -
NJU6657
Preliminary
7. Using Only Internal Voltage follower Circuit.
8. Using Only External LCD Power Supply
C1+
C1+
C1VDD
VST1
C1-
CA1
CA1
VDD
VST1
+
VDCOUT
+
VEE
VDCOUT
VDCIN
VDCIN
VST1R
VST1R
VSS
C4+
C6+
VSSA
C2C4+
C6+
C3+
C3+
C3-
C3-
C5+
C5+
VLCD
CA3×4
External
Power
Circuit
C2+
V2
+
V3
+
+
V4
VSSA
VLCD
V1
+
VSSE
NJU6657
C2-
VSS
VSSE
NJU6657
C2+
VEE
External
Power
Circuit
V1
V2
V3
V4
Reference Values
CA1
1.0 ~ 4.7µF
CA2
1.0 ~ 4.7µF
CA3
0.47 ~ 1µF
Note 1) B grade capacitor is recommended for CA1 to CA3. Make sure what is the best capacitor value in the
particular application.
Note 2) Parasitic resistance on the power supply lines (VSS, VDD, VSSE, VEE, VDCIN, VLCD, V1 to V4) reduces
step-up efficiency of the voltage booster, and may have an impact on the LSI’s operation and display quality.
- 46 -
Ver.2012-11-22
NJU6657
Preliminary
(1) Instruction SetThe NJU6657 distinguishes the signal on the data bus D0 to D7 as an instruction by combination of A0, RDB and
WRB(R/W). The decode of the instruction and execution performs with only high speed Internal timing without relation
to the external clock. In case of serial interface, the data input as MSB(D7) first serially. The Table. 4-1, 4-2 shows the
instruction codes of the NJU6657.
Table. 4-1 Instruction table (1/2)
(*: Don’t Care)
Instruction code
Instruction
A0
RDb
WRb
(1)
Display ON/OFF
0
1
0
(2)
Initial Display Line Set
0
1
0
(3)
Page Address Set
0
0
(4)
1
1
Defoult
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
1
1
1
D
1
0
0
0
1
0
1
0
*
SL6
SL5
SL4
SL3
SL2
SL1
SL0
1
0
1
1
0
0
0
1
*
*
*
*
PA3
PA2
PA1
PA0
0
0
0
1
0
0
1
1
*
*
*
*
CA3
CA2
CA1
CA0
0
0
0
1
0
1
0
0
*
*
*
CA8
CA7
CA6
CA5
CA4
0
0
0
Description
D0=0:OFF, D0=1:ON
00H
SL6 to 0: Initial Display Line Address
0H
PA3 to 0: Page Address of DDRAM
00H
Column Address Set
CA8 to 0: Column Address of DDRAM
0
1
00H
0
(5)
Status Read
0
0
1
Status
-
(6)
Write Display Data
1
0
0
Write Data
-
Write the data into the Display Data RAM
(7)
Read Display Data
1
0
1
Read Data
-
Read the data from the Display Data
RAM
(8)
ADC Select
0
1
0
1
0
1
0
0
0
0
ADC
0
ADC: Set the DDRAM vs Segment
(9)
Common Direction Select
0
1
0
1
1
0
0
0
0
0
INV
000
0
1
0
1
0
1
0
0
1
1
REV
0
REV: Inverse the ON and OFF Display
0
ALLON: Whole Display Turns ON
(10) Normal or Inverse of ON/OFF Set
(11) Whole Display ON/OFF
LCD Duty Ratio Set
0
1
0
0
1
0
1
0
1
0
0
1
0
ALL
ON
1
0
1
1
1
1
0
1
*
DN6
DN5
DN4
DN3
DN2
DN1
DN0
1
0
1
1
1
1
1
0
*
DS6
DS5
DS4
DS3
DS2
DS1
DS0
1
1
1
0
0
1
0
NLS
0
0
1
1
0
1
1
0
48H
Partial Select Function
DN5 to 0: LCD Duty Ratio
DS5 to 0: COM Start Position
(12)
Common Start Position Set
0
1
00H
0
(13) n-line Inverse Drive Set
0
1
0
(14) n-line Inverse Drive Register Set
0
1
0
(15) Dummiy width Set
INV: Common Direction
0
NLS: n-line Inverse Drive Set
-
NL6 to 0: Set the number of inverse drive
line.
MIX: n-line inverse + 2-frame
MIX
NL6
NL5
NL4
NL3
NL2
NL1
NL0
0
0
1
1
0
0
ST
DUM
00
DUM: Dummy Width ON/OFF
ST: Segment Output Status
(16) Read Modify Write Set
0
1
0
1
1
1
0
0
0
0
0
-
Read Modify Write Set
(17) End
0
1
0
1
1
1
0
1
1
1
0
-
Read Modify Write Reset
Ver.2012-11-22
- 47 -
NJU6657
Preliminary
table. 4-2 Instruction table (2/2)
(*: Don’t Care)
Instruction Code
Instruction
A0
(18)
Internal Oscillation Circuit
On/Off
0
1
0
(19)
Oscillation Circuit Frequency
Set
0
1
0
(20) LCD Bias Ratio Set
(21) Temprature Gradient Set
(22) Power Control Set
(23) EVR Register Set (Upper Bit)
(24) EVR Register Set (Lower Bit)
Default
RDb WRb
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
1
0
1
INT
CK
0
0
0
0
0
0
1
1
1
1
1
INTCK: Oscillation Circuit
ON/OFF
SH1 to 0: Divide Set
101000
OS3 to 0: Oscillation Circuit
0
SH1 SH0 OS4 OS3 OS2 OS1 OS0
Frequency ON/OFF
1
0
1
1
1
1
1
1
0
1
0
0
0
1
0
*
*
*
*
*
0
1
0
0
1
*
*
*
*
*
0
0
1
0
0
*
1
Description
0
1
1
*
*
1
0
0
0
*
*
*
1
0
0
000
TC2 to 0: Temprature Gradient of
LCD Drive Voltgae
0000
DC1 to 0: Boost ON/OFF
VRG: Adjust Voltage ON/OFF
VF: VF ON/OFF
00h
ER8 to 4: EVR Register Set
(Upper-4bit)
0H
ER3 to 0: EVR Register Set
(Lower-4bit)
TC2 TC1 TC0
1
0
1
0
*
BS2 to 0: LCD Bias Ratio Set
0
0
*
000
BS2 BS1 BS0
DC1 DC0 VRG VF
0
0
0
1
0
ER8 ER7 ER6 ER5 ER4
0
0
0
1
0
0
*
*
*
*
ER3 ER2 ER1 ER0
(25) EVR Step Up
0
1
0
1
0
0
0
0
0
1
1
-
EVR Step Up
(26) EVR Step Down
0
1
0
1
0
0
0
0
1
0
0
-
EVR Step Down
1
0
0
0
1
1
0
1
0h
*
*
*
*
*
1
0
0
0
0
*
*
*
*
*
(27) Boost Voltage Control Set
(28) Boost Clock Set
0
1
VU2 to 0: 2nd Boost Set
VU2 VU1 VU0
1
1
0
0
101
DCC2 to 0: Boost Clock Set
DCC2 DCC1 DCC0
(29) Thermo Sensor ON/OFF
0
1
0
0
0
1
0
1
0
0
TS
ON
0
TSON: Thermo Sensor ON/OFF
(30) Discharge ON/OFF
0
1
0
1
1
1
0
1
0
1
DIS
0
DIS: Discharge ON/OFF
(31) Address Home
0
1
0
1
1
1
0
0
0
1
0
-
Initialize of PA and CA value
(32) Power Save
0
1
0
1
1
1
1
1
0
0
0
-
Set to Power Save
(33) Power Save Reset
0
1
0
1
1
1
1
0
0
0
1
-
Power Save Reset
(34) Low Voltage Operation Mode
0
1
0
0
1
1
0
0
1
1
0
0
*
*
*
*
*
*
*
LVM
LVM: Set to Low Voltage
Operation
- 48 -
Ver.2012-11-22
NJU6657
Preliminary
(1-1) Explanation of Instruction Code
1. Display ON/OFF
This instruction selects display turn-on or turn-off regardless of the contents of the DDRAM.
A0
0
RDB WRB
1
0
D
D7
1
D6
0
D5
1
D4
0
D3
1
D2
1
D1
1
D0
D
COMMAND
Display ON/OFF
0: Display OFF
1: Display ON
2. Initial Display Line Set ( refer to ■FUNCTIONAL DESCRIPTION Fig.1 Display data RAM (DDRAM) Map )
This instruction specifies the DDRAM line address which correponds to the COM0 position.
By means of repeating this instruction, the initial display line address will be dynamically changed; it means smooth
display scrolling will be enabled.
In this time, DDRAM data are unchanged.
A0
0
RDB WRB
1
0
SL6
0
1
:
:
1
D7
1
*
SL5
0
0
:
:
0
D6
0
SL6
SL4
0
0
:
:
1
D5
0
SL5
SL3
0
0
:
:
0
D4
0
SL4
D3
1
SL3
SL2
0
0
:
:
1
D2
0
SL2
SL1
0
0
:
:
1
D1
1
SL1
SL0
0
1
:
:
1
D0
0
SL0
COMMAND
Mode Set
Initial Display Line Set
Line Address (HEX)
00H ( Default )
01H
:
:
57H
3. Page Address Set ( refer to ■FUNCTIONAL DESCRIPTION Fig.1 Display data RAM (DDRAM) Map )
In order to access to the DDRAM for writing or reading display data, both “page address set” and “column
address set” instructions are required before accessing.
The change of page address is not affected to the display.
A0
0
RDB WRB
1
0
P3
0
0
:
:
1
Ver.2012-11-22
D7
1
*
D6
0
*
P2
0
0
:
:
0
D5
1
*
D4
1
*
P1
0
0
:
:
1
D3
0
P3
D2
0
P2
P0
0
1
:
:
0
D1
0
P1
D0
1
P0
COMMAND
Mode Set
Page Address Set
Page
0 ( Default )
1
:
:
10
- 49 -
NJU6657
Preliminary
4. Column Address Set ( refer to ■FUNCTIONAL DESCRIPTION Fig.1 Display data RAM (DDRAM) Map )
As abobe-mentioned, in order to access to the DDRAM for writing or reading display data, it is necessary to execute
both “page address set” and “column address set” before accessing.
Once the column address is set, it will automatically increment (+1) whenever the DDRAM will be accessed, so that the
DDRAM will be able to be continuously accessed without “column address set” instruction.
A0
0
RDB WRB
1
0
D7
0
*
D6
0
*
D5
0
*
D4
1
*
D3
0
CA3
D2
0
CA2
D1
1
CA1
D0
1
CA0
COMMAND
Mode Set
Column Address Set 1
A0
0
RDB WRB
1
0
D7
0
*
D6
0
*
D5
0
*
D4
1
CA8
D3
0
CA7
D2
1
CA6
D1
0
CA5
D0
0
CA4
COMMAND
Mode Set
Column Address Set 2
CA8
0
0
:
:
1
CA7
0
0
:
:
0
CA6
0
0
:
:
0
CA5
0
0
:
:
0
CA4
0
0
:
:
0
CA3
0
0
:
:
1
CA2
0
0
:
:
1
CA1
0
0
:
:
1
CA0
0
1
:
:
1
Column Address (HEX)
00H ( Default )
01H
:
:
10FH
5. Status Read
This instruction reads out the internal status regarding “busy flag”, “ADC select”, “Display on/off”, “Power save”
“2nd Booster on/off”, “1st Booster on/off.”, “Voltage regulator on/off” and “Voltage follower on/off”
< Status Read Command >
A0 RDB WRB
0
0
1
D7
D6
D5
D4
D3
D2
D1
D0
BF
ADC
D
PO
DC1
DC0
VRG
VF
BF
0: The instruction can be input.
1: operating status
ADC
0: Clockwise Output (Normal)
1: Counterclockwise Output (Inverse)
D
0: Display OFF
1: Display ON
PO
0: Normal
1: Power Seve
DC1
0: 2nd Boost Circuit OFF
1: 2nd Boost Circuit ON
DC0
0: 1st Boost Circuit OFF
1: 1st Boost Circuit ON
VRG
0: Adjust Voltage Circuit OFF
1: Adjust Voltage Circuit ON
VF
0: VF Circuit OFF
1: VF Circuit ON
- 50 -
COMMAND
Status Read
Ver.2012-11-22
NJU6657
Preliminary
6. Display Data Write
This instruction writes display data into the selected column address on the DDRAM.
The column address automatically increments (+1) whenever the display data is written by this instruction, so that this
instruction can be continuously issued without “column address set” instruction.
A0
1
RDB WRB
1
0
D7
D6
D5
D4
D3
Write Data
D2
D1
D0
COMMAND
Display Data Write
7. Display Data Read
This instruction reads out the display data stored in the selected column address on the DDRAM.
The column address automatically increments (+1) whenever the display data is read out by this instruction, so that this
instruction can be continuously issued without “column address set” instruction.
After the “column address set” instruction, adummy read will be required, please refer to the (*-*).
In case of using serial interface mode, this instruction can’t be used.
A0
1
RDB WRB
0
1
D7
D6
D5
D4
D3
Read Data
D2
D1
D0
COMMAND
Display Data Read
8. ADC Select
This instruction selects segment driver direction.
The correspondence between the column address and segment driver direction is shown in Fig.1.
This function reduces the restrictions on the IC position of an LCD module.
A0
0
RDB WRB
1
0
ADC
D7
1
D6
0
D5
1
D4
0
D3
0
0: Clockwise Output (Normal)
1: Counterclockwise Output (Inverse)
D2
0
D1
0
D0
COMMAND
ADC select
ADC
Segment Driver S0 to S271 ( Default )
Segment Driver S271 to S0
9. Common Driver Direction Select
This instruction selects common driver direction.
A0
0
RDB WRB
1
0
INV
Ver.2012-11-22
D7
1
0: Normal
1: Inverse
D6
1
D5
0
D4
0
D3
0
D2
0
D1
0
D0
INV
COMMAND
Common Driver Direction
Common driver direction C0 to C88 (Default )
Common driver direction C88 to C0
- 51 -
NJU6657
Preliminary
10. Inverse Display ON/OFF
This instruction inverses the status of turn-on or turn-off of entire LCD pixels. It doesn’t change the contents of the
DDRAM.
A0
0
RDB WRB
1
0
REV
D7
1
D6
0
D5
1
0: Normal
1: Inverse
D4
0
D3
0
D2
1
D1
1
D0
REV
COMMAND
Normal / Inverse
RAM data “1” correspond to “ON” ( Default )
RAM data “0” correspond to “ON”
11. Whole Display ON/OFF
This instruction turns on entire LCD pixels regardless the contents of the DDRAM. It doesn’t change the
contents of DDRAM.
This instruction should be performed prior to the “Inverse display ON/OFF” instruction.
A0
0
RDB WRB
1
0
ALLON
D7
1
D6
0
D5
1
D4
0
D3
0
D2
1
D1
0
D0
ALL
ON
COMMAND
Whole Display ON/OFF
0: Normal Display
(Whole Display OFF) ( Default )
1: Whole Display Turns ON (Whole Display ON)
12. Partial Select
The partial display is executed by combining the Display Duty Ratio with the Display Start Position instruction.
A0
0
RDB WRB
1
0
D7
D6
D5
D4
D3
D2
D1
D0
1
*
0
DN6
1
DN5
1
DN4
1
DN3
1
DN2
0
DN1
1
DN0
A0
0
RDB WRB
1
0
D7
D6
D5
D4
D3
D2
D1
D0
1
*
0
DS6
1
DS5
1
DS4
1
DS3
1
DS2
1
DS1
0
DS0
DN6
DN5
DN4
DN3
DN2
DN1
DN0
0
0
:
:
1
0
0
:
:
0
0
0
:
:
0
0
0
:
:
1
0
0
:
:
0
0
0
:
:
0
0
1
:
:
0
COMMAND
Mode Set
Duty Ratio
COMMAND
Mode Set
COM Start Potision
Duty Ratio
1/16
1/17
:
:
1/88 ( Default )
DS5
DS4
DS3
DS2
DS1
DS0
COM Start Position
0
0
0
0
0
0
0
COM0(COM87) ( Default )
0
0
0
0
0
0
1
COM1(COM86)
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
1
0
1
0
1
1
1
COM87(COM0)
( ): INV=”1” set by “Common Direction Select” instruction
Duty is changed automatically when Partial Display execution. But VLCD voltage and frame frequency are not changed.
The optimum conditions should fix refering the result of actual display.
DS6
- 52 -
Ver.2012-11-22
NJU6657
Preliminary
13. n-line Inverse ON/OFF
This instruction sets n-line inversion.
A0
0
RDB WRB
1
0
D7
1
D6
1
NLS
D5
1
D4
0
D3
0
D2
1
D1
0
D0
NLS
COMMAND
n-line Inverse ON/OFF
0: 2-frame alternating drive mode. ( Default )
1: N-line inverse drive mode.
14. n-line Inverse Drive Register Set
This instruction specifies the number of n-line. The line count to be set is 2 to 88.
In case of Mix=”1”, the driving wave form is Mixed. (n-line Inverse + 2-frame alternating drive mode.)
A0
0
RDB WRB
1
0
D7
0
0
D6
0
NL6
D5
1
NL5
D4
1
NL4
D3
0
NL3
D2
1
NL2
NL6
NL5
NL4
NL3
NL2
NL1
NL0
0
0
:
:
1
1
0
0
:
:
0
0
0
0
:
:
1
1
0
0
:
:
0
0
0
0
:
:
1
1
0
0
:
:
0
1
0
1
:
:
1
0
D1
1
NL1
D0
0
NL0
COMMAND
Mode Set
n-line Inverse Register Set
Inverse Lines
2 ( Default )
3
:
:
87
88
15. Dummy period
This instruction specifies the insert position of dummy period.
In addition, SEG outputs of dummy period are made by ST register
A0
0
RDB WRB
1
0
D7
0
D6
0
D5
1
D4
1
D3
0
D2
0
D1
ST
D0
DUM
COMMAND
Dummy Period Set
DUM
0: 1/CL Duty ( Default )
1: 1/ (CL+1dummy) Duty
ST
0: All segment drivers output non-active.. ( Default )
1: All segment drivers output active.
CL: Display line count
Ver.2012-11-22
- 53 -
NJU6657
Preliminary
16. Read Modify Write
This instruction controls column address increment.
By using of this instruction, the column address can’t increment when read operation but it can increment when write
operation. This status will be continued until the below-mentioned “end” instruction will be issued.
This instruction can reduce the load of MPU, during the display data in specific DDRAM area is repeatedly changed for
cursor blink or others.
A0
0
RDB WRB
1
0
D7
1
D6
1
D5
1
D4
0
D3
0
D2
0
D1
0
D0
0
COMMAND
Read Modify Write
Note) In this “Read Modify Write” mode, out of display data “Read” / “Write”, any instructions except “Column Address
Set” can be executed
- The Sequence of Cursor Blink Display
Page Address Set
Set to the Start Address of
cursor Display
Column Address Set
Read Modify Write
Dummy Read
Start the Read Modify Write
The data is igonored
Column Counter doesn’t increase
Dummy Read
Data inverse by MPU
Data Write
Column Counter increase
Dummy Read
Column Counter doesn’t increase
Data Read
Column Counter doesn’t increase
Data Write
Column Counter increase
Dummy Read
Column Counter doesn’t increase
Data Read
Column Counter doesn’t increase
Data Write
Column Counter increase
Repeating
End
No
End the Read Modify Write
Finish？
Yes
- 54 -
Ver.2012-11-22
NJU6657
Preliminary
17. End
The “end” instruction cancels the read modify write mode and makes the coulumn address return to the initial value just
before “read modify write” is atarted
A0
0
RDB WRB
1
0
D7
1
D6
1
D5
1
D4
0
D3
1
D2
1
D1
1
D0
0
COMMAND
End
Return
Column
Address
N
N+1
N+2
･ ･ ･ ･
N+3
N+m
Read modify write
N
End
18. Internal Oscillator Circuit ON/OFF
This command starts the internal oscillator circuit operation. (INTCLK = “1”)
This setting is effective when CLS=”1”.
A0
0
RDB WRB
1
0
D7
1
D6
0
D5
1
INTCLK
Ver.2012-11-22
D4
0
D3
1
D2
0
D1
1
D0
INT
CLK
COMMAND
Oscillator Control
0: Internal OSC OFF ( Default )
1: Internal OSC ON
- 55 -
NJU6657
Preliminary
19. Internal Oscillator Circuit Frequency Select
This instruction sets the internal oscillator circuit frequency.
A0
0
OS4
RDB WRB
1
0
OS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
OS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
OS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D7
D6
D5
D4
D3
D2
D1
D0
0
*
1
SH1
0
SH0
1
OS4
1
OS3
1
OS2
1
OS1
1
OS0
OS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
SH1
SH0
0
0
1
1
0
1
0
1
COMMAND
Mode Set
OSC Frequency Control
Divide Frequency Select
fOSC
fOSC/2
fOSC/4 ( Default )
fOSC/8
OS4~0
(HEX)
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
10h
11h
12h
13h
fOSC
82.4
88.0
93.4
99.2
104.7
110.3
115.2
120.8
126.0
131.6
137.0
142.3
147.5
153.1
158.5
163.9
169.0
174.4
179.4
184.9
Internal Frequency fOSC [kHz]
fOSC/2
fOSC/4
41.2
20.6
22.0
44.0
23.4
46.7
24.8
49.6
26.2
52.4
27.6
55.1
28.8
57.6
30.2
60.4
31.5
63.0
32.9
65.8
34.2
68.5
35.6
71.2
36.9
73.8
38.3
76.5
39.6
79.2
41.0
81.9
42.2 (Default)
84.5
43.6
87.2
44.9
89.7
46.2
92.4
fOSC/8
10.3
11.0
11.7
12.4
13.1
13.8
14.4
15.1
15.8
16.4
17.1
17.8
18.4
19.1
19.8
20.5
21.1
21.8
22.4
23.1
* The table above showns the values at 25OC and without of manufacturing variations in the internal oscillation circuit
frequency.
* The frame frequency changed automatically when Partial Display execution. The optimum conditions should be select
refer to formula is shown below.
◆ Formula of OSC Frequency
When using internal OSC Circuit.
Dummy Period Set: DUM=’0’
OSC frequency fOSC = fFR× (CL ×6)
fFR: frame frequency
CL: Display line count
Dummy Period Set: DUM=’1’
OSC Frequency fOSC = fFR× { (CL+1dummy) ×6 }
fFR: frame frequency
CL: Display line count
- 56 -
Ver.2012-11-22
NJU6657
Preliminary
In External clock operation, the external clock input to OSC1 terminal.
The formula is shown below.
Condition: DUM=’0’
External clock frequency fOSC = n×fFR× (CL ×6)
n: Divide count
fFR: Frame frequency
CL: Display line
Condition: External clock Input, DUM=”1”
External Clock Frequency fOSC = n×fFR× { (CL+1dummy) ×6 }
n: Divide count
fFR: Frame frequency
CL: Display line
The relationship between OSC register (OS4 to OS0) and OSC frequency are shownbelow.
200
180
OSC frequency [kHz]
160
140
120
100
80
60
40
20
13h
12h
11h
10h
Fh
Eh
Dh
Ch
Bh
Ah
9h
8h
7h
6h
5h
4h
3h
2h
1h
0h
0
OS4 to OS0
Ver.2012-11-22
- 57 -
NJU6657
Preliminary
20. Bias Select
This instruction selects LCD bias value.
A0
0
RDB WRB
1
0
D7
1
*
D6
0
*
D5
1
*
D4
0
*
NL2
0
0
0
0
1
1
1
D3
0
*
D2
0
BS2
D1
1
BS1
NL1
NL0
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Bias Ratio
1/10 ( Default )
1/9
1/8
1/7
1/6
1/5
1/4
D0
0
BS0
COMMAND
Mode Set
Bias Select
21. Temperature Gradient Set
This instruction is used to set the temperature gradient characteristics of the VLCD voltage output from the internal
power supply circuit.
A0
0
RDB WRB
1
0
D7
0
*
D6
1
*
D5
0
*
D4
0
*
Temperature Gradient [%/℃]
-0.000 ( Default )
-0.050
-0.075
-0.100
-0.125
-0.150
TC2
TC1
TC0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
D3
1
*
D2
1
TC2
D1
1
TC1
D0
0
TC0
COMMAND
Mode Set
Temperature Gradient Set
22. Power Control Set
This instruction controls the status of internal power circuits. Please refer to the (1-24) internal power circuit more
detail.
A0
0
RDB WRB
1
0
D7
D6
D5
D4
D3
D2
D1
D0
0
*
0
*
1
*
0
*
0
DC1
1
DC0
0
VRG
1
VF
DC1
0: 2nd Boost OFF ( Default )
1: 2nd Boost ON
DC0
0: 1st Boost OFF ( Default )
1: 1st Boost ON
VRG
0: Adjust Voltage Circuit OFF ( Default )
1: Adjust Voltage Circuit ON
VF
0: V/F Circuit OFF ( Default )
1: V/F Circuit ON
COMMAND
Mode Set
Internal Power Supply Control
The internal power supply must be Off when external power supply using.
*The wait time depends on the C4 to C8, COUT capacitors, and VDD and VLCD Voltage.
Therefore it requires the actual evaluation using the LCD module to get the correct time.
- 58 -
Ver.2012-11-22
NJU6657
Preliminary
23. EVR Register Set (Upper bit)
The EVR values is controled in 400 steps by setting the combination of “EVR register set” instruction..
A0
0
RDB WRB
1
0
D7
1
*
D6
0
*
D5
0
*
D4
0
ER8
D3
0
ER7
D2
0
ER6
D1
0
ER5
D0
1
ER4
COMMAND
Mode Set
EVR Register Set 2
24. EVR Register Set (Lower bit)
The EVR values is controled in 400 steps by setting the combination of “EVR register set” instruction..
A0
0
RDB WRB
1
0
D7
1
*
D6
0
*
D5
0
*
D4
0
*
D3
0
ER3
D2
0
ER2
D1
0
ER1
D0
1
ER0
COMMAND
Mode Set
EVR Register Set 1
The combination of EVR register at shown in below.
ER8
0
0
:
:
1
ER7
0
0
:
:
1
ER6
0
0
:
:
0
ER5
0
0
:
:
0
ER4
0
0
:
:
1
ER3
0
0
:
:
0
ER2
0
0
:
:
0
ER1
0
0
:
:
0
ER0
0
1
:
:
0
EVR
0
1
:
:
400
VLCD
Min. ( Default )
:
:
:
Max.
25. EVR register Step Up
The “EVR register Step Up” instruction controls +1 step of EVR register value.
A0
0
RDB WRB
1
0
D7
1
D6
0
D5
0
D4
0
D3
0
D2
0
D1
1
D0
1
COMMAND
EVR Register Step Up
26. EVR register Step Down
The “EVR Register Step Down” instruction controls – 1 step of EVR register value
A0
0
RDB WRB
1
0
D7
1
D6
0
D5
0
D4
0
D3
0
D2
1
D1
0
D0
0
COMMAND
EVR Register Step Down
27. Adjust Boost Voltage Set
The “Adjust Boost Voltage Set” instruction controls 2nd Voltage Booster at Vlcd = 36(V).
A0
0
RDB WRB
1
0
VU2
0
0
0
0
1
1
Ver.2012-11-22
D7
1
*
VU1
0
0
1
1
0
0
D6
0
*
D5
0
*
VU0
0
1
0
1
0
1
D4
0
*
D3
1
*
D2
1
D1
0
D0
1
VU2
VU1
VU0
COMMAND
Mode Set
Adjust Boost Voltage Set
2nd Boost Circuit
OFF ( Default )
2-Time
3-Time
4-Time
5-Time
6-Time
- 59 -
NJU6657
Preliminary
28. Boost Clock Set
The “Boost Clock Set” instruction controls Boost Clock Frequency of 1st Vand 2nd Voltage Booster.
A0
0
RDB WRB
1
0
D7
D6
D5
D4
D3
D2
D1
D0
1
*
0
*
0
*
0
*
0
*
1
1
0
COMMAND
Mode Set
DCC
DCC
DCC
Boost CLK Set
2
1
0
DCC2
DCC1
DCC0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2 Divide
4 Divide
8 Divide
16 Divide
32 Divide
64 Divide
128 Divide
256 Divide
Boost CLK
84.5[kHz]
42.2[kHz]
21.1[kHz]
10.6[kHz]
5.28[kHz]
2.64[kHz] (Default )
1.33[kHz]
0.66[kHz]
* The Boost clock frequency is changes by register (OS4 to 0 ) of Internal Oscillator frequency select instruction. Upper
table value is Boost clock when set to reset condition. (OS4 to 0 =’10000 )
When fix to Internal Frequency, the boost clock frequency caluculate is shown in below.
Boost Clock Frequency: fDCC = fDOSC / n
n: Fix to divide
fDOSC: Basis Frequency (Internal Oscillator : )
* In case of using external clock, Basis frequency interchange External clock frequency.
100
90
80
2-Divide
70
60
50
4-Divide
40
8-Divide
30
16-Divide
20
10
13h
12h
11h
Fh
10h
Eh
Dh
Bh
Ch
0
9h
82.4
88.0
93.4
99.2
104.7
110.3
115.2
120.8
126.0
131.6
137.0
142.3
147.5
153.1
158.5
163.9
169.0 (Default)
174.4
179.4
184.9
Ah
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
10h
11h
12h
13h
8h
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
7h
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
6h
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
5h
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
4h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
Boost CLK
3h
OS4~
0(HEX)
2h
OS
0
1h
OS
1
0h
OS
2
Boost CLK frequency [kHz]
OS
3
OS4 to OS0
7
6
Boost CLK frequency [kHz]
OS
4
5
32-Divide
4
3
64-Divide
128-Divide
2
256-Divide
1
13h
12h
11h
10h
Fh
Eh
Dh
Bh
Ch
Ah
9h
8h
7h
6h
5h
4h
3h
2h
1h
0h
0
OS4 to OS0
Fundamental frequency (it corresponds to OS4 to 0 of a built-in oscillating frequency setting command)
- 60 -
Ver.2012-11-22
NJU6657
Preliminary
29. Thermal Sensor ON/OFF
The ON/OFF of the thermal sensor is set by this instruction.
A0
0
RDB WRB
1
0
D7
0
D6
0
TSON
D5
1
D4
0
D3
1
D2
0
D1
0
D0
TSON
COMMAND
Thermal Sensor ON/OFF
0: Thermal Sensor OFF ( Default )
1: Thermal Sensor ON
30. Discharge ON/OFF
Discharge circuits is used discharge out the stabilizing capacitors placed on the VLCD, V1, V2, V3, V4 and VSS..
This instruction prevents the unknown display at the power supply OFF.
A0
0
RDB WRB
1
0
D7
1
DIS
Ver.2012-11-22
D6
1
D5
1
D4
0
D3
1
D2
0
D1
1
D0
DIS
COMMAND
Discharge ON/OFF
0: Discharge OFF ( Default )
1: Discharge ON
- 61 -
NJU6657
Preliminary
31. Address Home
This instruction sets the initialization of Page Address and Coulumn Address.
A0
0
•
RDB WRB
1
0
D7
1
D6
1
D5
1
D4
0
D3
0
D2
0
D1
1
D0
COMMAND
Address Home
0
Initialize Status
1
2
PARAMETER
Page Address: Set to “0” page.
Coulumn Address: St to “0”.
Resistor
PA3∼0
AC7∼0
Default
0H
00H
32. Power Save
This instruction sets the LSI into the power save mode. This instruction is reducing operating current.
A0
0
RDB WRB
1
0
D7
1
D6
1
D5
1
D4
1
D3
1
D2
0
D1
0
D0
COMMAND
Power Save
0
<Power Save Status>
PARAMETER
Internal Oscillator
Adjust Voltage Circuit
VF Circuit
Voltage Boost Circuit
Thermo Sensor
All COM/SEG output terminals
Status
Stop
Stop
Stop
Stop
Stop
VSS
* When the external clock operation, it can not be accessed.
* The DDRAM can be accessed during the power save mode.
33. Power Save Reset
This instruction releases the power save mode.
A0
0
RDB WRB
1
0
D7
1
D6
1
D5
1
D4
1
D3
0
D2
0
D1
0
D0
COMMAND
Power Save Reset
1
34. Low Voltage Operation Mode
When using to the Low VDD condition (VDD=2.7 to 3.3V), Please set up to “Low Voltage Operation
Mode ON”.
A0
0
RDB WRB
1
0
LVM
- 62 -
D7
0
*
D6
1
*
D5
1
*
D4
0
*
D3
0
*
D2
1
*
D1
1
*
D0
COMMAND
0
LVM
Low Voltage Operation Mode
0: Low Voltage Operation Mode OFF (Default)
1: Low Voltage Operation Mode ON
Ver.2012-11-22
NJU6657
Preliminary
TYPICAL INSTRUCTION SEDUENCE
Initialization Sequence in Using Internal LCD Power Supply
Power ON (VDD, VEE) (*1)
WAIT *2
Reset (RESB terminal)
WAIT *3
Command initialization
(18) Oscillator ON/OFF
(19) Int.
(20) Set to Bias ratio
(21) Set to Temperature Gradient
(23),(24) Set to E.V.R Volume
(27) Boost Circuit Controll function
(28) Set to Boost Clock
(29) Thermo Sensor ON/OFF
(34) Low Voltage Operation Mode
(VDD=3V)
(22) Internal Power Control
Voltage Boost ON
WAIT *4
Initialization Sequence in Using Ext. LCD Power Supply
Power ON (VDD)
WAIT *2
Reset (RESB terminal)
WAIT *3
Command initialization
(18) OSC ON/OFF
(19) Set to internal OSC Frequency
(21) Set to Temperature Gradient
(23),(24) Set to E.V.R Volume
(30) Thermo Sensor ON/OFF
(34) Low Voltage Operation Mode
(VDD=3V)
External Power Supply
From VDCOUT terminal.
WAIT *5
End of Initialize setting
(22) Internal Power Control
Adjust Voltage Circuit ON
V/F Circuit ON
WAIT *5
End of Initialize setting
*1 If different power sources are applied to the VDD and the VEE, turn ON the VDD first.
*2 Wait until the VDD and VEE are stabilized
*3 Reset wait time. ( Over than 2mS )
*4 Wait until the VDCOUT and VDCIN are stabilized
*5 Wait until the VLCD and V1 to V4 are stabilized
Note) Wait time for stabilizing internal power supply differs by external components, VDD, and VLCD.
Make sure what is the eait time in the particular application.
Ver.2012-11-22
- 63 -
NJU6657
Preliminary
Example for Display Data Write Sequence
Set of Initialize
Example for Power OFF Sequence in using Internal Power Supply.
(1) Display OFF
(34) Power Save
(2) Initial Display Line Address Set
(3) Page Address Set
(22) Internal Power Control
Voltage Boost OFF
Voltage Regualator OFF
Voltage Follower OFF
(30) Discharge ON
(4) Culumn Address Set
WAIT (*6)
(6) Display Data write
VEE Power OFF
(6) Diplay Data Write (different Page)
Set to from Page AddressSet
VDD Power OFF
(1) Display ON
Example for Power OFF Sequence in using Ext. Power Supply
(1) Display OFF
(34) Power Save
Ext. Power Supply OFF
(30) Discharge ON
WAIT (*6)
VEE Power OFF
VDD Power OFF
*6 Wait until the discharge stabilized .
Wait time for End of discharge differs by external components, VDD, and VLCD.Make sure what is
the eait time in the particular application.
- 64 -
Ver.2012-11-22
NJU6657
Preliminary
ABSOLUTE MAXIMUMN RATINGS
(Ta=25℃)
PARAMETER
Supply Voltage (1)
RATING
-0.3 to +6.0
UNIT
VDD
Supply Voltage (2)
VEE
-0.3 to +6.0
V
-0.3 to +40.0
V
-0.3 to VLCD
-0.3 to VDD + 0.3
-0.3 to VDD + 0.3
-40 to +105
-55 to +125
V
V
V
℃
℃
SYMBOL
Supply Voltagae (3)
VST1,VST1R
VDCOUT,VDCIN,VLCD
Supply Voltage (4)
V1,V2,V3,V4
Input Voltage
VIN
Output Voltgae
VOUT
Operation Temperature
Topr
Storage Temperature (Chip) Tstg
V
VDCOUT
VDCIN
VLCD
VEE
VDD
V1 to V4
VDDL
VSS
Note 1) VDD, VLCD to V4, VDCOUT, VDCIN voltage values are specified as VSS = 0V.
Note 2) The relation of VDCOUT >VLCD>V1>V2>V3>V4>Vss ; VOUT>VDD>VSS must be maintained.
In case of inputting external LCD driving voltage, LCD drive voltage should start supplying to NJU6657 at the
mean time of turning on VDD power supply or after turned on VDD.
In use of the voltage boost circuit, the condition that the supply voltage : 40V >VOUT –VSS is necessary.
Note 3) If the LSI are used on condition beyond the absolute maximum rating, the LSI may be destroyed. Using LSI
within electrical characteristics is strongly recommended for normal operation. Use beyond the electric
characteristics conditions will cause malfunction and poor reliability.
Note 4) Decoupling capacitor should be connected between VDD and VSS due to the stabilized operation for the voltage
converter.
Ver.2012-11-22
- 65 -
NJU6657
Preliminary
DC Electrical Characteristics
PARAMETER
Power Supply (1)
Power Supply (2)
Power Supply (3)
SYMBOL
VDD
VEE
VST1
VST1R
Power Supply (4)
VDCOUT
VDCIN
VLCD
V1,V2
V3,V4
“H” Level Input Voltage
VIHC1
“L” Level Input Voltage
VILC1
“H” Level Output Voltage VOHC1
“L” Level Output Voltage VOLC1
Leakage Current
ILI
ILO
Driver On-resistance
RON1
RON2
Stand-by Current
Oscillation Frequency
External
Clock Frequency
IDDQ
IEEQ
ILCDQ
fOSC
fCL
CONDITION
1st Boost Input Voltage
VDD=2.7 to 5.5V
VDD=2.7 IOH=-25uA
to 5.5V
IOL= 25uA
VIN=VDD or VSS
Ta=25℃
VLCD=20V
VLCD=10V
VDD=3V,Ta=25℃
VEE=3V, Ta=25℃
VLCD=20V, Ta=25℃
Ta=25℃, Initialize Status
(VSS=0V, VDD=2.7 to 5.5V, Ta=-40 to 105°C)
MIN
TYP
MAX
単位 NOTE
2.7
5.5
V
5
2.7
5.5
V
15
V
6
VDD
VEE
6
6
0.4VLCD
VSS
0.8VDD
VSS
0.8VDD
VSS
-1.0
-3.0
-
1
2.5
36
36
36
VLCD
0.6VLCD
VDD
0.2VDD
VDD
0.2VDD
1.0
3.0
1.7
4.2
38.0
-
0.3
0.3
2
42.2
42.2
5
5
10
46.5
200
V
6
V
V
V
V
uA
uA
kΩ
kΩ
uA
7
kHz
kHz
8
9
10
11
12
Note 5) Although the NJU6657 can operate in wide range of the operating voltage, it shall not be guaranteed in a
suddeen voltage flucuation during the access with MPU.
Note 6) Apply to using of external power supply.
Note 7) Apply to A0,D0 to D7, RDB, WRB, CSB, RESB, CEL68, PS, VDLS, CLS terminals.
Note 8) Apply to D0 to D7, BUSY terminals.
Note 9) Aplly to All Input terminals.
Note 10) Apply to D0 to D7, All output terminals.
Note 11) RON is the resistance values in supplying 0.1V voltage-difference between power supply terminals (V1,
V2, V3, V4) and each output terminals (common/segment) of 1/7 bias setting.
Note 12) Internal osillation frequency when the reset status.
SH1∼0 = ’10’
OS4∼0 = ’10000’
Note 13) The divide of internal oscillation frequency.
SH1 to 0 = ‘00’
- 66 -
Ver.2012-11-22
NJU6657
Preliminary
(VSS=0V, VDD=2.7 to 5.5V, Ta=-40 to 105°C)
SYMBOL
PARAMETER
CONDITION
4-times boost
6-times boost
8-times boost
10-times boost
12-times boost
2-times boost
3-times boost
4-times boost
5-times boost
6-times boost
VSS common
VEE
st
1 Boost
Input Voltgae
VST1R
2nd Boost
Input Voltage
1st Boost
output Voltgae
2nd Boost
output Voltage
Adjustment Range
LCD Driving Voltage
Voltage Follower
Operating Voltage
Operating current
VST1
MIN
2.7
2.7
2.7
2.7
2.7
VDD
VDD
VDD
VDD
VDD
-
TYP
-
MAX
5.5
5.5
5.0
4.0
3.3
15.0
13.3
10.0
8.0
6.6
11.0
VDOUT
VSS common
-
-
36
VLCD
Voltage boost operation off
External power supply
6
-
36
6
-
36
1
1.7
220
40
3
500
VLCD
ISSQ1
ISS1
ISS2
Power save mode
VDD=3V, VLCD=20V,
All COM/SEG open, without MPU
access, checker flag display
UNIT
NOTE
V
14
V
V
V
V
15
V
uA
mA
uA
16
Note 14) Applies to the condition when using the internal voltage booster, VST1 and VST1R terminals are
connected. The adjust boost voltage and boost autocontroled function are not used.
Note 15) The voltage adjustment circuit controls VLCD within the range of the E.V.R circuit.
Note 16) Each operating current shall be defined as being measured in the following condition.
( fFR=80[Hz], 1/10Bias, 1/88Duty, Low voltage operation mode, Driver terminals are open )
SYMBOL
ISS1
ISS2
Power Control
Operating Condition
DCC1
DCC0
VRG
VF
1
0
1
0
1
0
1
0
1st
Booster
On
Off
2nd
Booster
On
Off
Voltage
regulator
On
Off
Voltage
followers
On
Off
External
Voltage Supply
(Input Terminal)
12-Time Boost
VDCIN, VLCD~V4
ISS 1,2 measurement circuit:
+
C1+
C1-
+
VST1
VDCOUT
VDD
VDD
VDCIN
VDCOUT
VEE
VEE
VDCIN
+
+
VST1R
NJU6657
+
C2+
C2-
+
+
C4+
C6+
NJU6657
VLCD
VSS
V1
External
Voltage
Generator
VSSE
VSSA
VSS
V2
VSSE
V3
VSSA
V4
+
C3+
A
A
C3+
C5+
ISS1
Ver.2012-11-22
ISS2
- 67 -
NJU6657
Preliminary
Temperature Sensor Characteristics
(VSS=0V, VDD=2.7 to 5.5V, Ta=-40 to 105°C)
PARAMETER
Operating
Temperature Range
Temperature Gradient
Output Voltage
Output Voltage
Temperature gradient
Temperature sensor
Setup time
Operating Current
SYMBOL
Ta
T
TSV
CONDITION
Ta=-40 to 105℃
Ta=-40℃
Ta=25℃
Ta=105℃
VINC
TTSV
MIN
-40
TYP
-
MAX
105
UNIT
℃
-5.0
1.412
1.144
0.807
-
1.433
1.165
0.828
-4.19
5.0
1.454
1.186
0.849
-
℃
20
-
-
ms
-
20
50
uA
ITS
NOTE
V
mV/℃
18
Note 17) The typ. Value of the sensor analog output voltage TSV when ambient temperature is Ta [OC] is approximated
by the following expression.
VTSV = -0.0006 x Ta2 –4.1386 x Ta +1269mV [mV]
The sensor analog output voltage is output with accuracy of + 5OC.
The output voltage temperature gradient VINC.
Since it is -4.19 [mV/OC], variation voltage [ of TSV ] ΔTSV is denoted by the following formula.
ΔVTSV = ±(4.19 x 5OC) = 21 [mV]
VOUT TSV [OC]
The relationship of between VOUT and Temperature as shown in below.
TSV max
TSV
TSV min
21[mV]
21[mV]
5OC
Ta min
5OC
Ta
Ta max
Temperrature [OC]
Note 18) The setup time is possible of Read-out from after input a temperature sensor ON/OFF instruction.
The TSV terminal is OPEN.
- 68 -
Ver.2012-11-22
NJU6657
Preliminary
BUS TIMING CHARACTERISTICS
- Read and Write characteristics (80 type MPU)
A0
tAS6
tAH6
tWCS6
CSB
tCSH6
tCSS6
tEHR6
WRB
tELR6
tCYC6
D7 to D0
Out Put
tRDD6
tRDH6
A0
tAS6
tAH6
tELR6
CSB
tEHR6
tCYC6
WRB
D7 to D0
PARAMETER
A0 Hold Time
A0 Set Up Time
CSB Hold Time
CSB Set Up Time
CSB ”H” Level Width
System Cycle Time
Write ”L” Pulse Time
Write ”H” Pulse Time
Data Set Up Time
Data Hold Time
tCSH6
tCSS6
tWCS6
tRDD6
SYMBOL
tAS8
tAH8
tCSH8
tCSS8
tWCS8
tCYC8
tWRLW8
tWRHW8
tDS8
tDH8
CONDITION
Out Put
tRDH6
(VSS=0V, VDD=2.7 to 5.5V, Ta=-40 to 105°C)
MIN.
MAX.
UNIT
TERMINAL
50
ns
A0
0
ns
100
ns
CSB
100
ns
500
ns
1350
ns
WRB
550
ns
700
ns
250
ns
D7 to D0
300
ns
Note) Each timing is specified based on 0.2xVDD and 0.8xVDD.
* : (1) Accessed by WRb and RDb signal when CS1b="L". (2) Accessed by CS1b signal when WRb and RDb ="L".
Ver.2012-11-22
- 69 -
NJU6657
Preliminary
- System bus read timing (80 type MPU)
A0
tAS6
tAH6
tWCS6
CSB
tCSH6
tCSS6
tEHR6
E(RDB)
tELR6
tCYC6
D7 to D0
Out Put
tRDD6
tRDH6
A0
tAS6
tAH6
tELR6
CSB
tEHR6
tCYC6
E(RDB)
D7 to D0
PARAMETER
A0 Hold Time
A0 Set Up Time
CSB Hold Time
CSB Set Up Time
CSB ”H” Level Width
System Cycle Time
Read ”L” Pulse Width
Read ”H” Pulse Width
Read Data Out Delay Time
Read Data Hold Time
tCSH6
tCSS6
tWCS6
tRDD6
SYMBOL
tAS8
tAH8
tCSH8
tCSS8
tWCS8
tCYC8
tWRLR8
tWRHR8
tRDD8
tRDH8
CONDITION
CL=100pF
Out Put
tRDH6
(VSS=0V, VDD=2.7 to 5.5V, Ta=-40 to 105°C)
MIN.
MAX.
UNIT
TERMINAL
50
ns
A0
0
ns
100
ns
CSB
100
ns
500
ns
2100
ns
RDB
1150
ns
700
ns
1150
ns
D7 to D0
0
ns
Note) Each timing is specified based on 0.2xVDD and 0.8xVDD.
* : (1) Accessed by WRb and RDb signal when CS1b="L". (2) Accessed by CS1b signal when WRb and RDb ="L".
- 70 -
Ver.2012-11-22
NJU6657
Preliminary
- System bus write timing (68 type MPU)
A0
tAS6
tAH6
RW(WRB)
tWCS6
CSB
tCSH6
tCSS6
tELR6
tEHR6
E(RDB)
tCYC6
D7 to D0
Out Put
tRDD6
tRDH6
A0
tAS6
tAH6
RW(WRB)
tCYC6
tELR6
CSB
tEHR6
tCSH6
tCSS6
E(RDB)
tWCS6
D7 to D0
PARAMETER
A0 Hold Time
A0 Set Up Time
CSB Hold Time
CSB Set Up Time
CSB ”H” Level Pulse Width
System Cycle Time
Enable “L” Pulse Time
Enable “H” Pulse Time
Data Set Up Time
Data Hold Time
tRDD6
SYMBOL
tAS6
tAH6
tCSH6
tCSS6
tWCS6
tCYC6
tELW6
tEHW6
tDS6
tDH6
CONDITION
Out Put
tRDH6
(VSS=0V, VDD=2.7 to 5.5V, Ta=-40 to 105°C)
MIN.
MAX.
UNIT
TERMINAL
50
ns
A0
0
ns
100
ns
CSB
100
ns
500
ns
1350
ns
E
700
ns
550
ns
250
ns
D7 to D0
300
ns
Note) Each timing is specified based on 0.2xVDD and 0.8xVDD.
* : (1) Accessed by WRb and RDb signal when CS1b="L". (2) Accessed by CS1b signal when WRb and RDb ="L".
Ver.2012-11-22
- 71 -
NJU6657
Preliminary
- System bus read timing (68 Type MPU)
A0
tAS6
tAH6
RW(WRB)
tWCS6
CSB
tCSH6
tCSS6
tELR6
tEHR6
E(RDB)
tCYC6
D7 to D0
Out Put
tRDD6
tRDH6
A0
tAS6
tAH6
RW(WRB)
tCYC6
tELR6
CSB
tEHR6
tCSH6
tCSS6
E(RDB)
tWCS6
D7 to D0
PARAMETER
A0 Hold Time
A0 Set Up Time
CSB Hold Time
CSB Set Up Time
CSB ”H” Level Pulse Width
System Cycle Time
Enable “L” Pulse Width
Enable “H” Pulse Width
Read Data Out Daley Time
Read Data Hold Time
tRDD6
SYMBOL
tAS6
tAH6
tCSH6
tCSS6
tWCS6
tCYC6
tELR6
tEHR6
tRDD6
tRDH6
CONDITION
CL=100pF
Out Put
tRDH6
(VSS=0V, VDD=2.7 to 5.5V, Ta=-40 to 105°C)
MIN.
MAX.
UNIT
TERMINAL
50
ns
A0
0
ns
100
ns
CSB
100
ns
500
ns
2100
ns
E
700
ns
1150
ns
1150
ns
D7 to D0
0
ns
Note ) Each timing is specified based on 0.2xVDD and 0.8xVDD.
* : (1) Accessed by WRb and RDb signal when CS1b="L". (2) Accessed by CS1b signal when WRb and RDb ="L".
- 72 -
Ver.2012-11-22
NJU6657
Preliminary
- Serial interface timing (5-wire/3-wire)
A0
RW(WRB)
tWCSS
CSB
tCSS
tCSH
tSLW
tSHW
SCL(D6)
tCYCS
tDSS
SDA Input
tSOD
SDA Output
PARAMETER
SYMBOL
Serial Clock Cycle
tCYCS
SCL “H” Pulse Width
tSHW
SCL ”L” Pulse Width
tSLW
Data Set Up Time
tDSS
Data Hold Time
tDHS
Serial Data Output Delay Time
tSOD
CSB – SCL Time
tCSS
CSB Hold Time
tCSH
CSB "H” Level Pulse Width
tWCSS
tDHS
Input
tSOD
Output
CONDITION
CL=50pF
Output
Output
(VSS=0V, VDD=2.7 to 5.5V, Ta=-40 to 105°C)
MIN.
MAX.
UNIT
TERMINAL
650
ns
300
ns
SCL
300
ns
200
ns
SDA
200
ns
250
ns
SDA
400
ns
200
ns
CSB
200
ns
Note 13) Each timing is specified based on 0.2xVDD and 0.8xVDD.
Ver.2012-11-22
- 73 -
NJU6657
Preliminary
- External clock input timing
OSC1
FCP
PARAMETER
External clock frequency
External clock duty
SYMBOL
fCP
duty
(VSS=0V, VDD=2.7 to 5.5V, Ta=-40 to 105°C)
MAX.
CONDITION
UNIT
200
OSC1
kHz
65
%
MIN.
35
- Reset input timing
tRW
RESb
tR
Internal
circuit status
PARAMETER
Reset Time
Reset “L” Puls width
- 74 -
During reset
SYMBOL
tR
tRW
MIN.
1
End of reset
(VSS=0V, VDD=2.7 to 5.5V, Ta=-40 to 105°C)
MAX.
CONDITION
UNIT
1
µs
ms
Ver.2012-11-22
NJU6657
Preliminary
LCD DRIVING WAVEFORM
0
FR
COM0
COM1
VLCD
V1
V2
V3
V4
VSS
COM2
VLCD
V1
V2
V3
V4
VSS
SEG0
VLCD
V1
V2
V3
V4
VSS
SEG1
VLCD
V1
V2
V3
V4
VSS
COM0-SEG0
VSS
V4
V3
V2
V1
VLCD
-V1
-V2
-V3
-V4
-VSS
COM0-SEG1
VSS
V4
V3
V2
V1
VLCD
-V1
-V2
-V3
-V4
-VSS
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
S S S S S
E E E E E
G G G G G
0
1
Ver.2012-11-22
2
3
2
3
4
86 87 0
1
2
3
4
5
86 87
VDD
VSS
VLCD
V1
V2
V3
V4
VSS
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
1
4
- 75 -
NJU6657
Preliminary
Precautions In Mounting COG
Power supply voltage may drop instantaneously in synchronization with the timing of generating instantaneous current as
in the time when the display clock is switched. If the ITO wiring resistance of the power supply pin is high at this time, power
supply voltge in the IC chip may greatly, leading to malfunction. To supply stable power to the IC, decrease the wiring
impedance of the power line as low as possible.
The ITO layout suggestion is shown as below;
(i)
VSS, VSSA, VSSE. ( Connects to system GND. )
PAD
PAD
PAD
PAD
VSSA
VSSA
VSSE
VSSE
VSS
VSS
NJU6657
PAD
PAD
Separate by ITO
FPC-PIN
FPC-PIN
(ⅱ) VDD,VEE. ( Connects to system VDD. )
NJU6657
PAD
PAD
PAD
PAD
Separate by ITO
FPC-PIN
- 76 -
FPC-PIN
Ver.2012-11-22
NJU6657
Preliminary
APPLICATION CIRCUIT
(1) Microprocessor Interface Example
The NJU6657 interfaces to 80 type or 68 type MPU directly. And the serial interface also communicate with MPU.
* : C86 terminal must be fixed VDD or VSS.
80 Type MPU
2.4 to 3.6V
VCC
(80 系 CPU)
A0
A1~A7
IORQb
D0~D7
RDb
WRb
RESb
7
Decoder
8
GND
A0
D0~D7
VDD
NJU6657
CSB
RDB
WRB
RSTB
VSS
Reset input
68 Type MPU
2.4 to 3.6V
VCC
A0
A1~A15
15
VMA
(68 系 CPU)
D0~D7
E
R/W
RESb
GND
Decoder
8
Reset input
A0
D0~D7
VDD
NJU6657
CSB
RDB(E)
WRB(R/W)
RSTB
VSS
Serial Interface
2.4 to 3.6V
VCC
A0
A1~A7
(CPU)
7
Decoder
PORT1
PORT2
RESb
GND
Ver.2012-11-22
A0
SDA
VDD
NJU6657
CSB
SCL
RSTB
Reset input
VSS
- 77 -
NJU6657
Preliminary
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
- 78 -
Ver.2012-11-22