RICHTEK RT9624B

®
RT9624B
Single Phase Synchronous Rectified Buck MOSFET Driver
General Description
Features
The RT9624B is a high frequency, synchronous rectified,
single phase MOSFET driver designed for normal MOSFET
driving applications and high performance CPU VR driving
capabilities.
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Drive Two N-MOSFETs
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Shoot Through Protection
Embedded Bootstrap Diode
Support High Switching Frequency
Fast Output Rising Time
Tri-State PWM Input for Output Shutdown
Small SOP-8, SOP-8 (Exposed Pad) and 8-Lead
WDFN Packages
RoHS Compliant and Halogen Free
The RT9624B can be supplied from 4.5V to 13.2V. The
applicable power stage VIN range is from 5V to 24V. The
IC also builds in an internal power switch to replace
external bootstrap diode.
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The RT9624B can support switching frequency efficiently
up to 500kHz. The IC has both the UGATE and LGATE
driving circuits for synchronous rectified DC/DC converter
applications. The shoot through protection mechanism is
designed to prevent shoot through between high side and
low side power MOSFETs. The RT9624B has tri-state
PWM input with shutdown function, which can force driver
to output low UGATE and LGATE signals.
Applications
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Core Voltage Supplies for Desktop, Motherboard CPU
High Frequency Low Profile DC/DC Converters
High Current Low Voltage DC/DC Converters
Core Voltage Supplies for GFX Card
The RT9624B comes in a small footprint with 8-pin
packages. The choice of package types includes SOP-8,
SOP-8 (Exposed Pad) and WDFN-8L 3x3.
Simplified Application Circuit
RT9624B
12V
R1
VCC
BOOT
UGATE
R3
Q1
L1
VOUT
PHASE
R4
LGATE
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
October 2012
C6
R5
Q2
+
PWM
GND
DS9624B-04
C5
CBOOT
C1
PWM
Controller
VIN
R2
C3
C4
C2
is a registered trademark of Richtek Technology Corporation.
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1
RT9624B
Ordering Information
Pin Configurations
RT9624B
(TOP VIEW)
Package Type
S : SOP-8
SP : SOP-8 (Exposed Pad-Option1)
QW : WDFN-8L 3x3 (W-Type)
8
BOOT
7
PHASE
NC
3
6
GND
VCC
4
5
LGATE
8
UGATE
Lead Plating System
Z : ECO (Ecological Element with
Halogen Free and Pb free)
SOP-8
BOOT
Note :
Richtek products are :
2
NC
3
VCC
4
GND
7
PHASE
6
GND
5
LGATE
9
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
`
PWM
SOP-8 (Exposed Pad)
Suitable for use in SnPb or Pb-free soldering processes.
Marking Information
RT9624BZS
RT9624BZS : Product Number
RT9624B
ZSYMDNN
BOOT
PWM
NC
VCC
8
1
3
GND
`
UGATE
PWM
2
6
4
9
5
2
7
UGATE
PHASE
GND
LGATE
WDFN-8L 3x3
YMDNN : Date Code
RT9624BZS
RT9624BZSP : Product Number
RT9624B
ZSPYMDNN
YMDNN : Date Code
RT9624BZQW
03 : Product Code
03 YM
DNN
YMDNN : Date Code
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS9624B-04
October 2012
RT9624B
Function Pin Description
SOP-8
Pin No.
SOP-8 (Exposed Pad) /
WDFN-8L 3x3
Pin Name
Pin Function
1
1
BOOT
2
2
PWM
3
3
NC
PWM Signal Input. Connect this pin to the PWM output of the
controller.
No Internal Connection.
4
4
VCC
Supply Voltage Input.
5
5
LGATE
6
6,
9 (Exposed Pad)
7
7
PHASE
8
8
UGATE
GND
Bootstrap Supply for High Side Gate Drive.
Low Side Gate Driver Output. Connect this pin to the Gate of
low side power N-MOSFET.
Ground. The exposed pad must be soldered to a large PCB
and connected to GND for maximum power dissipation.
Connect this pin to the Source of the high side N-MOSFET
and the Drain of the low side N-MOSFET.
High Side Gate Drive Output. Connect this pin to the Gate of
high side power N-MOSFET.
Function Block Diagram
VCC
POR
Bootstrap
Control
Internal
VDD
BOOT
Tri-State
Detect
PWM
Shoot-Through
Protection
UGATE
Turn Off
Detection
PHASE
VCC
Shoot-Through
Protection
LGATE
GND
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS9624B-04
October 2012
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
3
RT9624B
Operation
POR (Power On Reset)
Turn-Off Detection
POR block detects the voltage the VCC pin. When the
VCC pin voltage is higher than POR rising threshold, POR
block output is high. POR output is low when VCC is not
higher than POR rising threshold. When the POR block
output is high, UGATE and LGATE can be controlled by
PWM input voltage. If the POR block output is low, both
UGATE and LGATE will be pulled to low.
Turn-off detection block detects whether high side
MOSFET is turned off by monitoring PHASE pin voltage.
To avoid shoot through between high side and low side
MOSFETs, low side MOSFET can be turned on only after
high side MOSFET is effectively turned off.
Tri-State Detect
When both POR block output and EN pin voltages are
high, UGATE and LGATE can be controlled by PWM input.
There are three PWM input modes, which are high, low,
and shutdown state. If PWM input is within the shutdown
window, both UGATE and LGATE output are low. When
PWM input is higher than its rising threshold, UGATE is
high and LGATE is low. When PWM input is lower than
its falling threshold, UGATE is low and LGATE is high.
Shoot-Through Protection
Shoot-through protection block implements the dead time
when both high side and low side MOSFETs are turned
off. With shoot-through protection block, high side and
low side MOSFET are never turned on simultaneously.
Thus, shoot through between high side and low side
MOSFETs is prevented.
Bootstrap Control
Bootstrap control block controls the integrated bootstrap
switch. When LGATE is high (low side MOSFET is turned
on), the bootstrap switch is turned on to charge the
bootstrap capacitor connected to BOOT pin. When LGATE
is low (low side MOSFET is turned off), the bootstrap
switch is turned off to disconnect VCC pin and BOOT
pin.
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS9624B-04
October 2012
RT9624B
Absolute Maximum Ratings
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(Note 1)
Supply Voltage, VCC -------------------------------------------------------------------------------- −0.3V to 15V
BOOT to PHASE ------------------------------------------------------------------------------------- −0.3V to 15V
PHASE to GND
DC -------------------------------------------------------------------------------------------------------- −0.3V to 30V
< 20ns --------------------------------------------------------------------------------------------------- −10V to 35V
LGATE to GND
DC -------------------------------------------------------------------------------------------------------- −0.3V to (VCC + 0.3V)
< 20ns --------------------------------------------------------------------------------------------------- −2V to (VCC + 0.3V)
UGATE to GND
DC -------------------------------------------------------------------------------------------------------- (VPHASE − 0.3V) to (VBOOT + 0.3V)
< 20ns --------------------------------------------------------------------------------------------------- (VPHASE − 2V) to (VBOOT + 0.3V)
PWM to GND ------------------------------------------------------------------------------------------ −0.3V to 7V
Power Dissipation, PD @ TA = 25°C
SOP-8 --------------------------------------------------------------------------------------------------- 0.833W
SOP-8 (Exposed Pad) ------------------------------------------------------------------------------ 1.333W
WDFN-8L 3x3 ----------------------------------------------------------------------------------------- 1.429W
Package Thermal Resistance (Note 2)
SOP-8, θJA --------------------------------------------------------------------------------------------- 120°C/W
SOP-8 (Exposed Pad), θJA ------------------------------------------------------------------------- 75°C/W
SOP-8 (Exposed Pad), θJC ------------------------------------------------------------------------ 15°C/W
WDFN-8L 3x3, θJA ------------------------------------------------------------------------------------ 70°C/W
WDFN-8L 3x3, θJC ------------------------------------------------------------------------------------ 8.2°C/W
Lead Temperature (Soldering, 10 sec.) ---------------------------------------------------------- 260°C
Junction Temperature -------------------------------------------------------------------------------- 150°C
Storage Temperature Range ----------------------------------------------------------------------- −65°C to 150°C
ESD Susceptibility (Note 3)
HBM (Human Body Model) ------------------------------------------------------------------------- 2kV
Recommended Operating Conditions
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(Note 4)
Supply Voltage, VCC -------------------------------------------------------------------------------- 4.5V to 13.2V
Junction Temperature Range ----------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range ----------------------------------------------------------------------- −40°C to 85°C
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS9624B-04
October 2012
is a registered trademark of Richtek Technology Corporation.
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RT9624B
Electrical Characteristics
(VCC = 12V, TA = 25°C unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
4.5
--
13.2
V
Power Supply
Power Supply Voltage
VCC
Power Supply Current
IVCC
VBOOT = 12V, PWM Input Floating
--
120
--
μA
POR Rising Threshold
VPOR_r
VCC Rising
--
4
4.4
V
POR Falling Threshold
VPOR_ f
VCC Falling
3
3.5
--
V
Maximum Input Current
IPWM
PWM = 0V or 5V
--
160
--
μA
PWM Floating Voltage
VPWM_fl
PWM = Open
--
1.8
--
V
PWM Rising Threshold
VPWM_rth
2.3
2.8
3.2
V
PWM Falling Threshold
VPWM_fth
0.7
1.1
1.4
V
Power On Reset (POR)
PWM Input
Timing
UGATE Rising Time
tUGATEr
3nF Load
--
25
--
ns
UGATE Falling Time
tUGATEf
3nF Load
--
12
--
ns
LGATE Rising Time
tLGATEr
3nF Load
--
24
--
ns
LGATE Falling Time
tLGATEf
3nF Load
--
10
--
ns
tUGATEpdh
--
30
--
tUGATEpdl
VBOOT − VPHASE = 12V
See Timing Diagram
--
22
--
tLGATEpdh
See Timing Diagram
--
30
--
tLGATEpdl
See Timing Diagram
--
8
--
UGATE Drive Source
RUGATEsr
VBOOT − VPHASE = 12V, ISource = 100mA
--
1.7
--
Ω
UGATE Drive Sink
RUGATEsk
VBOOT − VPHASE = 12V, ISink = 100mA
--
1.4
--
Ω
LGATE Drive Source
RLGATEsr
ISource = 100mA
--
1.6
--
Ω
LGATE Drive Sink
RLGATEsk
ISink = 100mA
--
1.1
--
Ω
UGATE Propagation Delay
LGATE Propagation Delay
ns
ns
Output
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS9624B-04
October 2012
RT9624B
Typical Application Circuit
12V
RT9624B
R1
2.2
VCC
C1
1µF
CBOOT
1µF R3
2.2
PWM
C6
10µF
x4
C5
1000µF
x3
L1
1µH
Q1
UGATE
VIN
12V
VOUT
PHASE
R4
0
GND
LGATE
+
PWM
Controller
BOOT
R2
1
R5
2.2
Q2
C3
2200µF
x2
C2
3.3nF
C4
10µF
x2
Timing Diagram
PWM
tLGATEpdl
LGATE
90%
tUGATEpdl
1.5V
1.5V
1.5V
90%
1.5V
UGATE
tUGATEpdh
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS9624B-04
October 2012
tLGATEpdh
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RT9624B
Typical Operating Characteristics
PWM Rising Edge
PWM Falling Edge
PWM
(10V/Div)
PWM
(10V/Div)
UGATE
(20V/Div)
UGATE
(20V/Div)
LGATE
(10V/Div)
LGATE
(10V/Div)
PHASE
(10V/Div)
PHASE
(10V/Div)
Time (20ns/Div)
Time (20ns/Div)
Dead Time
Dead Time
UGATE
UGATE
PHASE
PHASE
LGATE
LGATE
(5V/Div)
(5V/Div)
Full Load
Full Load
Time (20ns/Div)
Time (20ns/Div)
Dead Time
Dead Time
UGATE
UGATE
PHASE
PHASE
LGATE
(5V/Div)
LGATE
(5V/Div)
No Load
Time (20ns/Div)
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No Load
Time (20ns/Div)
is a registered trademark of Richtek Technology Corporation.
DS9624B-04
October 2012
RT9624B
Short Pulse
UGATE
LGATE
PHASE
(5V/Div)
UGATE − PHASE
No Load
Time (20ns/Div)
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS9624B-04
October 2012
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
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RT9624B
Application Information
The RT9624B is a high frequency, synchronous rectified,
single phase dual MOSFET driver containing Richtek's
advanced MOSFET driver technologies. The RT9624B is
designed to be able to adapt from normal MOSFET driving
applications to high performance CPU VR driving
capabilities.
Internal Bootstrap Power Switch
Supply Voltage and Power On Reset
Non-overlap Control
The RT9624B can be utilized under both VCC = 5V or VCC
= 12V applications which may happen in different fields of
electronics application circuits. In terms of efficiency,
higher VCC equals higher driving voltage of UGATE/LGATE
which may result in higher switching loss and lower
conduction loss of power MOSFETs. The choice of VCC =
12V or VCC = 5V can be a tradeoff to optimize system
efficiency.
To prevent the overlap of the gate drivers during the UGATE
pull low and the LGATE pull high, the non-overlap circuit
monitors the voltages at the PHASE node and high side
gate drive (UGATE-PHASE). When the PWM input signal
goes low, UGATE begins to pull low (after propagation
delay). Before LGATE is pulled high, the non-overlap
protection circuit ensures that the monitored voltages have
gone below 1.1V. Once the monitored voltages fall below
1.1V, LGATE begins to turn high. By waiting for the
voltages of the PHASE pin and high side gate driver to fall
below 1.1V, the non-overlap protection circuit ensures that
UGATE is low before LGATE pulls high.
The RT9624B is designed to drive both high side and low
side N-MOSFET through external input PWM control
signal. It has power on protection function which held
UGATE and LGATE low before the VCC voltage rises to
higher than rising threshold voltage.
Tri-state PWM Input
After the initialization, the PWM signal takes the control.
The rising PWM signal first forces the LGATE signal to
turn low then UGATE signal is allowed to go high just
after a non-overlapping time to avoid shoot through current.
The falling of PWM signal first forces UGATE to go low.
When UGATE and PHASE signal reach a predetermined
low level, LGATE signal is allowed to turn high.
The PWM signal is acted as “ High” if the signal is above
the rising threshold and acted as “ Low” if the signal is
below the falling threshold. When PWM signal level enters
and remains within the shutdown window, the output drivers
are disabled and both MOSFET gates are pulled and held
low. If the PWM signal is left floating, the pin will be kept
around 1.8V by the internal divider and provide the PWM
controller with a recognizable level.
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The RT9624B builds in an internal bootstrap power switch
to replace external bootstrap diode, and this can facilitate
PCB design and reduce total BOM cost of the system.
Hence, no external bootstrap diode is required in real
applications.
Also to prevent the overlap of the gate drivers during
LGATE pull low and UGATE pull high, the non-overlap
circuit monitors the LGATE voltage. When LGATE goes
below 1.1V, UGATE goes high after propagation delay.
Driving Power MOSFETs
The DC input impedance of the power MOSFET is
extremely high. When Vgs1 or Vgs2 is at 12V or 5V, the
gate draws the current only for few nano-amperes. Thus
once the gate has been driven up to “ ON” level, the
current could be negligible.
However, the capacitance at the gate to source terminal
should be considered. It requires relatively large currents
to drive the gate up and down 12V (or 5V) rapidly. It is
also required to switch drain current on and off with the
required speed. The required gate drive currents are
calculated as follows.
is a registered trademark of Richtek Technology Corporation.
DS9624B-04
October 2012
RT9624B
d1
s1
VPHASE
VIN
L
VOUT
Igd1 = Cgd1
Cgd2
Igs1
Igd1
Ig1
g1
Before the low side MOSFET is turned on, the Cgd2 have
been charged to VIN. Thus, as Cgd2 reverses its polarity
and g2 is charged up to 12V, the required current is
VIN + 12
dV
Igd2 = Cgd2
= Cgd2
(4)
dt
tr2
d2
Ig2 Igd2
g2
D2
Igs2
Cgs2
s2
GND
Vg1
VPHASE +12V
t
Vg2
It is helpful to calculate these currents in a typical case.
Assume a synchronous rectified Buck converter, input
voltage VIN = 12V, Vgs1 = 12V, Vgs2 = 12V. The high side
MOSFET is PHB83N03LT whose C iss = 1660pF,
Crss = 380pF, and tr = 14ns. The low side MOSFET is
PHB95N03LT whose Ciss = 2200pF, Crss = 500pF and
tr = 30ns, from the equation (1) and (2) we can obtain
Igs1 =
12V
Igs2 =
t
Figure 1. Equivalent Circuit and Waveforms (VCC = 12V)
In Figure 1, the current Ig1 and Ig2 are required to move the
gate up to 12V. The operation consists of charging Cgd1,
Cgd2 , Cgs1 and Cgs2. Cgs1 and Cgs2 are the capacitors from
gate to source of the high side and the low side power
MOSFETs, respectively. In general data sheets, the Cgs1
and C gs2 are referred as “ Ciss” which are the input
capacitors. Cgd1 and Cgd2 are the capacitors from gate to
drain of the high side and the low side power MOSFETs,
respectively and referred to the data sheets as “ Crss” the
reverse transfer capacitance. For example, tr1 and tr2 are
the rising time of the high side and the low side power
MOSFETs respectively, the required current Igs1 and Igs2,
are shown as below :
dVg1 Cgs1 x 12
(1)
=
Igs1 = Cgs1
dt
tr1
dVg2
dt
=
Cgs1 x 12
(2)
tr2
Before driving the gate of the high side MOSFET up to
12V, the low side MOSFET has to be off; and the high
side MOSFET will be turned off before the low side is
turned on. From Figure 1, the body diode “ D2” will be
turned on before high side MOSFETs turn on.
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS9624B-04
(3)
Cgs1
Cgd1
Igs2 = Cgs1
dV
12
= Cgd1
dt
tr1
October 2012
1660 x 10-12 x 12
14 x 10-9
2200 x 10-12 x 12
30 x 10-9
= 1.428
= 0.88
(5)
(A)
(A)
(6)
from equation. (3) and (4)
Igd1 =
Igd2 =
380 x 10-12 x 12
14 x 10-9
= 0.326 (A)
500 x 10-12 x (12+12 )
30 x 10-9
(7)
= 0.4 (A)
(8)
the total current required from the gate driving source can
be calculated as the following equations.
Ig1 = Igs1 + Igd1 = (1.428 + 0.326 ) = 1.754 (A)
Ig2 = Igs2 + Igd2 = ( 0.88 + 0.4 ) = 1.28 (A)
(9)
(10)
By a similar calculation, we can also get the sink current
required from the turned off MOSFET.
Select the Bootstrap Capacitor
Figure 2 shows part of the bootstrap circuit of the
RT9624B. The VCB (the voltage difference between BOOT
and PHASE on RT9624B) provides a voltage to the gate
of the high side power MOSFET. This supply needs to be
ensured that the MOSFET can be driven. For this, the
capacitance CBOOT has to be selected properly. It is
determined by the following constraints.
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RT9624B
Figure 4 shows the power dissipation of the RT9624B as
a function of frequency and load capacitance when VCC =
VIN
BOOT
CBOOT
UGATE
12V. The value of CU and CL are the same and the frequency
is varied from 100kHz to 1MHz.
+
VCB
-
PHASE
Power Dissipation vs. Frequency
1000
VCC
GND
Figure 2. Part of Bootstrap Circuit of RT9624B
In practice, a low value capacitor CBOOT will lead to the
over charging that could damage the IC. Therefore, to
minimize the risk of overcharging and to reduce the ripple
on VCB, the bootstrap capacitor should not be smaller than
0.1μF, and the larger the better. In general design, using
1μF can provide better performance. At least one low-ESR
capacitor should be used to provide good local de-coupling.
It is recommended to adopt a ceramic or tantalum
capacitor.
Power Dissipation
To prevent driving the IC beyond the maximum
recommended operating junction temperature of 125°C,
it is necessary to calculate the power dissipation
appropriately. This dissipation is a function of switching
frequency and total gate charge of the selected MOSFET.
Figure 3 shows the power dissipation test circuit. CL and
C U are the UGATE and LGATE load capacitors,
respectively. The bootstrap capacitor value is 1μF.
Power Dissipation (mW)
900
LGATE
CU = CL = 3nF
800
700
600
CU = CL = 2nF
500
400
300
CU = CL = 1nF
200
100
VCC = 12V
0
0
200
400
600
800
1000
Frequency (kHz)
Figure 4. Power Dissipation vs. Frequency
The operating junction temperature can be calculated from
the power dissipation curves (Figure 4). Assume
VCC = 12V, operating frequency is 200kHz and CU = CL =
1nF which emulate the input capacitances of the high side
and low side power MOSFETs. From Figure 4, the power
dissipation is 100mW. Thus, for example, with the SOP8 package, the package thermal resistance θJA is 120°C/
W. The operating junction temperature is then calculated
as :
TJ = (120°C/W x 100mW) + 25°C = 37°C
(11)
where the ambient temperature is 25°C.
Thermal Considerations
CBOOT
1µF
12V
BOOT
10
12V
VCC
2N7002
UGATE
1µF
CU
3nF
RT9624B
PHASE
PWM
2N7002
PWN
LGATE
GND
20
CL
3nF
Figure 3. Power Dissipation Test Circuit
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12
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
is a registered trademark of Richtek Technology Corporation.
DS9624B-04
October 2012
RT9624B
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
SOP-8 package, the thermal resistance, θJA, is 120°C/W
on a standard JEDEC 51-7 four-layer thermal test board.
For SOP-8 (Exposed Pad) package, the thermal
resistance, θJA, is 75°C/W on a standard JEDEC 51-7
four-layer thermal test board. For WDFN-8L 3x3 package,
the thermal resistance, θJA, is 70°C/W on a standard
JEDEC 51-7 four-layer thermal test board. The maximum
power dissipation at TA = 25°C can be calculated by the
following formulas :
Layout Consideration
Figure 6 shows the schematic circuit of a synchronous
buck converter to implement the RT9624B. The converter
operates from 5V to 12V of input Voltage.
For the PCB layout, it should be very careful. The power
circuit section is the most critical one. If not configured
properly, it will generate a large amount of EMI. The location
of Q1, Q2, L1 should be very close.
PD(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W for
SOP-8 (Exposed Pad) package
Next, the trace from UGATE, and LGATE should also be
short to decrease the noise of the driver output signals.
PHASE signals from the junction of the power MOSFET,
carrying the large gate drive current pulses, should be as
heavy as the gate drive trace. The bypass capacitor C1
should be connected to GND directly. Furthermore, the
bootstrap capacitors (CBOOT) should always be placed as
close to the pins of the IC as possible.
PD(MAX) = (125°C − 25°C) / (70°C/W) = 1.429W for
WDFN-8L 3x3 package
VIN
12V
Maximum Power Dissipation (W)
Four-Layer PCB
WDFN-8L 3x3
1.4
12V
C5
R1
VCC
CBOOT
C1
Q1
L1
VCORE
UGATE
PHB83N03LT
PHASE
C3
Q2
1.2
C6
BOOT
+
1.6
L2
+
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curve in Figure 5 allow the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
PHB95N03LT
LGATE
RT9624B
PD(MAX) = (125°C − 25°C) / (120°C/W) = 0.833W for
SOP-8 package
PWM
PWM
GND
SOP-8 (Exposed Pad)
1.0
Figure 6. Synchronous Buck Converter Circuit
0.8
SOP-8
0.6
0.4
0.2
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 5. Derating Curve of Maximum Power Dissipation
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS9624B-04
October 2012
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
13
RT9624B
Outline Dimension
H
A
M
J
B
F
C
I
D
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
4.801
5.004
0.189
0.197
B
3.810
3.988
0.150
0.157
C
1.346
1.753
0.053
0.069
D
0.330
0.508
0.013
0.020
F
1.194
1.346
0.047
0.053
H
0.170
0.254
0.007
0.010
I
0.050
0.254
0.002
0.010
J
5.791
6.200
0.228
0.244
M
0.400
1.270
0.016
0.050
8-Lead SOP Plastic Package
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
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14
is a registered trademark of Richtek Technology Corporation.
DS9624B-04
October 2012
RT9624B
H
A
M
EXPOSED THERMAL PAD
(Bottom of Package)
Y
J
X
B
F
C
I
D
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
4.801
5.004
0.189
0.197
B
3.810
4.000
0.150
0.157
C
1.346
1.753
0.053
0.069
D
0.330
0.510
0.013
0.020
F
1.194
1.346
0.047
0.053
H
0.170
0.254
0.007
0.010
I
0.000
0.152
0.000
0.006
J
5.791
6.200
0.228
0.244
M
0.406
1.270
0.016
0.050
X
2.000
2.300
0.079
0.091
Y
2.000
2.300
0.079
0.091
X
2.100
2.500
0.083
0.098
Y
3.000
3.500
0.118
0.138
Option 1
Option 2
8-Lead SOP (Exposed Pad) Plastic Package
Copyright © 2012 Richtek Technology Corporation. All rights reserved.
DS9624B-04
October 2012
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
15
RT9624B
D2
D
L
E
E2
1
e
SEE DETAIL A
b
2
1
2
1
A
A1
A3
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.200
0.300
0.008
0.012
D
2.950
3.050
0.116
0.120
D2
2.100
2.350
0.083
0.093
E
2.950
3.050
0.116
0.120
E2
1.350
1.600
0.053
0.063
e
L
0.650
0.425
0.026
0.525
0.017
0.021
W-Type 8L DFN 3x3 Package
Richtek Technology Corporation
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
www.richtek.com
16
DS9624B-04
October 2012