54F/74F322 Octal Serial/Parallel Register with Sign Extend General Description Features The ’F322 is an 8-bit shift register with provision for either serial or parallel loading and with TRI-STATEÉ parallel outputs plus a bi-state serial output. Parallel data inputs and parallel outputs are multiplexed to minimize pin count. State changes are initiated by the rising edge of the clock. Four synchronous modes of operation are possible: hold (store), shift right with serial entry, shift right with sign extend and parallel load. An asynchronous Master Reset (MR) input overrides clocked operation and clears the register. Y Commercial Package Number Military 74F322PC N20A 54F322DM (Note 2) 74F322SJ (Note 1) Y Y Y Multiplexed parallel I/O ports Separate serial input and output Sign extend function TRI-STATE outputs for bus applications Package Description 20-Lead (0.300× Wide) Molded Dual-In-Line J20A 20-Lead Ceramic Dual-In-Line M20D 20-Lead (0.300× Wide) Molded Small Outline, EIAJ 54F322FM (Note 2) W20A 20-Lead Cerpack 54F322LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C Note 1: Devices also available in 13× reel. Use suffix e SJX. Note 2: Military grade device with environmental and burn-in processing. Use suffix e DMQB, FMQB and LMQB. Logic Symbols IEEE/IEC TL/F/9516 – 3 TL/F/9516 – 5 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/9516 RRD-B30M105/Printed in U. S. A. 54F/74F322 Octal Serial/Parallel Register with Sign Extend May 1995 Connection Diagrams Pin Assignment for DIP, SOIC and Flatpak Pin Assignment for LCC TL/F/9516 – 2 TL/F/9516–1 2 Unit Loading/Fan Out 54F/74F Pin Names RE S/P SE S D0, D1 CP MR OE Q0 I/O0 – I/O7 Description U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL Register Enable Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA Serial (HIGH) or Parallel (LOW) Mode Control Input 1.0/1.0 20 mA/b0.6 mA Sign Extend Input (Active LOW) 1.0/3.0 20 mA/b1.8 mA Serial Data Select Input 1.0/2.0 20 mA/b1.2 mA Serial Data Inputs 1.0/1.0 20 mA/b0.6 mA Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 mA/b0.6 mA Asynchronous Master Reset Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA TRI-STATE Output Enable Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA b 1 mA/ b 20 mA Bi-State Serial Output 50/33.3 Multiplexed Parallel Data Inputs or 3.5/1.083 70 mA/b0.65 mA TRI-STATE Parallel Data Outputs 150/40 (33.3) b3 mA/24 mA (20 mA) Functional Description on SE enables serial entry from either D0 or D1, as determined by the S input. A LOW signal on SE enables shift right but Q7 reloads its contents, thus performing the sign extend function required for the ’F384 Twos Complement Multiplier. A HIGH signal on OE disables the TRI-STATE output buffers, regardless of the other control inputs. In this condition the shifting and loading operations can still be performed. The ’F322 contains eight D-type edge triggered flip-flops and the interstage gating required to perform right shift and the intrastage gating necessary for hold and synchronous parallel load operations. A LOW signal on RE enables shifting or parallel loading, while a HIGH signal enables the hold mode. A HIGH signal on S/P enables shift right, while a LOW signal disables the TRI-STATE output buffers and enables parallel loading. In the shift right mode a HIGH signal Mode Select Table Inputs Mode Outputs Q0 MR RE S/P SE S OE* CP I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 L L X X X X X X X X L H X X L Z L Z L Z L Z L Z L Z L Z L Z L L Parallel Load H L L X X X L I7 I6 I5 I4 I3 I2 I1 I0 I0 Shift Right H H L L H H H H L H L L L L D0 D1 O7 O7 O6 O6 O5 O5 O4 O4 O3 O3 O2 O2 O1 O1 O1 O1 Sign Extend H L H L X L L O7 O7 O6 O5 O4 O3 O2 O1 O1 Hold H H X X X L L NC NC NC NC NC NC NC NC NC Clear *When the OE input is HIGH all I/On terminals are at the high impedance state; sequential operation or clearing of the register is not affected. Note 1: I7 –I0 e The level of the steady-state input at the respective I/O terminal is loaded into the flip-flop while the flip-flop outputs (except Q0) are isolated from the I/O terminal. Note 2: D0, D1 e The level of the steady-state inputs to the serial multiplexer input. Note 3: O7 –O0 e The level of the respective Qn flip-flop prior to the last Clock LOW-to-HIGH transition. H e HIGH Voltage Level L e LOW Voltage Level Z e High Impedance Output State L e LOW-to-HIGH Transition NC e No Change 3 Logic Diagram TL/F/9516 – 4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 4 Absolute Maximum Ratings (Note 1) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0.5V to VCC Standard Output b 0.5V to a 5.5V TRI-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b 65§ C to a 150§ C Ambient Temperature under Bias Junction Temperature under Bias Plastic b 55§ C to a 125§ C b 55§ C to a 175§ C b 55§ C to a 150§ C VCC Pin Potential to Ground Pin Recommended Operating Conditions b 0.5V to a 7.0V Free Air Ambient Temperature Military Commercial b 0.5V to a 7.0V Input Voltage (Note 2) Input Current (Note 2) b 30 mA to a 5.0 mA Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. b 55§ C to a 125§ C 0§ C to a 70§ C Supply Voltage Military Commercial Note 2: Either voltage limit or current limit is sufficient to protect inputs. a 4.5V to a 5.5V a 4.5V to a 5.5V DC Electrical Characteristics Symbol 54F/74F Parameter Min VIH Input HIGH Voltage VIL Input LOW Voltage Units Input Clamp Diode Voltage VOH Output HIGH Voltage 54F 10% VCC 54F 10% VCC 74F 10% VCC 74F 10% VCC 74F 5% VCC 74F 5% VCC VCC Conditions Max 2.0 VCD VOL Typ V Recognized as a HIGH Signal 0.8 V Recognized as a LOW Signal b 1.2 V 2.5 2.4 2.5 2.4 2.7 2.7 Min IIN e b18 mA V Min IOH IOH IOH IOH IOH IOH IOL e 20 mA (Q0, I/On) IOL e 20 mA (Q0) IOL e 24 mA ( I/On) e e e e e e b 1 mA (Q0, I/On) b 3 mA (I/On) b 1 mA (Q0, I/On) b 3 mA (I/On) b 1 mA (Q0, I/On) b 3 mA (I/On) Output LOW Voltage 54F 10% VCC 74F 10% VCC 74F 10% VCC 0.5 0.5 0.5 V Min IIH Input HIGH Current 54F 74F 20.0 5.0 mA Max VIN e 2.7V IBVI Input HIGH Current Breakdown Test 54F 74F 100 7.0 mA Max VIN e 7.0V (Non-I/O Inputs) IBVIT Input HIGH Current Breakdown Test (I/O) 54F 74F 1.0 0.5 mA Max VIN e 5.5V (I/On) ICEX Output HIGH Leakage Current 54F 74F 250 50 mA Max VOUT e VCC VID Input Leakage Test 74F V 0.0 IID e 1.9 mA All Other Pins Grounded IOD Output Leakage Circuit Current 74F 3.75 mA 0.0 VIOD e 150 mV All Other Pins Grounded IIL Input LOW Current b 0.6 b 1.2 b 1.8 mA mA mA Max Max Max VIN e 0.5V (RE, S/P, Dn, CP, MR, OE) VIN e 0.5V (S) VIN e 0.5V (SE) IIH a IOZH Output Leakage Current 70 mA Max VI/O e 2.7V (I/On) IIL a IOZL Output Leakage Current b 650 mA Max VI/O e 0.5V (I/On) IOS Output Short-Circuit Current b 150 mA Max VOUT e 0V IZZ Bus Drainage Test 500 mA 0.0V VOUT e 5.25V ICC Power Supply Current 90 mA Max 4.75 b 60 60 5 AC Electrical Characteristics Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V CL e 50 pF TA, VCC e Mil CL e 50 pF TA, VCC e Com CL e 50 pF Max Min Max Min Typ fmax Maximum Clock Frequency 70 90 tPLH tPHL Propagation Delay CP to I/On 3.5 5.0 7.0 8.5 7.5 11.0 3.5 3.5 9.5 10.0 3.5 5.0 8.5 12.0 tPLH tPHL Propagation Delay CP to Q0 3.5 3.5 7.0 7.0 9.0 8.0 3.5 3.5 11.0 10.0 3.5 3.5 10.0 9.0 tPHL Propagation Delay MR to I/On 6.0 10.0 13.0 6.0 15.0 6.0 14.0 ns tPHL Propagation Delay MR to Q0 5.5 7.5 12.0 5.5 14.0 5.5 13.0 ns tPZH tPZL Output Enable Time OE to I/On 3.0 4.0 6.5 8.5 9.0 11.0 3.0 4.0 12.5 14.5 3.0 4.0 10.0 12.0 tPHZ tPLZ Output Disable Time OE to I/On 2.0 2.0 4.5 5.0 6.0 7.0 2.0 2.0 8.0 10.0 2.0 2.0 7.0 8.0 tPZH tPZL Output Enable Time S/P to I/On 4.5 5.5 8.0 10.0 10.5 14.0 4.5 5.5 13.5 17.0 4.5 5.5 11.5 15.0 tPHZ tPLZ Output Disable Time S/P to I/On 5.0 6.0 9.0 12.0 11.5 15.5 5.0 6.0 16.5 19.5 5.0 6.0 12.5 16.5 50 Min Units Max 70 MHz ns ns ns AC Operating Requirements Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V TA, VCC e Mil TA, VCC e Com Min Min Min Max Max Units Max ts(H) ts(L) Setup Time, HIGH or LOW RE to CP 6.0 14.0 14.0 18.0 7.0 16.0 ns th(H) th(L) Hold Time, HIGH or LOW RE to CP 0 0 0 0 0 0 ns ts(H) ts(L) Setup Time, HIGH or LOW D0, D1 or I/On to CP 6.5 6.5 8.5 8.5 7.5 7.5 ns th(H) th(L) Hold Time, HIGH or LOW D0, D1 or I/On to CP 2.0 2.0 3.0 3.0 3.0 3.0 ns ts(H) ts(L) Setup Time, HIGH or LOW SE to CP 7.0 2.5 9.0 11.0 8.0 3.5 ns th(H) th(L) Hold Time, HIGH or LOW SE to CP 2.0 0.0 2.0 1.0 2.0 0.0 ns ts(H) ts(L) Setup Time, HIGH or LOW S/P to CP 11.0 13.5 13.0 21.0 12.0 15.5 ns ts(H) ts(L) Setup Time, HIGH or LOW S to CP 6.5 9.0 8.5 11.0 7.5 10.0 ns th(H) th(L) Hold Time, HIGH or LOW S or S/P to CP 0 0 1.0 0 0 0 ns tw(H) tw(L) CP Pulse Width, HIGH or LOW 7.0 8.0 7.0 ns tw(L) MR Pulse Width, LOW 5.5 7.5 6.5 trec Recovery Time MR to CP 8.0 12.0 8.0 6 ns Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74F 322 S Temperature Range Family 74F e Commercial 54F e Military C X Special Variations QB e Military grade device with environmental and burn-in processing X e Devices shipped in 13× reel Device Type Package Code P e Plastic DIP D e Ceramic DIP F e Flatpak SJ e Small Outline SOIC EIAJ L e Leadless Chip Carrier (LCC) Temperature Range C e Commercial (0§ C to a 70§ C) M e Military (b55§ C to a 125§ C) Physical Dimensions inches (millimeters) 20-Lead Ceramic Leadless Chip Carrier (L) NS Package Number E20A 7 Physical Dimensions inches (millimeters) (Continued) 20-Lead Ceramic Dual-In-Line Package (D) NS Package Number J20A 8 Physical Dimensions inches (millimeters) (Continued) 20-Lead (0.300× Wide) Molded Small Outline Package, EIAJ (SJ) NS Package Number M20D 20-Lead (0.300× Wide) Molded Dual-In-Line Package (P) NS Package Number N20A 9 54F/74F322 Octal Serial/Parallel Register with Sign Extend Physical Dimensions inches (millimeters) (Continued) 20-Lead Ceramic Flatpak (F) NS Package Number W20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Europe Fax: (a49) 0-180-530 85 86 Email: cnjwge @ tevm2.nsc.com Deutsch Tel: (a49) 0-180-530 85 85 English Tel: (a49) 0-180-532 78 32 Fran3ais Tel: (a49) 0-180-532 93 58 Italiano Tel: (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductor Japan Ltd. Tel: 81-043-299-2309 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.