54F/74F194 4-Bit Bidirectional Universal Shift Register General Description Features The ’F194 is a high-speed 4-bit bidirectional universal shift register. As a high-speed, multifunctional, sequential building block, it is useful in a wide variety of applications. It may be used in serial-serial, shift left, shift right, serial-parallel, parallel-serial, and parallel-parallel data register transfers. The ’F194 is similar in operation to the ’F195 universal shift register, with added features of shift left without external connections and hold (do nothing) modes of operation. Y Commercial Y Y Y Typical shift frequency of 150 MHz Asynchronous master reset Hold (do nothing) mode Fully synchronous serial or parallel data transfers Package Number Military 74F194PC 54F194DM (Note 2) Package Description N16E 16-Lead (0.300× Wide) Molded Dual-In-Line J16A 16-Lead Ceramic Dual-In-Line 74F194SC (Note 1) M16A 16-Lead (0.150× Wide) Molded Small Outline, JEDEC 74F194SJ (Note 1) M16D 16-Lead (0.300× Wide) Molded Small Outline, EIAJ 54F194FM (Note 2) W16A 16-Lead Cerpack 54F194LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C Note 1: Devices also available in 13× reel. Use suffix e SCX and SJX. Note 2: Military grade device with environmental and burn-in processing. Use suffix e DMQB, FMQB and LMQB. Logic Symbols Connection Diagrams Pin Assignment for DIP, SOIC and Flatpak IEEE/IEC TL/F/9498 – 1 Pin Assignment for LCC TL/F/9498 – 2 TL/F/9498–5 TL/F/9498–3 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/9498 RRD-B30M105/Printed in U. S. A. 54F/74F194 4-Bit Bidirectional Universal Shift Register November 1994 Unit Loading/Fan Out 54F/74F Pin Names Description U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL S0, S1 P0 – P3 DSR DSL CP MR Q 0 – Q3 Mode Control Inputs Parallel Data Inputs Serial Data Input (Shift Right) Serial Data Input (Shift Left) Clock Pulse Input (Active Rising Edge) Asynchronous Master Reset Input (Active LOW) Parallel Outputs 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 20 mA/b0.6 mA 20 mA/b0.6 mA 20 mA/b0.6 mA 20 mA/b0.6 mA 20 mA/b0.6 mA 20 mA/b0.6 mA b 1 mA/20 mA Functional Description The ’F194 contains four edge-triggered D flip-flops and the necessary interstage logic to synchronously perform shift right, shift left, parallel load and hold operations. Signals applied to the Select (S0, S1) inputs determine the type of operation, as shown in the Mode Select Table. Signals on the Select, Parallel data (P0 – P3) and Serial data (DSR, DSL) inputs can change when the clock is in either state, provided only that the recommended setup and hold times, with respect to the clock rising edge, are observed. A LOW signal on Master Reset (MR) overrides all other inputs and forces the outputs LOW. Mode Select Table Operating Mode Inputs Outputs MR S1 S0 DSR DSL Pn Q0 Q1 Q2 Q3 Reset L X X X X X L L L L Hold H l l X X X q0 q1 q2 q3 Shift Left H H h h l l X X l h X X q1 q1 q2 q2 q3 q3 L H Shift Right H H l l h h l h X X X X L H q0 q0 q1 q1 q2 q2 Parallel Load H h h X X pn p0 p1 p2 p3 H (h) e High Voltage Level L (l) e Low Voltage Level pn (qn) e Lower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-to-HIGH clock transition. X e Immaterial Logic Diagram TL/F/9498 – 4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 2 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b 65§ C to a 150§ C Ambient Temperature under Bias Junction Temperature under Bias Plastic b 55§ C to a 125§ C Free Air Ambient Temperature Military Commercial b 55§ C to a 125§ C 0§ C to a 70§ C Supply Voltage Military Commercial b 55§ C to a 175§ C b 55§ C to a 150§ C a 4.5V to a 5.5V a 4.5V to a 5.5V VCC Pin Potential to Ground Pin b 0.5V to a 7.0V b 0.5V to a 7.0V Input Voltage (Note 2) b 30 mA to a 5.0 mA Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0.5V to VCC Standard Output b 0.5V to a 5.5V TRI-STATEÉ Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol 54F/74F Parameter Min VIH Input HIGH Voltage VIL Input LOW Voltage Typ Units VCC Conditions Max 2.0 V Recognized as a HIGH Signal 0.8 V Recognized as a LOW Signal b 1.2 V Min IIN e b18 mA V Min IOH e b1 mA IOH e b1 mA IOH e b1 mA IOL e 20 mA IOL e 20 mA VCD Input Clamp Diode Voltage VOH Output HIGH Voltage 54F 10% VCC 74F 10% VCC 74F 5% VCC VOL Output LOW Voltage 54F 10% VCC 74F 10% VCC 0.5 0.5 V Min IIH Input HIGH Current 54F 74F 20.0 5.0 mA Max VIN e 2.7V IBVI Input HIGH Current Breakdown Test 54F 74F 100 7.0 mA Max VIN e 7.0V ICEX Output HIGH Leakage Current 54F 74F 250 50 mA Max VOUT e VCC VID Input Leakage Test 74F V 0.0 IID e 1.9 mA All Other Pins Grounded IOD Output Leakage Circuit Current 74F 3.75 mA 0.0 VIOD e 150 mV All Other Pins Grounded IIL Input LOW Current IOS Output Short-Circuit Current ICC Power Supply Current 2.5 2.5 2.7 4.75 b 60 33 3 b 0.6 mA Max VIN e 0.5V b 150 mA Max VOUT e 0V 46 mA Max AC Electrical Characteristics Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V CL e 50 pF TA, VCC e Mil CL e 50 pF TA, VCC e Com CL e 50 pF Max Min Max Min Units Min Typ fmax Maximum Shift Frequency 105 150 tPLH tPHL Propagation Delay CP to Qn 3.5 3.5 5.2 5.5 7.0 7.0 3.0 3.0 8.5 8.5 3.5 3.5 8.0 8.0 ns tPHL Propagation Delay MR to Qn 4.5 8.6 12.0 4.5 14.5 4.5 14.0 ns 90 Max 90 MHz AC Operating Requirements Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V TA, VCC e Mil TA, VCC e Com Min Min Min Max Max ts(H) ts(L) Setup Time, HIGH or LOW Pn or DSR or DSL to CP 4.0 4.0 6.0 4.0 4.0 4.0 th(H) th(L) Hold Time, HIGH or LOW Pn or DSR or DSL to CP 1.0 0 1.5 1.0 1.0 1.0 ts(H) ts(L) Setup Time, HIGH or LOW Sn to CP 10.0 8.0 10.5 8.0 11.0 8.0 th(H) th(L) Hold Time, HIGH or LOW Sn to CP 0 0 0 0 0 0 Units Max ns ns tw(H) CP Pulse Width, HIGH 5.0 5.5 5.5 ns tw(L) MR Pulse Width, LOW 5.0 5.0 5.0 ns trec Recovery Time MR to CP 9.0 9.0 11.0 ns 4 Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74F 194 S Temperature Range Family 74F e Commercial 54F e Military C X Special Variations QB e Military grade device with environmental and burn-in processing X e Devices shipped in 13× reel Device Type Package Code P e Plastic DIP D e Ceramic DIP F e Flatpak L e Leadless Chip Carrier (LCC) S e Small Outline SOIC JEDEC SJ e Small Outline SOIC EIAJ Temperature Range C e Commercial (0§ C to a 70§ C) M e Military (b55§ C to a 125§ C) Physical Dimensions inches (millimeters) 20-Lead Ceramic Leadless Chip Carrier (L) NS Package Number E20A 5 Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A 16-Lead (0.150× Wide) Molded Small Outline Package, JEDEC (S) NS Package Number M16A 6 Physical Dimensions inches (millimeters) (Continued) 16-Lead (0.300× Wide) Molded Small Outline Package, EIAJ (SJ) NS Package Number M16D 16-Lead (0.300× Wide) Molded Dual-In-Line Package (P) NS Package Number N16E 7 54F/74F194 4-Bit Bidirectional Universal Shift Register Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flatpak (F) NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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