DS78C120 Dual CMOS Compatible Differential Line Receiver General Description Features The DS78C120 is a high performance, dual differential, CMOS compatible line receiver for both balanced and unbalanced digital data transmission. The inputs are compatible with EIA, Federal and MIL standards. Input specifications meet or exceed those of the popular DS7820 line receiver. The line receiver will discriminate a ± 200 mV input signal over a common-mode range of ± 10V and a ± 300 mV signal over a range of ± 15V. Circuit features include hysteresis and response control for applications where controlled rise and fall times and/or high frequency noise rejection are desirable. Threshold offset control is provided for fail-safe detection, should the input be open or short. Each receiver includes a 180Ω terminating resistor and the output gate contains a logic strobe for time discrimination. The DS78C120 is specified over a −55˚C to +125˚C temperature range. n Full compatibility with EIA Standards RS232-C, RS422 and RS423, Federal Standards 1020, 1030 and MIL-188-114 n Input voltage range of ± 15V (differential or common-mode) n Separate strobe input for each receiver n 1/2 VCC strobe threshold for CMOS compatibility n 5k typical input impedance n 50 mV input hysteresis n 200 mV input threshold n Operation voltage range = 4.5V to 15V n Separate fail-safe mode Connection Diagram Dual-In-Line Package DS005801-1 Top View For Complete Military Product Specifications, refer to the appropriate SMD or MDS. Order Number DS78C120J/883 See NS Package Number J16A TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS005801 www.national.com DS78C120 Dual CMOS Compatible Differential Line Receiver May 1999 Absolute Maximum Ratings (Note 2) Storage Temperature Range −65˚C to +150˚C Lead Temperature (Soldering, 4 seconds) 260˚C If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage Input Voltage Strobe Voltage Output Sink Current Maximum Power Dissipation (Note 1) at 25˚C Cavity Package Molded Package Operating Conditions 18V ± 25V Supply Voltage (VCC) Temperature (TA) DS78C120 Common-Mode Voltage (VCM) 18V 50 mA 1433 mW 1362 mW Min 4.5 Max 15 Units V −55 −15 +125 +15 ˚C V Note 1: Derate cavity package 9.6 mW/˚C; derate molded package 10.9 mW/˚C above 25˚C. Electrical Characteristics (Notes 3, 4) Symbol VTH VTL Typ Max Units Differential Threshold Parameter IOUT = −200 µA, −7V ≤ VCM ≤ 7V 0.06 0.2 Voltage VOUT ≥ V CC − 1.2V IOUT = 1.6 mA,VOUT ≤ 0.5V −15V ≤ VCM ≤ 15V 0.06 0.3 V −7V ≤ VCM ≤ 7V −0.08 −0.2 V Differential Threshold Conditions Min V −15V ≤ VCM ≤ 15V −0.08 −0.3 V VTH Differential Threshold IOUT = −200 µA, −7V ≤ VCM ≤ 7V 0.47 0.7 V VTL Voltage Fail-Safe Offset = 5V VOUT ≥ VCC − 1.2V IOUT = 1.6 mA,VOUT ≤ 0.5V −7V ≤ VCM ≤ 7V RIN Input Resistance RT Line Termination Resistance −15V ≤V CM ≤ 15V, 0V ≤ VCC ≤ 15V TA = 25˚C RO Offset Control Resistance TA = 25˚C IIND Data Input Current 0V ≤ VCC ≤ 15V Voltage kΩ 100 180 300 Ω 2 3.1 mA kΩ 0 −0.5 mA −2 −3.1 mA −7V ≤ VCM ≤ 7V 0.1 0.4 V (Note 6) IOUT = 200 µA, VOUT ≥ VCC − 1.2V, RS = 500Ω −0.1 −0.4 V 0.25 0.5 V Input Balance VOH Logical “1” Output Voltage VOL Logical “0” Output Voltage I ICC Power Supply Current 15V ≤ VCM ≤ −15V, VCC = 5.5V VDIFF = −0.5V VCC = 15V (Both Receivers) V STROBE = 15V, VDIFF = 3V OUT Logical “1” Strobe Input Current IIN(0) Logical “0” Strobe Input Current V VIH Logical “1” Strobe Input VOL ≤ 0.5V, IOUT = 1.6 mA STROBE = 0V, VDIFF = −3V Voltage Logical “0” Strobe Input Voltage Output Short-Circuit Current OUT = 0V, VCC VCC = 5V VCC = 10V VCC = 15V VCC = 15V = 15V, VSTROBE = 0V, (Note 5) VCC − 0.75 V 8 15 mA 15 30 mA 15 100 µA −0.5 −100 µA 3.5 2.5 V 8.0 5.0 V 12.5 7.5 VCC = 5V VCC = 10V VOH V CC − 1.2V, IOUT = −200 µA V VCC − 1.2 = 1.6 mA, VDIFF = −1V IIN(1) IOS V 5 56 IOUT = 1.6 mA,VOUT ≤ 0.5V −7V ≤ VCM ≤ 7V RS = 500Ω I OUT = −200 µA, VDIFF = 1V VIL 0.42 4 VCM = 10V VCM = 0V VCM = −10V (Unterminated) VTHB 0.2 −5 V 2.5 1.5 V 5.0 2.0 V 7.5 2.5 V −20 −40 mA Note 2: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Note 3: Unless otherwise specified min/max limits apply across the −55˚C to +125˚C temperature range for the DS78C120. All typical values for TA = 25˚C, VCC = 5V and VCM = 0V. www.national.com 2 Electrical Characteristics (Notes 3, 4) (Continued) Note 4: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown as max or min on absolute value basis. Note 5: Only one output at a time should be shorted. Note 6: Refer to EIA-RS422 for exact conditions. Switching Characteristics VCC = 5V, TA = 25˚C Symbol Parameter tpd0(D) Differential Input to “0” Output tpd1(D) Differential Input to “1” Output tpd0(S) Strobe Input to “0” Output tpd1(S) Strobe Input to “1” Output Conditions CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF Min Typ Max 60 100 Units ns 100 150 ns 30 70 ns 100 150 ns AC Test Circuit and Switching Time Waveforms Differential and Strobe Input Signal DS005801-3 *Includes probe and test fixture capacitance DS005801-4 tr = tf ≤ 10 ns PRR = 1 MHz Note: Optimum switching response is obtained by minimizing stray capacitance on Response Control pin (no external connection). 3 www.national.com (1⁄2 Circuit Shown) DS005801-2 Schematic Diagram www.national.com 4 Application Hints Balanced Data Transmission DS005801-5 Unbalanced Data Transmission DS005801-6 Logic Level Translator DS005801-8 DS005801-7 The DS78C120 may be used a level transistor to interface between ± 12V MOS, ECL, TTL and CMOS. To configure, bias either input to voltage equal to 1⁄2 the voltage of the input signal, and the other input to the driving gate. 5 www.national.com Application Hints (Continued) LINE DRIVERS Line drivers which will interface with the DS78C120 are listed below. Balanced Drivers DS26LS31Quad RS-422 Line Driver DS7830, DS8830Dual TTL DS7831, DS8831Dual TRI-STATE ® TTL DS7832, DS8832Dual TRI-STATE TTL DS1691A, DS3691- Dual RS-422 DS1692, DS3692 Dual TRI-STATE RS-422 DS3587, DS3487Quad TRI-STATE RS-422 Unbalanced Drivers DS1488Quad RS-232 DS005801-9 FIGURE 1. Noise Pulse Width vs Response Control Capacitor DS14C88Quad RS-232 DS75150Dual RS-232 RESPONSE CONTROL AND HYSTERESIS In unbalanced (RS-232/RS-423) applications it is recommended that the rise time and fall time of the line driver be controlled to reduce cross-talk. Elimination of switching noise is accomplished in the DS78C120 by the 50 mV of hysteresis incorporated in the output gate. This eliminates the oscillations which may appear in a line receiver due to the input signal slowly varying about the threshold level for extended periods of time. High frequency noise which is superimposed on the input signal which may exceed 50 mV can be reduced in amplitude by filtering the device input. On the DS78C120, a high impedance response control pin in the input amplifier is available to filter the input signal without affecting the termination impedance of the transmission line. Noise pulse width rejection vs the value of the response control capacitor is shown in Figure 1 and Figure 2. This combination of filters followed by hysteresis will optimize performance in a worse case noise environment. DS005801-10 TRANSMISSION LINE TERMINATION On a transmission line which is electrically long, it is advisable to terminate the line in its characteristic impedance to prevent signal reflection and its associated noise/cross-talk. A 180Ω termination resistor is provided in the DS78C120 line receiver. To use the termination resistor, connect pins 2 and 3 together and pins 13 and 14 together. The 180Ω resistor provides a good compromise between line reflections, power dissipation in the driver, and IR drop in the transmission line. If power dissipation and IR drop are still a concern, a capacitor may be connected in series with the resistor to minimize power loss. The value of the capacitor is recommended to be the line length (time) divided by 3 times the resistor value. Example: if the transmission line is 1,000 feet long, (approximately 1000 ns) the capacitor value should be 1852 pF. For additional application details, refer to application notes AN-22 and AN-108. www.national.com DS005801-11 FIGURE 2. FAIL-SAFE OPERATION Communication systems require elements of a system to detect the presence of signals in the transmission lines, and it is desirable to have the system shut-down in a fail-safe mode if the transmission line is open or shorted. To facilitate the detection of input opens or shorts, the DS78C120 incorporates an input threshold voltage offset. This feature will force the line receiver to a specific logic state if presence of either fault is a condition. Given that the receiver input threshold is ± 200 mV, an input signal greater than ± 200 mV insures the receiver will be in a specific logic state. When the offset control input (pins 1 and 15) is connected to VCC = 5V, the input thresholds are offset from 200 mV to 700 mV, referred to the non-inverting input, or −200 mV to −700 mV, referred to the inverting input. Therefore, if the input is open or shorted, the input will be greater than the input threshold and the receiver will remain in a specified logic state. 6 Application Hints For unbalanced operation, the receiver would be in an indeterminate logic state if the offset control input was open. Connecting the offset to 5V offsets the receiver threshold 0.45V. The output is forced to a logic zero state if the input is open or shorted. For balanced operation with inputs shorted or open, receiver C will be in an indeterminate logic state. Receivers A and B will be in a logic zero state allowing the NOR gate to detect the short or open condition. The strobe will disable receivers A and B and may therefore be used to sample the fail-safe detector. Another method of fail-safe detection consists of filtering the output of the NOR gate D so it would not indicate a fault condition when receiver inputs pass through the threshold region, generating an output transient. In a communications system, only the control signals are required to detect input fault condition. Advantages of a balanced data transmission system over an unbalanced transmission system are: 1. High noise immunity 2. High data ratio 3. Long line lengths (Continued) The input circuit of the receiver consists of a 5k resistor terminated to ground through 120Ω on both inputs. This network acts as an attenuator, and permits operation with common-mode input voltages greater than ± 15V. The offset control input is actually another input to the attenuator, but its resistor value is 56k. The offset control input is connected to the inverting input side of the attenuator, and the input voltage to the amplifier is the sum of the inverting input plus 0.09 times the voltage on the offset control input. When the offset control input is connected to 5V the input amplifier will see VIN(INVERTING) + 0.45V or VIN(INVERTING) + 0.9V when the control input is connected to 10V. The offset control input will not significantly affect the differential performance of the receiver over its common-mode operating range, and will not change the input impedance balance of the receiver. It is recommended that the receiver be terminated (500Ω or less) to insure it will detect an open circuit in the presence of noise. The offset control can be used to insure fail-safe operation for unbalanced interface (RS-423) or for balanced interface (RS-422) operation. Unbalanced RS-423 and RS-232 Fail-Safe DS005801-12 7 www.national.com Application Hints (Continued) Balanced RS-422 Fail Safe DS005801-13 DS005801-14 DS005801-16 DS005801-15 Truth Table (For Balanced Fail-Safe) www.national.com Input Strobe A-OUT B-OUT C-OUT D-OUT 0 1 0 1 0 0 1 1 1 0 1 0 X 1 0 0 X 1 0 0 1 1 0 0 1 0 1 1 0 0 X 0 1 1 0 0 8 DS78C120 Dual CMOS Compatible Differential Line Receiver Physical Dimensions inches (millimeters) unless otherwise noted Ceramic Dual-In-Line Package (J) Order Number DS78C120J/883 NS Package Number J16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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