DS78LS120 Dual Differential Line Receiver (Noise Filtering and Fail-Safe) General Description The DS78LS120 is a high performance, dual differential, TTL compatible line receiver for both balanced and unbalanced digital data transmission. The inputs are compatible with EIA, Federal and MIL standards. The line receiver will discriminate a ± 200 mV input signal over a common-mode range of ± 10V and a ± 300 mV signal over a range of ± 15V. Circuit features include hysteresis and response control for applications where controlled rise and fall times and/or high frequency noise rejection are desirable. Threshold offset control is provided for fail-safe detection, should the input be open or short. Each receiver includes an optional 180Ω terminating resistor and the output gate contains a logic strobe for time discrimination. The DS78LS120 is specified over a −55˚C to +125˚C temperature range. Input specifications meet or exceed those of the popular DS7820 line receiver. Features n Meets EIA standards RS232-C, RS422 and RS423, Federal Standards 1020, 1030 and MIL-188-114 n Input voltage range of ± 15V (differential or common-mode) n Separate strobe input for each receiver n 5k typical input impedance n Optional 180Ω termination resistor n 50mV input hysteresis n 200mV input threshold n Separate fail-safe mode Connection Diagram Dual-In-Line-Package 00749901 Top View see RETS Data Sheet. Order Number DS78LS120J/883 or DS78LS120W/883 See NS Package Number J16A or W16A © 2004 National Semiconductor Corporation DS007499 www.national.com DS78LS120 Dual Differential Line Receiver (Noise Filtering and Fail-Safe) September 1999 DS78LS120 Absolute Maximum Ratings (Note 2) Lead Temperature (Soldering, 4 sec) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage Operating Conditions Min Max Supply Voltage (VCC) 4.5 5.5 V Temperature (TA) −55 +125 ˚C Common-Mode Voltage (VCM) −15 +15 V 7V ± 25V Input Voltage Strobe Voltage 7V Output Sink Current Storage Temperature Range 260˚C 50 mA Units −65˚C to +150˚C Maximum Power Dissipation at 25˚C (Note 1) 1433 mV Electrical Characteristics (Notes 3, 4) Symbol VTH VTL Parameter Differential Threshold Voltage Differential Threshold Voltage Conditions IOUT = −400 µA, VOUT ≥ 2.5V IOUT = 4 mA, VOUT ≤ 0.5V Min Typ Max Units −7V ≤ VCM ≤ 7V 0.06 0.2 −15 ≤ VCM ≤15V 0.06 0.3 V −7V ≤ VCM ≤7V −0.08 −0.2 V −15V ≤ VCM ≤ 15V −0.08 −0.3 V V VTH Differential Threshold Voltage IOUT = −400 µA, VOUT ≥ 2.5V −7V ≤ VCM ≤ 7V 0.47 VTL with Fail-Safe Offset = 5V IOUT = 4 mA, VOUT ≤ 0.5V −7V ≤ VCM ≤ 7V −0.2 −0.42 RIN Input Resistance −15V ≤ VCM ≤ 15V, 0V ≤ VCC ≤ 7V 4 5 0.7 V V kΩ RT Line Termination Resistance TA = 25˚C 100 180 300 Ω RO Offset Control Resistance TA = 25˚C 42 56 70 kΩ IIND Data Input Current (Unterminated) VCM = 10V VCM = 0V 2 3.1 mA 0V ≤ VCC ≤ 7V 0 −0.5 mA −2 −3.1 mA −7V ≤ VCM 7V 0.1 0.4 V −7V ≤ VCM ≤ 7V −0.1 −0.4 V 0.35 0.5 V VCM = −10V VTHB Input Balance IOUT = −400 µA, VOUT ≥ 2.5V, (Note 6) RS = 500Ω IOUT = 4 mA, VOUT ≤ 0.5V, RS = 500Ω VOH Logical “1” Output Voltage IOUT = −400 µA, VDIFF = 1V, VCC = 4.5V VOL Logical “0” Output Voltage IOUT = 4 mA, VDIFF = −1V, VCC = 4.5V ICC Power Supply Current VCC = 5.5V VCM = 15V 10 16 mA VDIFF = −0.5V, (Both Receivers) VCM = −15V 10 16 mA 1 100 µA −290 −400 µA IIN (1) Logical “1” Strobe Input Current IIN (0) Logical “0” Strobe Input Current VSTROBE = 0V, VDIFF = −3V VIH Logical “1” Strobe Input Voltage VOL ≤ 0.5, IOUT = 4mA VIL Logical “0” Strobe Input Voltage VOH ≥ 2.5V, IOUT, = −400 µA IOS Output Short-Circuit Current VOUT = 0V, VCC = 5.5V, VSTROBE = 0V,(Note 5) 2.5 VSTROBE = 5.5V, VDIFF = 3V 2.0 3 1.12 1.12 −30 V V 0.8 −100 −170 V mA Note 1: Derate cavity package 9.6 mW/˚C above 25˚C. Note 2: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Note 3: Unless otherwise specified min/max limits apply across the −55˚C to +125˚C temperature range for the DS78LS120. All typical values are for TA = 25˚C, VCC = 5V and VCM = 0V. Note 4: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown as max or min on absolute value basis. Note 5: Only one output at a time should be shorted. Note 6: Refer to EIA-RS422 for exact conditions. www.national.com 2 VCC = 5V, TA = 25˚C Symbol Parameter tpd0(D) Differential Input to “0” Output Conditions Min Typ Max Units 38 60 ns tpd1(D) Differential Input to “1” Output 38 60 ns tpd0(S) Strobe Input to “0” Output 16 25 ns tpd1(S) Strobe Input to “1” Output 12 25 ns Response Pin Open, CL = 15 pF, RL = 2 kΩ AC Test Circuit and Switching Time Waveforms Differential and Strobe Input Signal 00749903 Includes probe and test fixture capacitance 00749904 Note: Optimum switching response is obtained by minimizing stray capacitance on Response Control pin (no external connection). Application Hints Balanced Data Transmission 00749905 3 www.national.com DS78LS120 Switching Characteristics DS78LS120 Application Hints (Continued) Unbalanced Data Transmission 00749906 RESPONSE CONTROL AND HYSTERESIS In unbalanced (RS-232/RS-423) applications it is recommended that the rise time and fall time of the line driver be controlled to reduce cross-talk. Elimination of switching noise is accomplished in the DS78LS120 by the 50 mV of hysteresis incorporated in the output gate. This eliminates the oscillations which may appear in a line receiver due to the input signal slowly varying about the threshold level for extended periods of time. High frequency noise which is superimposed on the input signal which may exceed 50 mV can be reduced in amplitude by filtering the device input. On the DS78LS120, a high impedance response control pin in the input amplifier is available to filter the input signal without affecting the termination impedance of the transmission line. Noise pulse width rejection vs the value of the response control capacitor is shown in Figure 1 and Figure 2. This combination of filters followed by hysteresis will optimize performance in a worse case noise environment. 00749907 Logic Level Translator 00749908 The DS78LS120 may be used as a level translator to interface between ± 12V MOS, ECL, TTL and CMOS. To configure, bias either input to a voltage equal to 1⁄2 the voltage of the input signal, and the other input to the driving gate. LINE DRIVERS Line drivers which will interface with the DS78LS120 are listed below. Balanced Drivers DS26LS31: Quad RS-422 Line Driver, Dual CMOS DS7830, DS8830: Dual TTL DS7831, DS8831: Dual TRI-STATE TTL DS7832, DS8832: Dual TRI-STATE TTL DS1691A, DS3691: Quad RS-423/Dual RS-422 TTL DS1692, DS3692: Quad RS-423/Dual TRI-STATE RS-422 TTL DS3487: Quad TRI-STATE RS-422 Unbalanced Drivers DS1488: Quad RS-232 DS75150: Dual RS-232 www.national.com 00749909 FIGURE 1. Noise Pulse Width vs Response Control Capacitor 4 mode if the transmission line is open or shorted. To facilitate the detection of input opens or shorts, the DS78LS120 incorporates an input threshold voltage offset. This feature will force the line receiver to a specific logic state if presence of either fault is a condition. Given that the receiver input threshold is ± 200 mV, an input signal greater than ± 200 mV insures the receiver will be in a specific logic state. When the offset control input (pins 1 and 15) is connected to VCC = 5V, the input thresholds are offset from 200 mV to 700 mV, referred to the non-inverting input, or −200 mV to −700 mV, referred to the inverting input. Therefore, if the input is open or shorted, the input will be greater than the input threshold and the receiver will remain in a specified logic state. (Continued) The input circuit of the receiver consists of a 5k resistor terminated to ground through 120Ω on both inputs. This network acts as an attenuator, and permits operation with common-mode input voltages greater than ± 15V. The offset control input is actually another input to the attenuator, but its resistor value is 56k. The offset control input is connected to the inverting input side of the attenuator, and the input voltage to the amplifier is the sum of the inverting input plus 0.09 times the voltage on the offset control input. When the offset control input is connected to 5V the input amplifier will see VIN(INVERTING) +0.45V or VIN(INVERTING) +0.9V when the control input is connected to 10V. The offset control input will not significantly affect the differential performance of the receiver over its common-mode operating range, and will not change the input impedance balance of the receiver. It is recommended that the receiver be terminated (500Ω or less) to insure it will detect an open circuit in the presence of noise. The offset control can be used to insure fail-safe operation for unbalanced interface (RS-423) or for balanced interface (RS-422) operation. For unbalanced operation, the receiver would be in an indeterminate logic state if the offset control input was open. Connecting the fail-safe offset pin to 5V, offsets the receiver threshold to 0.45V. The output is forced to a logic zero state if the input is open or shorted. 00749910 FIGURE 2. TRANSMISSION LINE TERMINATION On a transmission line which is electrically long, it is advisable to terminate the line in its characteristic impedance to prevent signal reflection and its associated noise/cross-talk. A 180Ω termination resistor is provided in the DS78LS120 line receiver. To use the termination resistor, connect pins 2 and 3 together and pins 13 and 14 together. The 180Ω resistor provides a good compromise between line reflections, power dissipation in the driver, and IR drop in the transmission line. If power dissipation and IR drop are still a concern, a capacitor may be connected in series with the resistor to minimize power loss. The value of the capacitor is recommended to be the line length (time) divided by 3 times the resistor value. Example: if the transmission line is 1,000 feet long, (approximately 1000 ns), and the termination resistor value is 180Ω, the capacitor value should be 1852 pF. For additional application details, refer to application notes AN-22 and AN-108. FAIL-SAFE OPERATION Communication systems require elements of a system to detect the presence of signals in the transmission lines, and it is desirable to have the system shut-down in a fail-safe Unbalanced RS-423 and RS-232 Fail-Safe 00749911 5 www.national.com DS78LS120 Application Hints DS78LS120 Application Hints (Continued) 00749912 Balanced RS-422 Fail-Safe 00749913 00749914 For balanced operation with inputs open or shorted, receiver C will be in an indeterminate logic state. Receivers A and B will be in a logic zero state allowing the NOR gate to detect the open or short condition. The strobe will disable receivers A and B and may therefore be used to sample the fail-safe detector. Another method of fail-safe detection consists of filtering the output of NOR gate D so it would not indicate a fault condition when receiver inputs pass through the threshold region, generating an output transient. www.national.com In a communications system, only the control signals are required to detect input fault conditions. Advantages of a balanced data transmission system over an unbalanced transmission system are: 1. High noise immunity 2. High data ratio 3. Long line lengths 6 DS78LS120 Truth Table (For Balanced Fail-Safe) Input Strobe A-Out B-Out C-Out D-Out 0 1 0 1 0 0 1 1 1 0 1 0 X 1 0 0 X 1 0 0 1 1 0 0 1 0 1 1 0 0 X 0 1 1 0 0 Schematic Diagram 00749902 7 www.national.com DS78LS120 Physical Dimensions inches (millimeters) unless otherwise noted Ceramic Dual-In-Line Package (J) Order Number DS78LS120J/883 NS Package Number J16A Ceramic Dual-In-Line Package (W) Order Number DS78LS120W/883 NS Package Number W16A www.national.com 8 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. 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