AEIC-7272-S16 Quad Differential Line Driver Separate Logic Bias and Driver Bias With Tri-State Outputs Data Sheet Description Features These line drivers are pin compatible with 26LS31 in applications where pin 4 = 5V and pin 12 = GND. Internal clamp diodes allow trouble-free operation when driving cable lengths exceeding 100m. Split supplies are provided to minimize standby power dissipation in high voltage applications. The logic should be powered from a regulated 5V supply at the VccBias pin. The output stages may then be powered by a separate supply at VccDrivers, up to 30V. Output voltage swings of 0.3V to VCC-1.9V are typical. The outputs are protected against shorts to ground, shorts to Vcc and to other outputs, by a two-fold scheme of current limiting and thermal shutdown. This assures highly reliable operation in harsh environments. Supply (Bias) Voltage Range 3.5 V to 30 V Operation to 800 KHz CMOS and TTL Compatible Inputs Separate logic bias and driver supply pins Optional single supply operation for moderate power applications High Impedance Buffered Inputs with hysteresis Tri-State outputs 80 mA peak SINK/SOURCE current Pin Assignment This part is available in 16L SOIC (Pb-free) package. Applications Encoders Industrial controls AIN 1 16 Vcc Drivers A+ 2 15 DIN A- 3 14 D+ Vcc Bias 4 VREG 13 D- B- 5 12 EN- B+ 6 11 C- BIN 7 10 C+ GND 8 9 CIN Table 1. Absolute Maximum Ratings Parameters Symbol Min. Max. Units Operating Temperature Range TA -55 125 °C Supply (Driver) Voltage Range VCCD 4.5 30 V Test Conditions Table 2. Electrical Characteristics Unless otherwise specified, TA = 25° C and EN- < 0.8 V. Parameters Symbol Min. Typ. Max. Units Test Conditions Overtemp Operate Point (junction) TJOP - 172 - °C Note 1 Overtemp Release Point (junction) TJRP - 136 - °C Note 1 Vcc Bias Voltage Range VCCB 3.5 5 30 V Vcc Drivers Voltage Range VCCD 4.5 5 30 V Supply Current VCCB1 (BIAS) ICCB1 - 11.9 16.0 mA VCCB and VCCD = 5 V Supply Current VCCD1 (DRIVERS) ICCD1 - 2.4 3.3 mA VCCB and VCCD = 5 V Supply Current VCCB2 ICCB2 - 2.5 3.4 mA VCCB and VCCD = 5 V, EN- > 2 V Supply Current VCCD2 ICCD2 - 0.0 0.1 mA VCCB and VCCD = 5 V, EN- > 2 V Supply Current VCCB3 ICCB3 - 12.1 18.5 mA VCCB and VCCD = 30 V Supply Current VCCD3 ICCD3 - 2.4 3.3 mA VCCB and VCCD = 30 V Supply Current VCCB4 ICCB4 - 2.6 3.5 mA VCCB and VCCD = 30 V, EN- > 2 V Supply Current VCCD4 ICCD4 - 0.0 0.1 mA VCCB and VCCD = 30 V, EN- > 2 V Enable Input Threshold V THE 0.8 1.5 2 V Enable Low Level Input Current IILE -10 0 10 A VIN = 0 V, VCCB = 5 V Enable High Level Input Current IIHE – 108 150 A VIN = 5 V, VCCB = 5 V High Impedance Output Leakage IOZ -4.0 0.0 4.0 A VCCD = 30 V, EN- > 2 V, Output at 15 V Input Positive-Going Threshold V T+ 1.05 1.25 1.45 V VCCB = 5 V Input Negative-Going Threshold V T- 0.75 0.95 1.15 V VCCB = 5 V Input Hysteresis VH – 0.3 – V VCCB = 5 V Low Level Input Current IIL -4.0 -0.1 - A VIN = 0 V, VCCB = 5 V High Level Input Current IIH - 0 4.0 A VIN = 5 V, VCCB = 5 V Low Level Output1 VOL1 - 375 500 mV IOL = 20 mA, VCCD = 5 V Low Level Output2 VOL2 - 370 500 mV IOL = 20 mA, VCCD =30 V High Level Output1 VOH1 2.4 2.8 - V IOH = -20 mA, VCCD = 5 V High Level Output2 VOH2 27.7 28.1 - V IOH = -20 mA, VCCD =30 V Note: 1. This is not a test parameter, but for information only. Table 3. AC Switching Characteristics Values given at VCCB = 5 V, VCCD = 24 V, TA = 25° C, CL = 1000 pF on all outputs, and EN- < 0.8 V. Parameters Symbol Min. Typ. Max. Units Test Conditions Propagation delay, rising input 50% point to zero crossing of differential outputs TPLH - 450 630 ns See above. Propagation delay, falling input 50% point to zero crossing of differential outputs TPHL - 450 630 ns See above. Output Rise Time TR - 700 980 ns See above. Output Fall Time TF - 700 980 ns See above. 2 Package Drawings (Dimensions in Inches) D CL X CL E PIN NO. 1 ID MARK 0.010 2 e DETAIL “A” B ±0.004 0.015 X 45° A A1 16 SOIC Symbol Min Max A 0.054 0.068 A1 0.004 0.0098 B 0.014 0.019 D 0.386 0.393 E 0.150 0.157 H 0.229 0.244 e 0.0075 0.0098 L 0.016 0.034 X θ1 θ2 H Notes: 1. Lead coplanarity should be o to 0.004" max. 2. Package surface finishing: VD1 24~27 (Dual). Package surface finishing: VD1 13~15 (16L Soic(NB) Matrix). 3. All dimension excluding mold flashes. 4. The lead width, B to be determined at 0.0075" from the lead tip. 0.020 REF 0° 8° 7° BSC For product information and a complete list of distributors, please go to our web site: DETAIL “A” C 1 0.050 BSC C L GAUGE PLANE SEATING PLANE www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved. AV02-3021EN - January 12, 2012