ELMOS E909-06

E909.06
HALIOS® MULTI PURPOSE SENSOR FOR AUTOMOTIVE
PRODUCTION DATA - NOV 16, 2011
Features
Applications
ÿ Sensor IC based on HALIOS® technology
ÿ Up to 4 sending channels, 1 compensation channel an 1 differential receiver input for various HALIOS®
applications
ÿ 16 bit micro controller ‘EL16’ with debug interface
ÿ Up to 1.5K x 18 (3KByte) SRAM including 2 bit
parity per 16 bit word and byte write support
ÿ Up to 30K x 22 (60KByte) FLASH including
6 bit CRC checksum per 16 bit word
ÿ SPI and I2C communication interface
ÿ SCI interface incl. LIN support
ÿ Watchdog, 32 bit timer, up to 8 GPIOs
ÿ Multiply unit
ÿ AEC-Q100 automotive qualification
ÿ Supply voltage range 2.25V to 2.75V
ÿ
ÿ
ÿ
Ordering Information
Product ID
Temp. Range
Package
E909.06
-40°C to +85°C
QFN32L5
AVDD
KA
AMP_KA
VDDC
The IC is based on an optical bridge technology which
provides a non-mechanical detection of movements.
The system detects the optical reflections of an object in front of the sensor by using a function principle
called HALIOS® (High Ambient Light Independent Optical System) which is very effective in the suppression
of ambient light and also has self calibration capability
to eliminate disturbances caused by housing reflections
and scratches.
In the same manner capacitive systems can be addressed by using the integrated charge amplifier.
TMODE
reset clock
AMP_AN
AN
General Description
NRST
+
+
-
Optical or capacitive input devices
Proximity and gesture detection
Compact HMI interfaces for one-dimensional up to three-dimensional input
CPU core
16 bit
test
J
T
A
G
RAM
TM1
Flash
LED1
VPP
MISO
LED2
LED3
HALIOS ®
control
LED4
digital/
analog
LEDC
TM0
multiply
SPI
interface
watchdog
LIN SCI
IRQ
control
GPIO
interface
timer
I2C
interface
MOSI
8
SCK
GPIO
VDDIO
CS
RX
TX
SDA
SDA
SCL
SCL
E909.06
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG
Data Sheet 1/71
QM-No.: 25DS0049E.02
E909.06
HALIOS® MULTI PURPOSE SENSOR FOR AUTOMOTIVE
PRODUCTION DATA - NOV 16, 2011
1 Pinout
1.1 Pin description
No
Name
Type 1)
Pull
ESD
Description
1
GPIO_7
D_IO
Down
+/- 2KV HBM D IO PD Sr - General Purpose IO 7
2
GPIO_6
D_IO
Down
+/- 2KV HBM D IO PD Sr - General Purpose IO 6
3
GPIO_5
D_IO
Down
+/- 2KV HBM D IO PD Sr - General Purpose IO 5
4
GPIO_4
D_IO
Down
+/- 2KV HBM D IO PD Sr - General Purpose IO 4
5
GPIO_3
D_IO
Down
+/- 2KV HBM D IO PD Sr - General Purpose IO 3
6
GPIO_2
D_IO
Down
+/- 2KV HBM D IO PD Sr - General Purpose IO 2
7
GPIO_1
D_IO
Down
+/- 2KV HBM D IO PD Sr - General Purpose IO 1
8
GPIO_0
D_IO
Down
+/- 2KV HBM D IO PD Sr - General Purpose IO 0
9
LED1
A_O
-
+/- 2KV HBM A O - LED Driver output
10
VSSLED1,2
S
-
+/- 2KV HBM A G - Ground LED1,2
11
LED2
A_O
-
+/- 2KV HBM A O - LED Driver output
12
LED3
A_O
-
+/- 2KV HBM A O - LED Driver output
13
VSSLED3,4
S
-
+/- 2KV HBM A G - Ground LED3,4
14
LED4
A_O
-
+/- 2KV HBM A O - LED Driver output
15
VSSLEDC
S
-
+/- 2KV HBM A G - Ground LEDC
16
LEDC
A_O
-
+/- 2KV HBM A O - LED Driver output
17
I2C_SDA
D_IO
-
+/- 2KV HBM D IO - I2C SDA (Data)
18
I2C_SCL
D_IO
-
+/- 2KV HBM D IO - I2C SCL (CLK)
19
VDDC
S
-
+/- 2KV HBM D S - Core Supply 2.5V
20
VSS
S
-
+/- 2KV HBM D G - Ground
21
VDDIO
S
-
+/- 2KV HBM D S - IO Supply 3.3V
22
AMP_KA
A_O
-
+/- 2KV HBM A O - Output 1. stage amplifier at KA
23
AVDD
S
-
+/- 2KV HBM A S - Analog Supply 2.5V
24
KA
A_I
-
+/- 2KV HBM A I - Kathode
25
AN
A_I
-
+/- 2KV HBM A I - Anode
26
AVSS
S
-
+/- 2KV HBM A G - Analog Ground
27
AMP_AN
A_O
-
+/- 2KV HBM A O - Output 1. stage amplifier at AN
28
NRST
D_I
Up
29
TMODE
D_I
Down
30
TM1
A_IO
-
+/- 2KV HBM A IO - Analog Testbus
31
TM0
A_IO
-
+/- 2KV HBM A IO - Analog Testbus
32
VPP
HV_S
-
+/- 2KV HBM A HV - FLASH program voltage
+/- 2KV HBM D I PU St - Reset
+/- 2KV HBM D I PD - Testmode
1) D = Digital, A = Analog, S = Supply, I = Input, O = Output, HV = High Voltage
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ELMOS Semiconductor AG
Data Sheet
2/71
QM-No.: 25DS0049E.02
E909.06
HALIOS® MULTI PURPOSE SENSOR FOR AUTOMOTIVE
PRODUCTION DATA - NOV 16, 2011
1.2 Package Pinout
Package: QFN32L5
21 20
19 18
I2C_SDA
I2C_SCL
22
VDDC
AMP_KA
23
VSS
AVDD
24
VDDIO
KA
Package is according JEDEC MO-220-K, version VHHD-4.
17
AN 25
16
LEDC
AVSS 26
15
VSSLEDC
AMP_AN 27
14
LED4
NRST 28
13
VSSLED3,4
TMODE 29
12
LED3
TM1
30
11
LED2
TMO 31
10
VSSLED1,2
9
LED1
1
2
3
4
5
6
7
8
GPIO_7
GPIO_6
GPIO_5
GPIO_4
GPIO_3
GPIO_2
GPIO_1
GPIO_0
VPP 32
Figure 1: Package Pinout
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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Data Sheet
3/71
QM-No.: 25DS0049E.02
E909.06
HALIOS® MULTI PURPOSE SENSOR FOR AUTOMOTIVE
PRODUCTION DATA - NOV 16, 2011
2 Operating Conditions
2.1 Absolute Maximum Ratings
Continuous operation of the device above these ratings is not allowed and may destroy the device. All potentials
refer to GROUND (GND) unless otherwise specified. Currents flowing into the circuit pins have positive values.
No.
Condition
Symbol
Min.
Max.
Unit
1
Supply voltage: digital core,
analog part
Description
Referenced
to VSS / AVSS
VDDC / AVDD
-0.3
2.8
V
2
IO supply voltage/digital pins
(see "type"/chapter )
Referenced
to VSS
VDDIO
-0.3
3.7
V
3
Input voltage analog pins
(see "type"/chapter )
Referenced
to AVSS
VINA
-0.3
AVDD + 0.3
V
4
Input voltage digital pins/GPIO
(see "type"/chapter )
Referenced
to VSS
VIND
-0.3
VDDIO + 0.3
V
5
Ground offset
VSS to AVSS to
VSSLED
Ground
offset
-0.3
0.3
V
6
Junction Temperature
TJ
-40
+125
°C
7
Storage Temperature
TSTG
-50
150
°C
2.2 Recommended Operating Conditions
The following conditions apply unless otherwise stated. All potentials refer to GROUND (GND) unless otherwise
specified. Currents flowing into the circuit pins have positive values.
No.
Description
1
Supply voltage: analog part,
digital core
2
IO supply voltage/digital pins
(see "type"/chapter )
3
Condition
Symbol
Referenced to V / A
DDC
VDD
VSS / AVSS
Min.
Typ.
Max.
Unit
2.25
2.5
2.75
V
3.0
3.3
3.6
V
Referenced
to VSS
VDDIO
Filter capacitor analog part
Connected to
AVDD
CAVDD
10
µF
4
Filter capacitor digital part
Connected to
VDDC
CVDDC
100
nF
5
Ambient operating temperature range
TOPT
-40
25
85
°C
All voltages are referred to VSS, and currents are positive when flowing into the node unless otherwise specified.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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Data Sheet
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QM-No.: 25DS0049E.02
E909.06
HALIOS® MULTI PURPOSE SENSOR FOR AUTOMOTIVE
PRODUCTION DATA - NOV 16, 2011
3 Detailed Electrical Specification
The following conditions apply unless otherwise stated. All potentials refer to GROUND (GND) unless otherwise
specified. Currents flowing into the circuit pins have positive values.
3.1 Supply Voltages
No.
Description
Condition
Symbol
Typ.
Max.
Unit
IVDDC
5.8
12
mA
1.8
5
mA
35
µA
5
mA
15
µA
1
Digital operating current, run FSYS = 8 MHz,
system state:
mode
run
2
Digital operating current,
standby mode
System state:
standby
ISTANDBY
3
Digital operating current, off
mode
System state:
off
IOFF
IAVDD
IAVDD_OFF
4
Analog operating current
MCR[13:12]
="11"
PCR[14:13]
="11"
5
Analog operating current
Analog on = 0
6
Over all current consumption Active mode 1)
in application mode
7
Over all current consumption
in application mode
8
State change from STANDBY
to RUN mode
TSTANDB-
State change from OFF to
RUN mode
TOFF2RUN
9
Min.
3.5
IACTIVE
2.0
2.25
mA
IIDLE
16
50
µA
3
1/
FSYS
5
1/
FSYS
Idle mode
(IIDLE = IOFF +
IAVDD_OFF)
Y2RUN
1) In application mode the current consumption is calculated from the duty cycle of the digital operating current and the
analog operating current.
MCR - Measurement Configuration Register
PCR - Preamplifier Configuration Register
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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Data Sheet
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QM-No.: 25DS0049E.02
E909.06
HALIOS® MULTI PURPOSE SENSOR FOR AUTOMOTIVE
PRODUCTION DATA - NOV 16, 2011
3.2 Reset Generation
No.
Description
Condition
Symbol
Min.
1
Power on reset level
Reference is
VDDC
VPOR
2
Brown out high-to-low
threshold level
Reference is
VDDC
VBOHL
1.8
3
Brown out reset hysteresis
VBOHYST
100
4
Minimum supply voltage for
power on reset and brown
out circuit 1)
5
NRST-pin threshold level
6
Pull up current NRST-pin
7
Min. pulse width for a valid
reset at pin NRST
(debouncing)
8
Delay Watchdog start =>
reset 1)
Typ.
Max.
Unit
2.25
V
V
200
300
mV
VDDmin
0.9
V
NRSTLH
0.5
VDDIO
VNRST = VDDIO
INRSTPU
35
µA
VDDC > VDDC min
TDEBNRST
1.0
timer
value
TWDOG
µs
1/
FSYS
1) Will not be tested in production test
3.3 Internal Clock Generation
3.3.1 Reference Clocks
No.
Description
Condition
Symbol
Min.
Typ.
Max.
Unit
FWK
115.2
128.0
140.8
kHz
FSYS
7.2
8.0
8.8
MHz
1
Wakeup clock frequency
Within recommended
operating
conditions
2
Master clock
Within recommended
operating
conditions
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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Data Sheet
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QM-No.: 25DS0049E.02
E909.06
HALIOS® MULTI PURPOSE SENSOR FOR AUTOMOTIVE
PRODUCTION DATA - NOV 16, 2011
3.4 Module Description
3.4.1 I²C Interface
No.
Description
Condition
Symbol
Min.
Typ.
Max.
Unit
1
SDA/SCL: Input voltage low
VIL
-0.3
0.3 x VDDIO
V
2
SDA/SCL: Input voltage high
VIH
0.7 x VDDIO
VDDIO + 0.3
V
3
SDA/SCL: Hysteresis of Schmitt trigger inputs 1)
Vhys
0.05 x VDDIO
-
V
4
SDA/SCL: Output voltage low I = 3 mA, VDDIO
(open drain)
> 2.0 V
0.4
V
5
SDA/SCL: Input current
6
VDDIO > 2.0 V
VOL
0 < VIN < VDDIO
Ii
-10
10
µA
SDA/SCL: capacitance 1)
Ci
-
10
pF
7
SCL clock frequency
fSCL
0
400
kHz
8
Hold time (repeated) START
condition 1)
tHD.:STA
600
-
ns
9
LOW period of SCL clock
tLOW
1300
-
ns
10
HIGH period of SCL clock
tHIGH
600
-
ns
11
Set-up time for repeated
start condition 1)
tSU.:STA
600
-
ns
12
Data hold time 1)
tHD.DAT
0
900
ns
13
Data set-up time 1)
tSU:DAT
100
-
ns
14
Rise time of SDA and SCL signals with a bus capacitance
(Cb) from 10 pF to 400 pF 1)
tr
20 + 0.1 x Cb
300
ns
15
Fall time of SDA and SCL signals with a bus capacitance
(Cb) from 10 pF to 400 pF 1)
tf
20 + 0.1 x Cb
300
ns
16
SDA/SCL: Output fall time
from VIH to VIL with a bus
capacitance (Cb) from 10 pF
to 400 pF 1)
tof
20 + 0.1 x Cb
250
ns
17
Set-up time for STOP condition 1)
tSU:STO
600
-
ns
18
Bus free time between STOP
and START 1)
tBUF
1300
-
ns
19
Pulse with of spikes which
must be suppressed by the
IC-internal input filter
tSP
0
50
ns
1) Will not be tested in production test
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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Data Sheet
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QM-No.: 25DS0049E.02
E909.06
HALIOS® MULTI PURPOSE SENSOR FOR AUTOMOTIVE
PRODUCTION DATA - NOV 16, 2011
3.4.2 SPI Module
No.
Description
Condition
Symbol
Min.
Typ.
Max.
Unit
transfer
Tck
4
1/
FSYS
1
SCK pulse low width / pulse
high width
2
First SCK after falling CSB
start of
transfer
Tcs1
2
1/
FSYS
3
Last SCK before rising CSB
end of
transfer
Tcs2
2
1/
FSYS
4
Setup time
Tsetup
1
1/
FSYS
5
Hold time
Thold
1
1/
FSYS
6
Data out after shift
Tso
7
CSB high time
Tcsh
8
Data out change from Z to
driven data
start of
transfer
Tz1
1
1/
FSYS
9
Data out change from driven
data to Z
end of
transfer
Tz2
1
1/
FSYS
1/
FSYS
3
1/
FSYS
2
3.4.3 GPIO Module
No.
Description
Condition
Symbol
Min.
Typ.
Max.
Unit
GPIOTH
1.2
1.32
1.46
V
54
130
kΩ
0.4
V
1
Threshold point
2
Pull down resistor
VIN > 0.75 · VDDIO
RGPIOPD
3
Output Voltage Low
GPIOIOL=4 mA;
VDDIO=3.3 V
GPIOVOL
4
Output Voltage High
GPIOIOH=-4 mA;
VDDIO=3.3 V
GPIOVOH
2.4
5
Low Level Output Current
GPIOVOL=0.4V
GPIOIOL
6
12
mA
6
High Level Output Current
GPIOVOH=2.4V
GPIOIOH
-25.6
-7.8
mA
7
Tri-State Input/Output
Leakage Current
Vout=VDDIO or 0 V
GPIOILC
-1
1
µA
V
3.4.4 HALIOS® Interface
3.4.4.1 Current Generation for LED Modulators
No.
Description
Condition
Symbol
Min.
Typ.
Max.
Unit
1
DAC resolution
N
10
bit
2
Integral non linearity (INL)
Ei
2
LSB
3
Differential non linearity
(DNL)
Ed
2
LSB
4
DAC output voltage at full
scale
VMAX
1.22
V
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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Data Sheet
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QM-No.: 25DS0049E.02
E909.06
HALIOS® MULTI PURPOSE SENSOR FOR AUTOMOTIVE
PRODUCTION DATA - NOV 16, 2011
3.4.4.2 LED Driver 1 - 4
No.
Description
Condition
Symbol
DAC = 0
IR_MINS
Min.
Typ.
Max.
Unit
5 % if IR_MAXS 1)
mA
1
Regulated proportion of LED
current @ DAC = 0
2
Max. regulated proportion of
LED current (RANGE)
RANGE = 31,
IR_MAXS
10.0
mA
3
Stepsize for regulated current-range configuration
DAC = 1023
IR_STEPS
290
µA
4
Resolution current-range
configuration
NRS
5
bit
5
Max. fixed proportion of LED
current (OFFSET)
IO_MAXS
10.0
mA
6
Stepsize for fixed offset-current configuration
I_STEPS
290
µA
7
Resolution offset-current
configuration
NOS
5
bit
8
DC-bias current
IBIAS S
225
µA
OFFSET = 31
1) IR_MAXS is the maximum current selected with parameter RANGE
3.4.4.3 LED Driver C
No.
Description
Condition
Symbol
Min.
Typ.
Max.
Unit
DAC = 0
IR_MINC
5 % of
IR_MAXS 1)
mA
RANGE = 31,
DAC = 1023
IR_MAXC
4.0
mA
1
Regulated proportion of LED
current @ DAC = 0
2
Max. regulated proportion of
LED current (RANGE)
3
Stepsize for regulated current-range configuration
IR_STEPC
125.0
µA
4
Resolution current-range
configuration
NRC
5
bit
5
Max. fixed proportion of LED
current (OFFSET)
IO_MAXC
5.0
mA
6
Stepsize for fixed offset-current configuration
IO_STEPC
40.0
µA
7
Resolution offset-current
configuration
NOC
7
bit
8
Minimal value for DC-bias
current
IBIA_C0
100
µA
9
Stepsize for DC-bias current
IDCO_STEPC
2.5
mA
10
Max. DC-bias current
(DC_OFFSET)
IDCO_MAXC
37.6
mA
OFFSET = 127
DC_OFFSET
= 15
1) IR_MAXS is the maximum current selected with parameter RANGE
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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Data Sheet
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QM-No.: 25DS0049E.02
E909.06
HALIOS® MULTI PURPOSE SENSOR FOR AUTOMOTIVE
PRODUCTION DATA - NOV 16, 2011
3.4.4.4 Receiver
No.
Description
Condition
Symbol
Min.
Typ.
Max.
Unit
1
Feedback resistor of 1. stage
amplifier at input KA and AN;
bit 0, bit 1 = 1
Rf
50
kΩ
2
Feedback capacitor of 1.
stage amplifier at input KA
and AN; bit 2, bit 3 = 1
Cf
3.6
pF
3
DC photo-current Gyrator
mode; bit 9, bit 10 = 1
IDC_photo
4
Voltage at amplifier input KA
VKA
1.9
V
5
Voltage at amplifier input AN
VAN
1.3
V
6
Corner frequency highpass
filter
fG
10
kHz
7
Gain amplifier 2. stage
G0
6
dB
8
Gain amplifier 3. stage
PCR[8:7]="01"
G3
12
dB
9
Gain amplifier 3. stage
PCR[8:7]="00"
or "11"
G3
24
dB
10
Gain amplifier 3. stage
PCR[8:7]="10"
G3
36
dB
11
Total gain sym. input
PCR[8:7]="01"
GTOT
118
dBΩ
12
Total gain sym. input
PCR[8:7]="00"
or "11"
GTOT
130
dBΩ
13
Total gain sym. input
PCR[8:7]="10"
GTOT
142
dBΩ
14
Total gain nonsym. input
PCR[8:7]="01"
GTOT
112
dBΩ
15
Total gain nonsym. input
PCR[8:7]="00"
or "11"
GTOT
124
dBΩ
16
Total gain nonsym. input
PCR[8:7]="10"
GTOT
136
dBΩ
17
Center frequency
fC
125
kHz
18
Resolution demodulator
output
NDEMOD
1
bit
19
Capacitance of photo diode
at input KA
CDIODE
20
Internal reference voltage
VREF
1.22
V
21
Internal reference current
IBIAS
10
µA
µA
70
pF
PCR - Preamplifier Configuration Register
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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Data Sheet
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QM-No.: 25DS0049E.02
E909.06
HALIOS® MULTI PURPOSE SENSOR FOR AUTOMOTIVE
PRODUCTION DATA - NOV 16, 2011
4 Functional Description
4.1 Introduction
The general architecture of the 3D-optical input device is shown in the system block diagram.
The CPU is connected to the memory (FLASH and SRAM) and the peripheral modules via the internal system bus.
The system bus provides a 16 bit address space and allows 8 and 16 bit data transfers.
The memory contains the program code and the data. Memory and registers are mapped to the global memory
map and can be accessed through all memory related operation provided by the CPUs instruction set. The memory
of the IC consists a FLASH cell up to 30Kx22 (60KByte) including 6 additional bits per word used as CRC for error
detection and error correction and a SRAM cell up to 1.5Kx18 (3KByte) including 2 bit parity per word.
The Interrupt Controller collects requests from all interrupt sources and provides an interrupt signal to the CPU.
Interrupt sources can be masked within the interrupt controller. Interrupts are generated by the modules and hold
until they are cleared within the module. See module description for clearing procedures.
The SPI can be configured either as a master or a slave. Transfer length is eight bit and can be extended by a multiple of eight bit. Data FIFOs are provided for transmit and receive tasks.
The SCI provides the standard NRZ (Non Return to Zero) mark/space data format where each frame contains one
start bit, eight data bits and one stop bit. Several features are implemented for special LIN support.
The timer module contains a 32 bit timer module as well as a watchdog timer. Additionally a second timer module
operating on wake up clock is implemented that remains active even in off mode, so it can be used for a periodical
wake up from off mode for applications that require a low current consumption.
8 IO port pins can either be configured as general purpose IO`s or can be configured as ports for the SPI or SCI module. Additionally two ports are reserved for the I²C slave interface.
The clock and reset generator module provides the system clock and the global reset signal. A power-on-reset,
brown out detect and a power watch are implemented. As external reset source a reset input will be considered.
The system clock is generated by an on-chip oscillators. A more detailed diagram of the clock/reset generation
block (CRG) is shown in the following sections.
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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Data Sheet
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QM-No.: 25DS0049E.02
E909.06
HALIOS® MULTI PURPOSE SENSOR FOR AUTOMOTIVE
PRODUCTION DATA - NOV 16, 2011
4.2 Supply Voltages
4.2.1 Block Diagram
VDDIO
Peripherie
VSS
VDDIO
RAM
VSS
Flash
GPIO
Interface
EL16 Core
VSSLEDx
CRG
Analog
VSSLEDC
LED1-4
LEDC
VSSLEDx
VSSLEDC
Figure 2: Block Diagram Supply Voltages
4.2.2 Functional Description
The devices has three separated power domains and needs two different levels of power supplies. The core power
domain is supplied by VDDC and the analog power domain by AVDD. Both needs the same voltage level. The third
supply domain is supplied by VDDIO and powers GPIOs. See also 2.2 Recommended Operating Conditions.
4.2.3 Power Up Sequence Considerations
During power-up the power-on-reset configures all pads as inputs consequently disabling the output drivers. The
IO supply is watched after power up if the core supply is in the specified range and causes a reset if it leaves the
allowed region. The core supply is watched via a brown out circuit.
The pads will remain input pads as long as the software does not reconfigure them.
According the following diagram it must be guaranteed that ADVV / DVVC is not switched on before VDDIO. NRST
can be switched on if the VDDIO and AVDD/DVVC are stabilized on its potential.
A >= 0ms
B > 5ms (recommended)
To avoid floating gates, A < 100µs is recommended.
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HALIOS® MULTI PURPOSE SENSOR FOR AUTOMOTIVE
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2.5V (AVDD / VDDC)
Figure 3: Brown-Out timing diagram
4.2.4 Power Down Sequence Considerations
During power down the chip will enter the reset state as soon as the core or IO supply leaves the specified region
bringing all pads into input configuration again.
4.3 Brown Out Detection
4.3.1 Timing Diagram
VDDC/AVDD
Reset
Brown-Out
Black-Out
VDDC/AVDD
VBOHL
VDDmin
VBOHYST
Undefined Behaviour
t
Figure 4: Brown-Out timing diagram
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HALIOS® MULTI PURPOSE SENSOR FOR AUTOMOTIVE
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4.3.2 Functional Description
The brown out detection of the chip will cause a reset whenever the core or IO power supply falls below the specified region. An over-voltage protection is not implemented. The circuit will not be operational when the core supply is below VDDmin. In these cases the power-on-reset will take care of proper reset generation.
4.4 Reset Generation
4.4.1 Reset Generation (RESGEN)
The IC is equipped with a reset input pin which can be used to reset the chip. Any low pulse longer than TDEBNRST
on the external reset line will be sensed and causes an IC reset.
The IC contains different dynamic and static reset sources. The static sources trigger the master reset as long as
the cause for the reset persists. The dynamic sources trigger the reset for a defined minimum reset time. After
that time has expired the system reset is released. In case the dynamic source is still signaling a reset the reset is
re-triggered.
Static reset sources:
- A power up sequence of the core voltage (power on reset)
- Brown out of the core voltage
Dynamic reset sources:
- Uncorrectable FLASH CRC error
- SRAM parity error
- CPU register parity error
- Watchdog timeout
- Uncorrectable trim register ECC error
TDEB_NRST
NRST_PADin
NRST_DEB
t
Filtered by Debouncer
Figure 5: Timing of the external reset signal
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HALIOS® MULTI PURPOSE SENSOR FOR AUTOMOTIVE
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4.4.2 Power-On-Reset
4.4.2.1 Timing Diagram
VDDC/AVDD
Vpor
VDDmin
End of Power-On-Reset
t
Brown Out
Is not detected
Figure 6: Power-On-Reset timing digram
4.4.2.2 Functional Description
The power on reset is designed to cause a reset during the power on cycle of the chip. The reset will be deactivated
when the supply crosses VPOR.
After the power up sequence the power on reset block will only cause a new reset if the power supply voltage drops
below VDDmin and the rise and fall times of the supply are below the specified values.
4.5 System Failsafe Features
failsafe feature
asserts interrupt
FLASH CRC (bit error corrected)
asserts reset
X
FLASH CRC (uncorrectable bit error)
X
Empty (erased) FLASH word read detection
X
FLASH write detection
X
RAM byte parity
X
Uninitialized RAM word / byte read detection
X
CPU register parity
X
CPU undefined opcode detection
X
CPU misaligned word access detection
X
Opcode execution memory protection
X
Stack overflow detection
X
Invalid module register access detection
X
Watchdog time-out
X
Watchdog window protection
X
Brownout detection (supply voltage monitoring)
X
System clock monitoring
X
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HALIOS® MULTI PURPOSE SENSOR FOR AUTOMOTIVE
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4.6 HALIOS® Interface
4.6.1 HALIOS® Block Diagram
Analog
KA
AMP_KA
clk
rst
+
Switch
AMP_AN
AN
Digital
+
2
demod.
HP
clocks
1
+
1
DAC
LED1
LED2
DAC
LED3
MUX
Current
Control
LED4
DAC
DAC
DAC
LEDC
DAC
10
10 bit
counter
offset
adr
5
offset
din
5
range
5
range
dout
Register
5
offset ledc
5
Figure 7: HALIOS® Block Diagram
4.6.2 HALIOS® Features
In order to be able to realize optical as well as capacitive sensors the input amplifier can be changed in its characteristic between transimpedance amplifier and charge amplifier. This is achieved by changing the feedback impedance. To have a good immunity to noise the receiving path consists of a symmetrical differential input.
The HALIOS® IC contains a configurable current driver interface. In the case of an optical sensor it is possible to
drive up to four sending LEDs and one compensation LED. If a capacitive sensor should be realized, the current is
converted into a voltage by connecting pullup resistances at the outputs LEDx. The HALIOS® measurement loop is
closed by a 10 bit DAC which regulates the output current for the sending/compensation LED. The DAC is controlled by a counter that sets the DAC dependent on the received signal amplitudes up or down.
To follow fast signal changes the counter can be increased or decreased by 1, 2, 4 or 8 steps, this is called the step
size that is set due to the number of up/down-counts in the same direction. To start a new measurement the interface is configured with the counter-value and the step size (generally the values from the last measurement),
the LED configuration and the current configuration for the LED driver. The measurement regulates the DAC and
performs 25 counter steps to follow the actual reflection conditions of the sensor. After one measurement the interface returns the counter-value, the mean-value (it is calculated from the last 16 counter-steps during one measurement) and the stepsize from the last integrator cycle.
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HALIOS® MULTI PURPOSE SENSOR FOR AUTOMOTIVE
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After the automated measurement cycle is finished an interrupt appears if the interrupt is enabled. The interrupt
is used to wake the system from standby mode.
The HALIOS® clock is adjustable in 5 frequencies (FSYS=8 MHz):
- 167 kHz
- 125 kHz (default)
- 100 kHz
- 83 kHz
- 71 kHz
4.6.3 HALIOS® Module Registers
Register Name
Address
Start Value Counter
Description
0x00
Measurement Configuration
0x02
Measurement Configuration HALIOS® Clock
0x04
Current Configuration Phase A
0x06
Current Configuration Phase B
0x08
Current Configuration Compensator Offset
0x0A
Measurement Result: Counter Value
0x0C
Measurement Result: Mean Value
0x0E
Interrupt
0x10
Preamplifier Configuration
0x12
Send Frequency Select
0x14
Register Start Value Counter (0x00)
Content
MSB
15:
12
LSB
Reset value
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal access
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
External access
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
15:12 : STZ: Startup step size for one step of the integrator (range: "0001", "0010", "0100" or
"1000")
10 : 0 - normal settling time of optical gyrator
1 - decrease settling time of optical gyrator
9:0 : STRTCNT: Startup counter - value from the integrator (range: 0 ... 1023)
reset value: 0x0000
Table 1: Start Value Counter
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HALIOS® MULTI PURPOSE SENSOR FOR AUTOMOTIVE
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Register Measurement Configuration (0x02)
MSB
LSB
Content
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal access
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
External access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
15 : HALMEAS: Starts a new measurement phase, switching from '0' to '1' starts
measurement. After measurement the bit resets itself.
14 : ACCON: En/disables the acceleration of the integrator
('0' = disabled, '1' = enabled)
13 : Deactivation of AN input to reduce current consumption in the case that only the KA
input is used
('0' = active, '1' = deactivated)
12 : AON: Control of analogue part ('0' = off, '1' = on)
11 : FIXB: Sets the LEDs activated in phase B to fixed sending current ('0' = variable, '1' = fixed)
10 : FIXA: Sets the LEDs activated in phase A to fixed sending current
('0' = variable, '1' = fixed)
9 : LED C A: Decides if LED is active for the measurement ('0' = off, '1' = on)
Note: Bits 9 downto 0 will be reset after measurement
8 : LED C B: Decides if LED is active for the measurement ('0' = off, '1' = on)
7 : LED 4 A: Decides if LED is active for the measurement ('0' = off, '1' = on)
Note: not available in version 1 and version 2
6 : LED 4 B: Decides if LED is active for the measurement ('0' = off, '1' = on)
Note: not available in version 1 and version 2
5 : LED 3 A: Decides if LED is active for the measurement ('0' = off, '1' = on)
Note: not available in version 1 and version 2
4 : LED 3 B: Decides if LED is active for the measurement ('0' = off, '1' = on)
Note: not available in version 1 and version 2
3 : LED 2 A: Decides if LED is active for the measurement ('0' = off, '1' = on)
2 : LED 2 B: Decides if LED is active for the measurement ('0' = off, '1' = on)
1 : LED 1 A: Decides if LED is active for the measurement ('0' = off, '1' = on)
0 : LED 1 B: Decides if LED is active for the measurement ('0' = off, '1' = on)
reset value: 0x0000
Table 2: Measurement Configuration
Register Measurement Configuration HALIOS® Clock (0x04)
MSB
LSB
Content
4
3
2
1
0
0
0
0
0
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
Internal access
R
R
R
R
R
R
R
R
R
R
R
R/W R/W R/W R/W R/W
External access
R
R
R
R
R
R
R
R
R
R
R
R/W R/W R/W R/W R/W
Bit Description
4 : Polarity of LEDC Modulator clock ('0' = normal, '1' = inverted)
3 : Polarity of LED4 Modulator clock ('0' = normal, '1' = inverted)
Note: not available in version 1 and version 2
2 : Polarity of LED3 Modulator clock ('0' = normal, '1' = inverted)
Note: not available in version 1 and version 2
1 : Polarity of LED2 Modulator clock ('0' = normal, '1' = inverted)
0 : Polarity of LED1 Modulator clock ('0' = normal, '1' = inverted)
Table 3: Measurement Configuration HALIOS® Clock
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HALIOS® MULTI PURPOSE SENSOR FOR AUTOMOTIVE
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Register Current Configuration Phase A (0x06)
MSB
LSB
Content
9:5
0
0
0
0
3
2
1
0
0
0
0
0
0
Reset value
0
0
0
0
0
0
Internal access
R
R
R
R
R
R
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
External access
R
R
R
R
R
R
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
0
4:0
9:5 : OFF: Offset phase A
4:0 : RNG: Range phase A
Table 4: Current Configuration Phase A
Register Current Configuration Phase B (0x08)
MSB
LSB
Content
9:5
0
0
0
0
3
2
1
0
0
0
0
0
0
Reset value
0
0
0
0
0
0
Internal access
R
R
R
R
R
R
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
External access
R
R
R
R
R
R
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
0
4:0
9:5 : OFF: OFFSET phase B
4:0 : RNG: RANGE phase B
Table 5: Current Configuration Phase B
Register Current Configuration Compensator Offset (0x0A))
MSB
LSB
Content
11:8
Reset value
0
0
0
0
Internal access
R
R
R
R
R/W R/W R/W R/W
R
R/W R/W R/W R/W R/W R/W R/W
External access
R
R
R
R
R/W R/W R/W R/W
R
R/W R/W R/W R/W R/W R/W R/W
Bit Description
0
6:0
0
0
0
0
0
0
0
0
0
0
0
11:8 : DC_OFFSET current LEDC (4 Bit)
6:0 : OFFSET compensation LEDC
Table 6: Current Configuration Compensator Offset
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Register Measurement Result: Counter Value (0x0C)
MSB
15:
12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
External access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Content
Reset value
Bit Description
LSB
9:0
15:12 : STZ: Stepsize integrator
9:0 : COUNT: Integrator value from the measurement
Table 7: Measurement Result: Counter Value
Register Measurement Result: Mean Value (0x0E)
MSB
15:
12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
External access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Content
Reset value
Bit Description
LSB
11:0
15:12 : STZ: Stepsize integrator
11:0 : MEAN: Mean value from the measurement
Table 8: Measurement Result: Mean Value
Register Interrupt (0x10)
MSB
LSB
Content
1
0
Reset value
0
0
0
0
0
0
0
0
Internal access
R
R
R
R
R
R
R/W
R/W
External access
R
R
R
R
R
R
R/W
R/W
Bit Description
1 : CLHALI: Clear HALIOS® interrupt
0 - no influence
1 - clear HALIOS® interrupt
0 : HALIE: HALIOS® interrupt enable:
0 - interrupt disabled
1 - interrupt enabled
Table 9: Interrupt
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Register Preamplifier Configuration (0x12)
MSB
LSB
Content
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal access
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
External access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
15 : Enlarge Phasemargin PM for 1. stage amplifiers in capacitive mode
('0' = PM low and fast, '1' = PM high and slow)
14 : Bias current of preamplifier medium IB = ('0' = 30uA, '1' = 10uA) if Bit13='0'
13 : Bias current of preamplifier low IB = ('0' = 10uA, '1' = 2uA) if Bit14='1'
12 : Deactivate Gyrator at AN input: ('0' = on, '1' = off)
11 : Deactivate Gyrator at KA input: ('0' = on, '1' = off)
10 : Select between optical and capacitive gyrator at AN input: ('0' = optical, '1' = capacitive)
Note: not available in version 1 and version 3
9 : Select between optical and capacitive gyrator at KA input: ('0' = optical, '1' = capacitive)
Note: not available in version 1 and version 3
8:7 : Select amplification of 3. Stage AMP
"00" - 16
"01" - 4
"10" - 64
"11" – 16
6 : Switch AN Input off: ('0' = on, '1' = off)
5 : Switch KA Input off: ('0' = on, '1' = off)
4 : Polarity of the Switch between 1. stage output and summation amplifier: Polarity
inverted ('0' = normal, '1' = inverted)
3 : 1. stage amplifier AN input: CF Feedback capacitor deactivation ('0' = on, '1' = off)
2 : 1. stage amplifier KA input: CF Feedback capacitor deactivation ('0' = on, '1' = off)
1 : 1. stage amplifier AN input: RF Feedback resistor deactivation ('0' = on, '1' = off)
0 : 1. stage amplifier KA input: RF Feedback resistor deactivation ('0' = on, '1' = off)
reset value: 0x0000
Table 10: Preamplifier Configuration
Register Send Frequency Select (0x14)
MSB
LSB
Content
2:0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal access
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W R/W R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W R/W R/W
External access
Bit Description
1
0
0
2:0 : HALIOS® send frequency select
SendFreq (sfreq)
frequency = FSYS/(sfreq*16)
sfreq range 3..7
reset value: 0x0004
Table 11: Send Frequency Select
5 Microcontroller EL16H6
The EL16H6 is based on a 16-bit RISC CPU core. It includes a 30Kx22 (60 Kbyte) FLASH Memory with 6 bit CRC
checksum per 16 bit word and a 1.5Kx18 (3 Kbyte) SRAM with byte write support. It provides up to 16 general
purpose I/O's, one synchronous Serial Peripheral Interface (SPI) and one asynchronous Serial Interface (SCI). SPI and
SCI can be mapped to the IO port or to the D2D port. Furthermore a 32 bit timer and a watchdog are included. As
the system clock source either an on-chip oscillator or a crystal oscillator can be selected.
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clock
CPU core
16 Bit
test
NRST
RAM
JTAG
reset
TM0
TM1
VP
FLASH
DATA
watchdog
timer
SPI/SCI
IRQ
Control
GPIO
multiply
I2C
GPIO
SDA
SCL
Figure 8: µC Block Diagram
5.1 Feature List
ÿ
ÿ
ÿ
ÿ
ÿ
ÿ
ÿ
ÿ
ÿ
ÿ
RISC architecture with 27 instructions and 7 addressing modes
16 registers including PC, SP and status register
16 bit address range
Word and byte addressing
Interrupt support
Standby and stop mode support
Automatic bus ready handling
Debugging support (JTAG interface)
3 hardware breakpoint triggers
Failsafe architecture
5.2 Debugging
To access the debug structures of the EL16 CPU a 4-wire standard JTAG interface is used. The JTAG interface can
be accessed via GPIO pins when the TEST_MODE pin is set to one. TEST_MODE pin set to zero resets all test and
debug structures and the IC operates in normal mode.
The EL16 embedded breakpoint logic provides the following features:
ÿ
ÿ
ÿ
ÿ
ÿ
ÿ
ÿ
3 breakpoint triggers
Each trigger can match a separate address or data bus value
A trigger value compare mask can be defined
Trigger can match a greater, smaller, equal or non equal value
Trigger can be configured for read / write or instruction fetch / non instruction fetch bus cycles
Triggers can be combined (trigger dependency)
All breakpoints can be used for stepping and run-stop a program
5.3 CPU Registers
The EL16 contains 16 registers (R0 to R15) including Program Counter, Stack Pointer and Status Register.
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5.3.1 Program Counter (PC)
The 16-bit Program Counter (PC/R0) points to the next instruction to be executed. Each instruction uses an even
number of bytes (two, four, or six), and the PC is incremented accordingly. Instruction accesses in the 64-KB address
space are performed on word boundaries, and the PC is aligned to even addresses. The PC can be addressed with
all instructions and addressing modes.
5.3.2 Stack Pointer (SP)
The Stack Pointer (SP/R1) is used by the CPU to store the return addresses of subroutine calls and interrupts. It uses
a pre-decrement, post-increment scheme. In addition, the SP can be used by software with all instructions and addressing modes. The SP is initialized into RAM by the user, and is aligned to even addresses.
5.3.3 Status Register (SR)
The Status Register (SR/R2), used as a source or destination register, can be used in the register mode only addressed with word instructions. The remaining combinations of addressing modes are used to support the constant generator.
Register Name
Address
Status Register
SR/R2
Description
Register Status Register (SR/R2)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal access
External access
Bit Description
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit 8 : V
Bit 5 : CLK OFF
Bit 4 : CPU OFF
BIT3 : GIE
Bit2 : N
Bit1 : Z
BIT0 : C
Table 12: Send Frequency Select
V: Overflow bit
This bit is set when the result of an arithmetic operation overflows the signed-variable range.
CLKOFF: Stop flag
CPU clock gated
CPUOFF: Standby flag
CPU halted
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GIE: Global Interrupt Enable
N: Negative bit
This bit is set when the result of a byte or word operation is negative and cleared when the result is not negative.
Word operation: N is set to the value of bit 15 of the result Byte operation: N is set to the value of bit 7 of the result
Z: Zero bit
This bit is set when the result of a byte or word operation is 0 and cleared when the result is not 0.
C: Carry bit
This bit is set when the result of a byte or word operation
produced a carry and cleared when no carry occurred.
5.3.4 Constant Generation Registers CG1 and CG2
Six commonly-used constants are generated with the constant generator registers R2 and R3, without requiring
an additional 16-bit word of program code. The constants are selected with the source-register addressing modes
(As), as described in the table below:
Register Name
As
Value
Remarks
R2
00
-
register mode (access R2)
R2
01
(0)
used for absolute
address mode
R2
10
0x0004
constant +4
R2
11
0x0008
constant +8
R3
00
0x0000
constant 0
R3
01
0x0001
constant +1
R3
10
0x0002
constant +2
R3
11
0xFFFF
constant -1
The constant generator advantages are:
No special instructions required
No additional code word for the six constants
No code memory access required to retrieve the constant
The assembler uses the constant generator automatically if one of the six constants is used as an immediate
source operand. Registers R2 and R3, used in the constant mode, cannot be addressed explicitly; they act as sourceonly registers.
5.3.5 General-Purpose Register R4 - R15
The twelve registers, R4-R15, are general-purpose registers. All of these registers can be used as data registers or
address pointers and can be used with byte or word instructions.
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5.4 Addressing Modes
Seven addressing modes for the source operand and four addressing modes for the destination operand can address the complete address space with no exceptions. The bit numbers in the table below describe the contents of
the As (source) and Ad (destination) mode bits.
As/Ad
Addressing Mode
Syntax
Description
00/0
Register mode
Rn
01/1
Indexed mode
X(Rn)
(Rn + X) point to the operand. X is stored in the
next word.
01/1
Symbolic mode
ADDR
(Rn + X) point to the operand. X is stored in the
next word. Indexed mode X(PC) is used.
01/1
Absolute mode
&ADDR
(Rn + X) point to the operand. X is stored in the
next word. Indexed mode X(0) is used.
10/-
Indirect Register
mode
@Rn
Rn is used as a pointer to the
11/-
Indirect auto
increment
@Rn+
Rn is used as a pointer to the operand. Rn is
incremented afterwards by 1 for .B instructions
and by 2 for .W instructions
11/-
Immediate mode
#N
The word following the instruction contains the
immediate constant N. Indirect auto-increment
mode @PC+ is used.
Register contents are operand
5.5 EL16 Instruction Set
The complete EL16 instruction set consists of 27 instructions. There are three instruction formats:
ÿ Dual-operand
ÿ Single-operand
ÿ Jump
All dual-operand and single-operand instructions can be byte or word instructions by using .B or .W extensions.
Byte instructions are used to access byte data. Word instructions are used to access word data. If no explicit extension is used, the instruction is a word instruction.
The source and destination of an instruction are defined by the following fields:
Abbr.
Description
src
The source operand defined by As and S-reg
dst
The destination operand defined by Ad and D-reg
As
The addressing bits responsible for the addressing
mode used for the source (src)
S-reg
The working register used for the source (src)
Ad
The addressing bits responsible for the addressing
mode used for the destination (dst)
D-reg
The working register used for the destination (dst)
B/W
Byte or word operation: 0: word operation, 1: byte
operation
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The following tables shows coding of the 16 bit op-code:
15
14
13
12
11
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
9
8
7
6
5
4
3
2
1
0
Mnemonic
0
0
0
0
RRC
0
0
0
1
RRC.B
0
0
1
0
SWP.B
0
0
1
1
---
0
1
0
0
RRA
0
1
0
1
RRA.B
0
1
1
0
SXT
0
1
1
1
1
0
0
0
1
0
0
1
PUSH.B
1
0
1
0
CALL
1
0
1
1
---
1
1
0
0
RETI
1
1
0
1
---
1
1
1
0
---
1
1
1
1
---
--
Ad/As
---
D-Reg/S-Reg
PUSH
0
1
---
1
0
---
1
1
---
0
0
0
JNZ / JNE
0
0
1
JZ / JEQ
0
1
0
JNC / JLO
0
1
1
1
0
0
1
0
1
JGE
1
1
0
JL
1
1
1
1
JC / JHS
10-Bit PC Offset
JN
JMP
0
1
0
0
MOV
0
1
0
1
ADD
0
1
1
0
ADDC
0
1
1
1
SUBC
1
0
0
0
SUB
1
0
0
1
1
0
1
0
1
0
1
1
BIT
1
1
0
0
BIC
1
1
0
1
BIS
1
1
1
0
XOR
1
1
1
1
AND
S-Reg
Ad
B/
W
As
CMP
D-Reg
DADD
Figure 9: Coding of the 16 bit op-code
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The table below shows a list of all instructions::
Mnemonic
Parameters Description
ADC(.B)**
dst
ADD(.B)
src, dst
ADDC(.B)
src, dst
AND(.B)
src, dst
BIC(.B)
src, dst
BIS(.B)
src, dst
BIT(.B)
src, dst
BR
dst
CALL
dst
CLR (.B)**
dst
CLRC**
--CLRN**
--CLRZ**
--CMP (.B)
src, dst
DADC (.B)**
dst
DADD (.B)
src, dst
dst
DEC (.B)**
dst
DECD (.B)**
--DINT**
--EINT**
dst
INC (.B)
dst
INCD (.B)**
dst
INV (.B)**
label
JC / JHS
label
JZ / JEQ
label
JGE
label
JL
label
JMP
label
JN
label
JNC /JLO
label
JNZ / JNE
src, dst
MOV (.B)
--NOP
dst
POP (.B)**
src
PUSH (.B)
--RET**
--RETI
dst
RLA (.B)**
dst
RLC (.B)**
dst
RRA (.B)
dst
RRC (.B)
dst
SBC (.B)**
--SETC**
--SETN**
--SETZ**
src, dst
SUB (.B)
src, dst
SUBC (.B)**
dst
SWPB
dst
SXT
dst
TST (.B)**
XOR(.B)
src, dst
** emulated instruction
Add C to destination
Add source to destination
Add source to C and destination
AND source and destination
Clear bits in destination
Set bits in destination
Test bits in destination
Branch to destination
Call destination
Clear destination 0
Clear C 0
Clear N 0
Clear Z 0
Compare source and destination
Add C decimally to destination
Add source and C decimally to destination
Decrement destination
Double decrement destination
Disable interrupts 0
Enable interrupts 1
Increment destination
Double increment destination
Invert destination
Jump if C set / Jump if higher or same
Jump if Z set / Jump if equal
Jump if greater or equal
Jump if less
Jump
Jump if N set / Jump if negative
Jump if C not set / Jump if lower
Jump if Z not set / Jump if equal
Move source to destination
No operation
Pop item from stack to destination
Push source onto stack
Return from subroutine
Return from interrupt
Rotate left arithmetically
Rotate left through C
Rotate right arithmetically
Rotate right through C
Subtract not(C) from destination
Set C
Set N
Set Z
subtract source from destination
dst + C -> dst
src + dst -> dst
src + dst + C -> dst
src AND dst -> dst
NOT(src) AND dst -> dst
src OR dst -> dst
src AND dst
dst -> PC
SP-2 -> SP, PC+2 -> @SP, dst -> PC
0 -> dst
0 -> C
0 -> N
0 -> Z
dst - src
dst + C -> dst
src + dst + C -> dst
dst -1 -> dst
dst -2 -> dst
0 -> GIE
1 -> GIE
dst +1 -> dst
dst +2 -> dst
NOT(dst) -> dst
if (condition) PC + 2 * offset -> PC
if (condition) PC + 2 * offset -> PC
if (condition) PC + 2 * offset -> PC
if (condition) PC + 2 * offset -> PC
PC + 2 * offset -> PC
if (condition) PC + 2 * offset -> PC
if (condition) PC + 2 * offset -> PC
if (condition) PC + 2 * offset -> PC
src -> dst
[email protected]+ -> dst
SP -2 -> SP, src -> SP
@SP -> PC
@SP -> SR, @SP+ -> PC
dst * 2 -> dst
dst * 2 -> dst, C -> LSB(dst)
dst / 2 -> dst
dst / 2 -> dst, C -> MSB(dst)
dst + NOT(0) + C -> dst
1 -> C
1 -> N
1 -> Z
dst + NOT(src) + 1 -> dst
subtract source and not(C) from destination dst + NOT(src) + C -> dst
Swap bytes
--Extend sign
--Test destination
dst + NOT (0) + 1
Exclusive OR source and destination
src XOR dst -> dst
V
N
Z
C
*
*
*
0
0
*
0
0
*
*
*
*
*
*
*
*
0
0
*
*
*
0
0
*
*
*
*
*
*
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
*
*
*
*
*
*
*
*
*
*
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
*
*
*
*
*
*
*
*
*
*
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
*
*
*
1
*
Figure 10: Instruction Set of EL16
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5.5.1 EL16 Instruction Cycle Counts
command type
operation
cycles
cycles(dreg==PC)
MOV
DOUBLE
sreg -> dreg
sreg x dreg -> dreg
1
1
2
2
MOV
DOUBLE
sreg -> Y(dreg) -> dreg
sreg x Y(dreg) -> Ydreg
3
4
--
MOV
DOUBLE
@sreg -> dreg
@sreg x dreg -> dreg
2
2
3
3
MOV
DOUBLE
@sreg -> Y(dreg) -> dreg
@sreg x Y(dreg) -> Ydreg
4
5
--
MOV
DOUBLE
@sreg+ -> dreg
@sreg+ x dreg -> dreg
2
2
3
3
MOV
DOUBLE
@sreg+ -> Y(dreg) -> dreg
@sreg+ x Y(dreg) -> Ydreg
4
5
---
MOV
DOUBLE
Xsreg+ -> dreg
Xsreg+ x dreg -> dreg
3
3
4
4
MOV
DOUBLE
Xsreg+ -> Y(dreg) -> dreg
Xsreg+ x Y(dreg) -> Ydreg
5
6
---
SINGLE
SINGLE
SINGLE
SINGLE
dreg
@dreg
@dreg+
Y(dreg)
---------
2
-------
JUMP
RETI
IRCQ
-------
2
3
4
-------
PUSH
PUSH
PUSH
PUSH
reg
@reg
@reg+
X(reg)
3
4
4
5
---------
CALL
CALL
CALL
CALL
reg
@reg
@reg+
X(reg)
3
4
4
5
---------
Figure 11: EL16 Instruction Cycle Counts
SINGLE includes RRC, RRA, SWPB and SXT
DOUBLE includes all double operand instructions except MOV
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5.6 Memory Description
5.6.1 Memory Map
0xFFFF
0xE000
V4
V3
V2
V1
FLASH
0xC000
0x8000
0x1000
0x0E00
DESIGN IDENT
MEMORY PROTECTION
ANALOG CONTROL
FLASH CONTROL
I²C
SRAM
0x0C00
IRQ CONTROL
MULTIPLIER
reserved
TIMER 1
TIMER 0 (WDOG)
0x0800
0x0400
0x0200
0x0000
0x0200
SPI
SCI
GPIO
HALIOS® MEASUREMENT
reserved
reserved
Modules
reserved
0x0000
Figure 12: Memory Map
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5.6.2 Base Address Table
Base address
Size
Module name
0x1000
0xF000
FLASH address
0x0400
0x0C00
SRAM address
0x0200
0x0200
reserved
0x01E0
0x0020
Design Ident Module
0x01C0
0x0020
Memory Protection Module
0x01A0
0x0020
Analog Control Module
0x0180
0x0020
FLASH Control Module
0x0160
0x0020
I²C Interface
0x0140
0x0020
Interrupt Control Module
0x0120
0x0020
Multiplier Module
0x0100
0x0020
reserved
0x00E0
0x0020
Timer 1
0x00C0
0x0020
Timer 0 (Window-Watchdog)
0x00A0
0x0020
SPI Module
0x0080
0x0020
LIN-SCI Module
0x0060
0x0020
GPIO Module
0x0040
0x0020
HALIOS® Interface
0x0020
0x0020
reserved
0x0000
0x0020
reserved
The differences in base addresses for the 3 additional devices of the EL16H6 versions are described in the tables
below.
Base address
Size
Module name
0x8000
0x8000
FLASH
0x1000
0x7000
reserved
0x0800
0x0800
SRAM
0x0400
0x0400
reserved
Base address
0xC000
Size
Module name
0x4000
FLASH
0x1000
0x3000
reserved
0x0C00
0x0400
SRAM
0x0400
0x0800
reserved
Base address
Size
Module name
0xE000
0x2000
FLASH
0x1000
0xD000
reserved
0x0E00
0x0200
SRAM
0x0400
0x0A00
reserved
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5.6.3 FLASH EL16H6
ÿ Main block size: up to 30K x 22 bit (60Kbyte) CRC protected
ÿ V4: 120 pages (60KByte)
ÿ V3: 64 pages (32KByte)
ÿ V2: 32 pages (16KByte)
ÿ V1: 16 pages (8KByte)
ÿ 256 words per page
ÿ 8 rows per page -> 32 words per row
ÿ Page erase support
ÿ See TSMC FLASH documentation for timing details
ÿ 20 ms page erase
ÿ 200 ms mass erase
ÿ About 30 µs programming time per word
FLASH CRC calculation
ÿ CRC polynomial: x6 + x4 + x3 + x2 + x1 + 1
ÿ Hamming distance: 4 (1 bit error correctable, 2 bit errors detectable)
ÿ Erased FLASH words will cause an uncorrectable bit error when read, which asserts a reset
5.6.4 SRAM EL16H6
ÿ
ÿ
ÿ
Size: up to 1.5K x 18Bit (3KByte)
ÿ V4: 3KByte
ÿ V3: 2KByte
ÿ V2: 1KByte
ÿ V1: 512Byte
Byte write enable support
Each byte is extended by a parity bit
5.7 Design Ident Module
The Design Ident Module of the EL16H6 contains following information:
ÿ Design Ident (split into 4x16 bit words), a unique number which identifies every single device
ÿ Design Version Code
All information are read only.
5.7.1 Design Ident Module Registers
Register Name
Address
Design Ident 0
0x00
Design Ident 1
0x02
Design Ident 2
0x04
Design Ident 3
0x06
Version
0x08
Description
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Register Design Ident 0 (0x00)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
External access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit Description
15:0 : Design Ident 0
Table 13: Send Frequency Select
Register Design Ident 1 (0x02)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
External access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit Description
15:0 : Design Ident 1
Table 14: Design Ident 1
Register Design Ident 2 (0x04)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
External access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit Description
15:0 : Design Ident 2
Table 15: Design Ident 2
Register Design Ident 3 (0x06)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
External access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit Description
15:0 : Design Ident 3
Table 16: Design Ident 3
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Register Version (0x08)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
External access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit Description
15:0 : Design Version Code
V1 - 0x0000
V2 - 0x0025
V3 - 0x001A
V4 - 0x003F
Table 17: Version
5.8 Memory Protection Module
ÿ Op-code execute area configuration (granularity: 1KByte, 64 areas)
ÿ Stack area configuration (granularity: 256Byte, 12 areas)
ÿ Invalid module register address handling
NOTE: In versions smaller then EL16H6V4 activation of non existent memory areas in Op-code Execute Enable Registers and Stack Enable Register have no effect.
5.8.1 Memory Protection Module Registers
Register Name
Op-code execute enable 0
Address
Description
0x00
Op-code execute enable 1
0x02
Op-code execute enable 2
0x04
Op-code execute enable 3
0x06
Failure address value
0x08
Stack enable
0x0A
Invalid address value
0x0C
Interrupt clear
0x0E
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Register op-code execute enable 0 (0x00)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
Internal access
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
External access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
15 : area 0x3000 to 0x3FFE
... : ...
1 : area 0x0400 to 0x07FE
0 : area 0x0000 to 0x03FE
Bit Description
enable
0 - execution of op-code denied
1 - execution of op-code allowed
area size: 1 KByte
reset value: 0xFFF0
Table 18: Op-code execute enable 0
Register op-code execute enable 1 (0x02)
Bit
Reset value
Internal access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
External access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
15 : area 0x7000 to 0x7FFE
... : ...
1 : area 0x4400 to 0x47FE
0 : area 0x4000 to 0x43FE
Bit Description
enable
0 - execution of op-code denied
1 - execution of op-code allowed
area size: 1 KByte
reset value: 0xFFFF
Table 19: Op-code execute enable 1
Register op-code execute enable 2 (0x04)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Internal access
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
External access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
15 : area 0xB000 to 0xBFFE
... : ...
1 : area 0x8400 to 0x87FE
0 : area 0x8000 to 0x83FE
Bit Description
enable
0 - execution of op-code denied
1 - execution of op-code allowed
area size: 1 KByte
reset value: 0xFFFF
Table 20: Op-code execute enable 2
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Register op-code execute enable 3 (0x06)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Internal access
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
External access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
15 : area 0xF000 to 0xFFFE
... : ...
1 : area 0xC400 to 0xC7FE
0 : area 0xC000 to 0xC3FE
Bit Description
enable
0 - execution of op-code denied
1 - execution of op-code allowed
area size: 1 KByte
reset value: 0xFFFF
Table 21: Op-code execute enable 3
Register failure address value (0x08)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
External access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit Description
15:0 : address of last detected failure (execute protection, stack protection, misaligned 16 bit
access, undefined op-code)
reset value: 0x0000
Table 22: Failure address value
Register stack enable (0x0A)
Bit
15
14
13
12
Reset value
0
0
0
0
Internal access
R
R
R
R
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
External access
R
R
R
R
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
1
1
1
11 : area 0x0F00 to 0x0FFE
to
1 : area 0x0500 to 0x05FE
0 : area 0x0400 to 0x04FE
reset value: 0x0FFF
Table 23: Stack enable
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Register invalid address value (0x0C))
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
External access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
6
5
4
3
2
1
0
W
W
W
W
W
W
W
W
W
W
Bit Description
15:0 : address of last invalid module register access
reset value: 0x0000
Table 24: Invalid address value
Register interrupt clear (0x0E)
Bit
15
14
13
12
11
10
9
8
7
Reset value
Internal access
External access
Bit Description
4 : undefined op-code IRQ clear (address of undefined op-code can be obtained by looking to
the return address stored in stack minus - 2)
0 - no influence
1 - clear interrupt
3 : misaligned 16 bit access IRQ clear
0 - no influence
1 - clear interrupt
2 : invalid address IRQ clear
0 - no influence
1 - clear interrupt
1 : stack protection IRQ clear
0 - no influence
1 - clear interrupt
0 : execute protection IRQ clear
0 - no influence
1 - clear interrupt
Table 25: Interrupt clear
5.9 Analog Control Module
ÿ Controls clock and reset generator (CRG)
5.9.1 Analog Control Module Registers
Register Name
Address
Wake-up timer config
0x00
Reset source status
0x0C
Reset source status clear
0x0E
Wake-up timer interrupt status
0x14
Wake-up timer interrupt clear
0x16
Description
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Register wake-up timer config (0x00)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W
R
R
R
R/W R/W R/W R/W R/W
External access R/W R/W R/W R/W R/W R/W R/W R/W
R
R
R
R/W R/W R/W R/W R/W
Internal access
Bit Description
15:8 : password
must be written as 0xA5, will always be read as 0x96
4 : enable timer
0 - timer off
1 - timer on
3:0 : timer value: timer period = 2 ms * [timer value + 1], with timer value 0...15
reset value: 0x0010
Table 26: Wake-up timer config
Register reset source status (0x0C)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
External access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
3
2
1
0
Bit Description
8 : Trap -> masked interrupt event occurred (interrupt number 0 and 1)
7 : RAM parity error
6 : FLASH uncorrectable bit error
5 : CPU register parity error
4 : watchdog reset
1 : external reset
0 : power on reset / supply observe / trim register ECC error
reset value: 0x0000
Table 27: Reset source status
Register reset source status clear (0x0E)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
Reset value
Internal access
W
External access
W
Bit Description
0 : clears all reset status bits
0 - no influence
1 - clears all reset status bits
Table 28: Reset source status clear
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Register wake-up timer interrupt status (0x14)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
External access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
3
2
1
0
Bit Description
8 : Trap -> masked interrupt event occurred (interrupt number 0 and 1)
0 : wake-up timer interrupt status
0 - no interrupt
1 - interrupt was asserted
reset value: 0x0000
Table 29: Wake-up timer interrupt status
Register wake-up timer interrupt clear (0x16)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
Reset value
Internal access
W
External access
W
Bit Description
0 : timer IRQ clear
0 - no influence
1 - clear interrupt
Table 30: Wake-up timer interrupt clear
5.10 FLASH Control Module
5.10.1 FLASH Control Module Registers
NOTE: In versions smaller then V4 activation of non existent memory areas in Area Protection Registers have no
effect.
Register Name
Address
Area protection (areas 0 - 7)
0x00
Area protection (areas 8 - 14)
0x02
Mode
0x04
Status
0x06
IRQ clear
0x08
Bit error corrected address
0x0C
Word config
0x0E
Frequency config
0x10
Description
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Register area protection (areas 0 - 7) (0x00)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
1
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
Internal access
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
External access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
15:8 : password
must be written as 0xA5
will always be read as 0x96
7:0 : writable
0 - area protected
1 - area writable
areas 0 - 7 are FLASH main block areas (each 4 Kbyte)
area 0: 0x1000 - 0x1FFF
area 7: 0x8000 - 0x8FFF
reset value: 0x9600
Table 31: Area protection (areas 0 - 7)
Register area protection (areas 8 - 14) (0x02)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
1
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
Internal access
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
External access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
15:8 : password
must be written as 0xA5
will always be read as 0x96
6:0 : writable
0 - area protected
1 - area writable
areas 8 - 14 are FLASH main block areas (each 4 Kbyte)
area 8: 0x9000 - 0x9FFF
area 14: 0xF000 - 0xFFFF
reset value: 0x9600
Table 32: Area protection (areas 8 - 14)
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Register mode (0x04)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
1
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
Internal access
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
External access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
15:8 : password
must be written as 0xA5
will always be read as 0x96
7:0 : mode
0x01 - main block read
0x04 - main block program
0x10 - erase main block page
0x40 - mass erase main block
. : every over written mode value results in "main block read" mode
. : program/erase modes: write access to appropriate flash address starts program / erase cycle (see busy flag of status register, consider word config and row programming incomplete
flag in program mode)
-> Program/Erase Mode FSM
reset value: 0x9600
Table 33: Mode
Register status (0x06)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
Internal access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
External access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit Description
3 : bit error corrected
bit error detected and corrected
this bit is cleared by bit error corrected IRQ clear
2 : write error
unexpected FLASH write access
this bit is cleared by write error IRQ clear
1 : row programming incomplete
current number of programmed row words != word config (see below)
0 : busy
0 - ready
1 - busy (program or erase is still in progress)
reset value: 0x0002
Table 34: Status
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Register IRQ clear (0x08)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Internal access
W
W
External access
W
W
Reset value
Bit Description
1 : bit error detected IRQ clear
0 - no influence
1 - clear interrupt
0 : write error IRQ clear
0 - no influence
1 - clear interrupt
Note: A write error interrupt handler which is asserted on a bad write access during FLASH
erase or program should be located in RAM because FLASH content may not be readable during these operations.
Table 35: IRQ clear
Register bit error corrected address (0x0C)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
External access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit Description
15:0 : address of last correctable flash bit error
reset value: 0x0000
Table 36: Bit error corrected address
Register word config (0x0E)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
1
0
0
1
0
1
1
0
0
0
0
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W
R
R
R
R/W R/W R/W R/W R/W
External access R/W R/W R/W R/W R/W R/W R/W R/W
R
R
R
R/W R/W R/W R/W R/W
Internal access
Bit Description
15:8 : password
must be written as 0xA5
will always be read as 0x96
4:0 : number of words to program within row
0: 1 word
1: 2 words
...
31: 32 words (default, a complete row)
reset value: 0x961F
Table 37: Word config
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Register frequency config (0x10)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
1
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W
R
R
R
R
R
R
R/W R/W
External access R/W R/W R/W R/W R/W R/W R/W R/W
R
R
R
R
R
R
R/W R/W
Internal access
Bit Description
15:8 : password
must be written as 0xA5
will always be read as 0x96
1:0 : system frequency config to get a correct erase and program timing
0: system frequency is 8 MHz (default)
1: system frequency is 16 MHz
2: system frequency is 24 MHz
3: system frequency is 32 MHz
reset value: 0x9600
Table 38: Frequency config
5.11 I²C Interface
5.11.1 I²C Block Diagram
SCL
SCLIN
receive
SCLOUT
8
receive fifo
4
3
2
1
receive data
high water level
high water interrupt
SDA
SDAIN
SDAOUT
STOP
detection
range
write byte
high water range
clear receive fifo
START
detection
slave address
Control
set/clear wake-up enable
wake-up
read byte
Bit
count
send
8
4
3
2
1
read fifo
send data
low water level
low water interrupt
range
low water range
clear send fifo
Figure 13: I²C Block Diagram
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5.11.2 I²C Function
The I²C slave interface operates in 7 bit addressing mode with a maximum frequency of 400 kHz (fast mode). To
synchronize the IC to different operation voltages of the I²C bus the interface has a separate supply voltage input
at pin VDDIO which is responsible for all interface pins. For more details of the addressing modes please refer to
the "I²C - BUS SPECIFICATION VERSION 2.1" from Philips.
5.11.3 I²C Bus Timing Diagram
SDA
tBUF
tr
SCL
tHD:STA tLOW
tHIGH
tSU:DAT
tHD:DAT
tSU:STA
tf
tSP
tSU:STO
Figure 14: I²C Bus Timing Diagram
5.11.4 I²C Module Registers
Register Name
Address
Receive Data FIFO Register
0x00
Send Data FIFO Register
0x02
Control Register
0x04
Status Register
0x06
Description
Register Receive Data FIFO Register (0x00)
MSB
Content
LSB
7:0
Reset value
0
0
Internal access
R
R
R
R
R
External access
R
R
R
R
R
Bit Description
0
0
0
0
0
0
R
R
R
R
R
R
7:0 : receive data
(see Data FIFO Registers for details)
Table 39: Receive Data FIFO Register
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Register Send Data FIFO Register (0x02)
MSB
Content
LSB
7:0
Reset value
0
0
0
0
0
0
0
0
Internal access
W
W
W
W
W
W
W
W
External access
W
W
W
W
W
W
W
W
Bit Description
7:0 : send data
(see Data FIFO Registers for details)
Table 40: Send Data FIFO Register
Register Control Register (0x04)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Internal access
R
R
R/W R/W R/W R/W R/W R/W
R
R/W R/W R/W
R
R/W R/W R/W
External access
R
R
R/W R/W R/W R/W R/W R/W
R
R/W R/W R/W
R
R/W R/W R/W
Bit Description
13 : Clear contents of send FIFO registers
0 - read
1 - write
12 : Clear contents of receive FIFO registers
0 - read
1 - write
11 : Clear wake-up mode enable bit (see description below)
0 - read
1 - write
10 : Set wake-up mode enable bit (see description below)
0 - read
1 - write
9:8 : Slave address
"00" - $58 (reset value)
"01" - $59
"10" - $5A
"11" - $5B
6:4 : High water range for receive FIFO (range 0....4)
2:0 : Low water range for send FIFO (range 0....4)
Table 41: Control Register
Register Status Register (0x06)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Internal access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
External access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit Description
8 : Wake-up mode enable bit
0 - wake-up mode disabled
1 - wake-up mode enabled
6:4 : Fill level of receive FIFO
2:0 : Fill level of send FIFO
Table 42: Status Register
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5.11.5 Data FIFO Registers
Receive Data FIFO Registers:
The data received from the master is stored in the receive FIFO registers and has a depth of 4. The current fill
level can be read in the status register. If the FIFO is completely filled up and another byte should be received the
interface will force the master into a wait state until the application software reads one byte from the FIFO.
Send Data FIFO Registers:
The master reads data that is stored in the send FIFO registers. This FIFO buffer has a depth of 4 registers. The
current fill level can be read in the status register. If the FIFO is empty and a byte is requested by the master the
interface will force the master into a wait state until the application software writes one byte to the FIFO.
5.11.6 Interrupt Handling
I²C receive command (see List Of All Interrupts)
Command word pending in receive FIFO, this means the next byte read from the receive FIFO is the first received
byte after the slave has been addressed. Depending on the application software this byte could be interpreted as
a command. The interrupt flag is set back by reading a byte from the receive FIFO. The master will force the interface into a wait state until the application software reads one byte from the FIFO.
I²C send request (see List Of All Interrupts)
This flag signalizes that the master is requesting a byte but the send FIFO is empty. The interrupt flag is set back
by writing a byte to the send FIFO. The master will force the interface into a wait state until the application software writes one byte to the FIFO.
I²C send FIFO low water (see List Of All Interrupts)
In case the low water mark (defined in control register) is reached or is exceeded the send FIFO low water flag becomes active. The flag is set back by filling to the send FIFO.
I²C receive FIFO high water (see List Of All Interrupts)
If the high water mark (defined in control register) is reached or is exceeded the receive FIFO high water flag becomes active. The flag is set back by reading from the receive FIFO..
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5.11.7 I²C Wake-up Detection
The I²C interface can be used to wake up the IC from any system state. In system state "off" the interface has to
be configured to wake the CPU Therefore the 'wake-up mode enable bit' has to be set (defined in control register)
before setting the IC to "off-mode".
It is only possible to set the 'wake-up mode enable bit' if the I²C Master has closed the communication on the
bus, so the application software has to poll the bit 'wake-up mode enable' (defined in status register) after it was
set to make sure the bus is in idle state and the IC can be set to "off-mode".
After a new addressing of the slave on the bus the system will wake up from "off-mode" and the "I²C wake-up
event" interrupt is active as long as the 'wake-up mode enable bit' is set back to zero (defined in control register).
While the wake-up process the interface will force the Master into a wait state by holding the SCL line low. The
application software has to clear the 'wake-up mode enable bit' (defined in control register) to release the SCL
line in order to continue the communication.
5.12 Interrupt Control Module
5.12.1 Interrupt Control Module Structure
ÿ
ÿ
ÿ
ÿ
ÿ
ÿ
ÿ
Interrupt pending bit flip-flops (request hold elements) are located inside asserting modules
Interrupt vector support for more simple and faster interrupt entry
Fast vector based interrupt enable / disable
Nested interrupt support
FLASH based main interrupt vector
Main interrupt enable MIE for easy cli() and sei() implementation
N is the number of interrupt vectors
N
Module
and GPIO
Interrupt
Sources
N
AND
N
N
N
Interrupt
Status
Interrupt
Mask
Masked
Interrupt
Status
OR
MIE
1
Interrupt
to CPU
Vector
Logic
Interrupt
Vector
Figure 15: Interrupt control circuit
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5.12.2 List Of All Interrupts
Vector Number
Interrupt Source
Priority
0
undefined op-code
highest
1
misaligned word access
2
op-code execute protection error
3
stack protection error
4
invalid module register address access
5
FLASH bit error corrected
6
FLASH write error
7
HALIOS® measurement ready
8
timer0 window error (watchdog)
9
timer1 event
10
I2C receive command
11
I2C send request
12
I2C send FIFO low water
13
I2C receive FIFO high water
14
SPI timeout
15
SPI FIFO error
16
SPI receive high water
17
SPI send low water
18
SCI break received
19
SCI measurement completed
20
SCI receive full
21
SCI transmit empty
22
GPIO rising
23
GPIO falling
24
I2C wake-up event
25
wake-up timer wake-up event
lowest
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5.12.3 Interrupt Control Module Registers
Register Name
Address
Interrupt mask
0x00
Interrupt status
0x04
Masked interrupt status
0x08
Interrupt vector number
0x10
Maximum interrupt level
0x14
Main interrupt enable
0x16
Interrupt enable
0x18
Interrupt disable
0x1A
Description
Register interrupt mask (0x00)
Bit
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
Reset value
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R R R R R R R R R R R R R R R R R
Internal access / / / / / / / / / / / / / / / / /
WWWWWWWWWWWWWWWWW
R R R R R R R R R R R R R R R R R
External access / / / / / / / / / / / / / / / / /
WWWWWWWWWWWWWWWWW
31:0 : mask (see List Of All Interrupts for details)
0 - disable
Bit Description 1 - enabled
0
R
/
W
R
/
W
0
R
/
W
R
/
W
0
R
/
W
R
/
W
0
R
/
W
R
/
W
0
R
/
W
R
/
W
0
R
/
W
R
/
W
0
R
/
W
R
/
W
0
R
/
W
R
/
W
0
R
/
W
R
/
W
0
R
/
W
R
/
W
0
R
/
W
R
/
W
0
R
/
W
R
/
W
0
R
/
W
R
/
W
0
R
/
W
R
/
W
0
R
/
W
R
/
W
reset value: 0x0000.0000
Table 43: Interrupt mask
Register interrupt status (0x04)
Bit
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
Reset value
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Internal access
R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
External access
R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
Bit Description
31:0 : status (see List Of All Interrupts for details)
0 - not active
1 - active
reset value: 0x0000.0000
Table 44: Interrupt status
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Register masked interrupt status (0x08)
Bit
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
Reset value
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Internal access
R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
External access
R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
Bit Description
31:0 : masked status (see List Of All Interrupts for details)
0 - not active
1 - active
reset value: 0x0000.0000
Table 45: Masked interrupt status
Register interrupt vector number (0x10)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Internal access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
External access
Bit Description
15:0 : number (see List Of All Interrupts for details)
vector number of pending interrupt with highest priority (smallest vector number)
when no interrupt is pending, vector will be 0xFFFF
reset value: 0x0000
Table 46: Interrupt vector number
Register maximum interrupt level (0x14)
Bit
15
14
13
12
11
10
9
8
7
6
Reset value
0
0
0
0
0
0
0
0
0
0
Internal access
R
R
R
R
R
R
R
R
R
R
R/W R/W R/W R/W R/W R/W
External access
R
R
R
R
R
R
R
R
R
R
R/W R/W R/W R/W R/W R/W
Bit Description
5
4
3
2
1
0
1
0
0
0
0
0
5:0 : level
needed for nested interrupt support
software writes current vector number to this register, so only interrupts with
higher priority (lower vector number) can nest.
reset value: 0x0020
Table 47: Maximum interrupt level
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Register main interrupt enable (0x16)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Internal access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W
External access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W
0 : MIE
Main interrupt enable flag which can be used for easy implementation of cli() and
sei() routines.
Bit Description
reset value: 0x0001
Note: cli() usually must check (save current enable status) and then clear interrupt enable
flag atomic (non interruptable). EL16 has no such operation, so GIE flag cannot be used. GIE
should only be used for interrupt nesting. When MIE is only used inside cli() and sei(), cli()
must not save current status, because MIE is always enabled on cli() entry.
Table 48: Main interrupt enable
Register interrupt enable (0x18)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Internal access
W
W
W
W
W
External access
W
W
W
W
W
Reset value
Bit Description
4:0 : set addressed enable bit in Interrupt Mask register to 1
vector number of interrupt to enable
Trap: when a disabled interrupt 0 or 1 occurred a system reset will be generated
Table 49: Interrupt enable
Register interrupt disable (0x1A)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Internal access
W
W
W
W
W
External access
W
W
W
W
W
Reset value
Bit Description
4:0 : set addressed enable bit in Interrupt Mask register to 0
vector number of interrupt to disable
Table 50: Interrupt disable
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5.13 Multiplier Module
The hardware multiplier is a peripheral and is not part of the EL16 CPU. This means, its activities do not interfere
with the CPU activities. The multiplier registers are peripheral registers that are loaded and read with CPU instructions.
ÿ
ÿ
ÿ
ÿ
ÿ
ÿ
ÿ
The hardware multiplier supports:
Unsigned multiply
Signed multiply
Unsigned multiply accumulate
Signed multiply accumulate
16 x 16 bits, 16 x 8 bits, 8 x 16 bits, 8 x 8 bits
CPU is halted until result is valid (1 clock cycle)
The hardware multiplier supports unsigned multiply, signed multiply, unsigned multiply accumulate, and signed
multiply accumulate operations. The type of operation is selected by the address the first operand is written to.
The hardware multiplier has two 16-bit operand registers, OP1 and OP2, and three result registers, SumLo, SumHi,
and SumExt. SumLo stores the low word of the result, SumHi stores the high word of the result, and SumExt stores
information about the result.
5.13.1 Multiplier Module Registers
Register Name
Address
MPY
0x10
MPYS
0x12
MAC
0x14
MACS
0x16
Operand 2
0x18
SumLo
0x1A
SumHi
0x1C
SumExt
0x1E
Description
Register MPY (0x10)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal access
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
External access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
15:0 : Operand 1
unsigned multiply
reset value: 0x000
Table 51: MPY
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Register MPYS (0x12)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal access
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
External access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
15:0 : Operand 1
signed multiply
reset value: 0x0000
Table 52: MPYS
Register MAC (0x14)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal access
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
External access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
15:0 : Operand 1
unsigned multiply accumulate
reset value: 0x0000
Table 53: MAC
Register MACS (0x16)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal access
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
External access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
15:0 : Operand 1
signed multiply accumulate
reset value: 0x0000
Table 54: MACS
Register Operand 2 (0x18)
Bit
Content
Reset value
Internal access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15:0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
External access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
15:0 : Operand 2
(write access starts multiplication)
reset value: 0x0000
Table 55: Operand 2
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Register SumLo (0x1A)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal access
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
External access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
15:0 : lower 16 bit of result
reset value: 0x0000
Table 56: SumLo
Register SumHi (0x1C)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal access
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
External access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
15:0 : In case of operation:
MPY: upper 16 bit of result
MPYS: The MSB is the sign of the result. The remaining bits are the upper 15-bits of the result. Two's complement notation is used for the result.
MAC: upper 16 bit of result
MACS: Upper 16-bits of the result. Two's complement notation is used for the result.
reset value: 0x0000
Table 57: SumHi
Register SumExt (0x1E)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
External access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit Description
15:0 : In case of operation:
MPY: always 0x0000
MPYS: contains the extended sign of the result
0x0000 if result was positive
0xFFFF if result was negative
MAC: contains the carry of the result
0x0000 no carry result
0x0001 result with carry
MPYS: contains the extended sign of the result
0x0000 if result was positive
0xFFFF if result was negative
reset value: 0x0000
Table 58: SumExt
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5.14 Timer 0 (Window-Watchdog) and Timer 1
ÿ
ÿ
ÿ
ÿ
ÿ
ÿ
ÿ
ÿ
Two 32 bit wide decrementing timers
Timer 0 is used as a window-watchdog, so it triggers a system reset instead of an interrupt when timer value = 0
Window-watchdog timer is disabled after reset and has to be armed by software
Window-watchdog cannot be disabled or changed when armed
16 times SCI Baud rate can be configured as timer1 clk base
NOTE: watchdog will be halted during FLASH erase / program
NOTE: watchdog and timer will be halted during debug CPU halt
Window-watchdog generates an interrupt when watchdog is reset outside specified window
(see diagram below)
timer_value
timer_counter
interrupt
when watchdog timer reset
2
(reset of timer_counter is not possible)
window_size
watchdog
reset
window
0
reset timer_counter to timer_value
when watchdog timer reset
system reset when timer_counter reaches 0
Figure 16: Window-Watchdog Timing
5.14.1 Timer 0 and Timer 1 Module Registers
Register Name
Address
Timer value
0x00
Timer counter
0x04
Timer control
0x08
Timer window config
0x0A
Timer interrupt clear
0x0C
SumLo
0x1A
SumHi
0x1C
SumExt
0x1E
Description
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Register timer value (0x00))
M
S
B
Content
L
S
B
31
:
0
Reset value
1 1 1 1 1 1 1 1 1
R R R R R R R R R
Internal access / / / / / / / / /
WWWWWWWWW
R R R R R R R R R
External access / / / / / / / / /
WWWWWWWWW
31:0 : timer start value
Bit Description
reset value: 0xFFFF.FFFF
1
R
/
W
R
/
W
1
R
/
W
R
/
W
1
R
/
W
R
/
W
1
R
/
W
R
/
W
1
R
/
W
R
/
W
1
R
/
W
R
/
W
1
R
/
W
R
/
W
1
R
/
W
R
/
W
1
R
/
W
R
/
W
1
R
/
W
R
/
W
1
R
/
W
R
/
W
1
R
/
W
R
/
W
1
R
/
W
R
/
W
1
R
/
W
R
/
W
1
R
/
W
R
/
W
1
R
/
W
R
/
W
1
R
/
W
R
/
W
1
R
/
W
R
/
W
1
R
/
W
R
/
W
1
R
/
W
R
/
W
1
R
/
W
R
/
W
1
R
/
W
R
/
W
1
R
/
W
R
/
W
Table 59: Timer value
Register timer counter (0x04)
M
S
B
L
S
B
Content
31
:
0
Reset value
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Internal access
R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
External access
R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
Bit Description
31:0 : timer start value
reset value: 0xFFFF.FFFF
Table 60: Timer counter
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Register timer control (0x08)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W
R
R
R
R
R/W
R
External access R/W R/W R/W R/W R/W R/W R/W R/W
R
R
R
R
R/W
R
0
0
(R) R/W
W
(R) R/W
W
Internal access
Bit Description
0
15:8 : password
must be written as 0xA5
will always be read as 0x96
3 : clock base selector (timer 1 only)
0 - MCLK
1 – MCLK/(16*baud rate)
synchronize timer to SPI clock
2 : timer reset
0 - no influence
1 - reset to start value
1 : loop
0 - run once and hold afterwards (clears "run enable")
1 - loop
0 : run enable
0 - timer stopped
1 - timer enabled
reset value: 0x0000
Table 61: Timer control
Register timer window config (0x0A)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W
R
R
R/W R/W R/W R/W R/W R/W
External access R/W R/W R/W R/W R/W R/W R/W R/W
R
R
R/W R/W R/W R/W R/W R/W
Internal access
15:8 : Timer Window Config (only applicable for window-watchdog)
Bit Description
password
must be written as 0xA5
will always be read as 0x96
5 : window enable
0 - no window (default)
1 - window active
4:0 : window size
reset window is defined as: timer value < (2^window size - 1)
reset value: 0x001F
Table 62: Timer window config
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Register timer interrupt clear (0x0C)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Internal access
W
W
External access
W
W
Reset value
1 : timer IRQ clear
0 - no influence
1 - clear interrupt
0 : window IRQ clear
0 - no influence
1 - clear interrupt
Bit Description
Table 63: Timer interrupt clear
5.15 SPI Module
ÿ
ÿ
ÿ
ÿ
ÿ
ÿ
ÿ
ÿ
ÿ
ÿ
Can be used as master or slave
The SPI Interface consists of the following 4 signals:
SCK: SPI clock (driven by master)
CSB: low active chip select (driven by master)
MISO: master in, slave out (data from slave to master)
MOSI: master out, slave in (data from master to slave)
Configurable phase, polarity and bit order
Byte and multi-byte transfer support
Slave mode SPI clock monitoring (timeout)
4 data word transmit and receive FIFOs
NOTE: Data will not be send as long as SPI interface is not routed to IO ports
T cs2
T cs1
T ck
C SB
T ck
T ck
T ck
T csh
SC K shift edge
SC K sample edge
T setup
MOSI
1st bit
T hold
2nd bit
last bit
T z1
MISO
Z
T z2
T so
1st bit
last bit
2nd bit
Z
Figure 17: SPI Bus Timing Diagram
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C SB
SSC PH
SSC PO
0
SC K
1st edge: shift
2nd edge: sample
off level: 0
0
1
SC K
1st edge: sample
2nd edge: shift
off level: 0
0
0
SC K
1st edge: shift
2nd edge: sample
off level: 1
1
1
SC K
1st edge: sample
2nd edge: shift
off level: 1
1
MOSI/MISO
first bit
last bit
sample
data
apply
data
sample
data
apply
data
sample
data
apply
data
apply
data
MOSI/MISO
sample
data
apply
data
Figure 18: SPI Mode Diagram
5.15.1 SPI Module Registers
Register Name
Address
Transmit data / receive data
0x00
Control
0x02
Baud config
0x04
Timeout config
0x06
Module reset
0x08
Status
0x0A
Error
0x0C
Interrupt clear
0x0E
Description
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Register transmit data / receive data (0x00)
Bit
15
14
13
12
11
10
9
Reset value
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
External access
0
0
0
0
0
0
0
0
0
(R) R/W R/W R/W R/W R/W R/W R/W R/W
R
R
R
R
R
R
R
W
(R) R/W R/W R/W R/W R/W R/W R/W R/W
R
R
R
R
R
R
R
W
8 : csb control (only for data transition and in master mode)
0 - byte mode
1 - keep csb active after related byte was transmitted
7:0 : transmit data / receive data
Bit Description
reset value: 0x0000
Internal access
The 'send low water' interrupt will be cleared by writing a byte to the transmit data register
(FIFO).
The 'receive high water' interrupt will be cleared by reading a byte from the receive data register (FIFO).
(see List Of All Interrupts)
Table 64: Transmit data / receive data
Register control (0x02)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
1
Internal access
R/W R/W R/W R/W
R
R/W R/W R/W
R
R
R
R
R/W R/W R/W R/W
External access R/W R/W R/W R/W
R
R/W R/W R/W
R
R
R
R
R/W R/W R/W R/W
Bit Description
14:12 : high water receive FIFO level
interrupt will be asserted when receive FIFO fill level increases to this value
default value: 2
10:8 : low water transmit FIFO level
interrupt will be asserted when transmit FIFO fill level decreases to this value
default value: 0
3 : slave
0 - master
1 - slave
2 : polarity: SSCPO, see SPI mode diagram
0 - clock off level 0
1 - clock off level 1
1 : phase: SSCPH, see SPI mode diagram
0 - 1st edge shift, 2nd edge sample
1 - 1st edge sample, 2nd edge shift
0 : order
0 - LSB first
1 - MSB first
Table 65: Control
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Register baud config (0x04)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Internal access
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
External access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
15:0 : baud divider
= (system clock frequency) / (2 * baud rate)
NOTE: Minimal value for baud divider is 4
reset value: 0x0004
Table 66: Baud config
Register timeout config (0x06))
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Internal access
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
External access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
15:0 : timeout value
maximum allowed count of system clock cycles between 2 SPI clock edges
reset value: 0xFFFF
Table 67: Timeout config
Register status (0x0A)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Internal access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
External access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit Description
15:0 : baud divider
= (system clock frequency) / (2 * baud rate)
NOTE: Minimal value for baud divider is 4
reset value: 0x0004
Table 68: Status
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Register error (0x0C))
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Internal access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
External access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
6
5
4
3
2
1
0
Internal access
W
W
External access
W
W
Bit Description
1 : transmit FIFO was empty (only in slave mode)
will be cleared on read
0 : receive FIFO was full (received data will be lost)
will be cleared on read
Table 69: Error
Register interrupt clear (0x0E)
Bit
15
14
13
12
11
10
9
8
7
Reset value
Bit Description
1 : clear error IRQ
0 : clear timeout IRQ
Table 70: Interrupt clear
5.16 LIN-SCI Module
ÿ
ÿ
ÿ
ÿ
Full duplex operation
8N1 data format, standard mark/space NRZ format
Extended baud rate selection options
Interrupt-driven operation with four flags: receiver full, transmitter empty, measurement finished,
break character received
Special LIN Support:
ÿ 13 Bit break generation
ÿ 11 Bit break detection threshold
ÿ A fractional-divide baud rate prescaler that allows fine adjustment of the baud rate
ÿ Measurement counter which has 16 bits and can be used as a mini-timer to measure break and bit times
(baud rate recovery).
ÿ Baud Measurement Results can directly be fed into the baud register to adjust the baud rate
(Baud self-synchronization with SYNC byte)
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Figure 19: SCI block diagram
5.16.1 LIN-SCI Module Registers
Register Name
Address
Sci baud rate
0x00
Sci control
0x02
Sci status
0x04
Sci data (in/out)
0x06
Sci measurement control
0x08
Sci measurement counter
0x0A
Description
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Register sci baud rate (0x00)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal access
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
External access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
15:5 : BD - SCI baud divisor select
Divisor:
0x000 --> 1 (bypass divider)
0x001 --> 2
0x002 --> 3
...
0x007 --> 8
...
4:0 : BDFA - SCI baud divisor fine adjust
These bits select the number of clocks inserted in each 32 output cycle frame to achieve
more timing resolution on the average baud frequency shown in the following table.
Bit Description
BDFA[00000] = 0/32 = 0
BDFA[00001] = 1/32 = 0.03125
BDFA[00010] = 2/32 = 0.0625
...
BDFA[10000] = 16/32 = 0.5
...
BDFA[11111] = 31/32 = 0.96875
reset value: 0x0000
The divider can be used to achieve divisor values between 1 and 2047.96875. The baud divisor fine adjust can be used to fine tune the baud rate in 1/32 steps of the divisor.
Use the following formula to calculate the SCI baud rate:
Baud Rate = clksys/(16*(BD+BDFA))
Note: The 16 bit baud divisor value represents the number of system clock cycles of two bit
lengths. The result of a baud measurement(see measurement counter below) can directly be
written to the baud rate register.
Table 71: Sci baud rate
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Register sci control (0x02)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal access
R
R
R
R
R
R
R
R
R/W R/W R/W R/W R/W R/W R/W R/W
External access
R
R
R
R
R
R
R
R
R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
7 : TIE - TxD interrupt enable (generates interrupt when TDRE is set)
6 : LIN - LIN Mode: LIN break transmit enable (13 bit break symbol instead of 10 bit),
LIN break receive detection enable (detects a 11 bit break symbol instead of 10 bit)
5 : RIE - RxD interrupt enable (generates interrupt when RDRF is set)
4 : BIE - break detection interrupt enable (generates interrupt when BRF is set)
3 : TE - transmitter enable
If software clears TE while a transmission is in progress (TC = 0), the frame in the transmit
shift register continues to shift out. To avoid accidentally cutting off the last frame in a message, always wait for TDRE to go high after the last frame before clearing TE
2 : RE - receiver enable
RE set to '0' suppresses start bit recognition, setting RE to '1' during an ongoing transfer can
cause erroneous data reception and interrupt generation (RDRF)
setting RE to '0' during an ongoing transfer can cause erroneous data reception and interrupt
generation (RDRF), received data should be ignored
1 : MFIE - measurement finish interrupt enable (generates interrupt when MF is set)
0 : SBK - send break bit
Toggling SBK sends one break character (10 logic 0s, respectively 13 logic 0s if LINT is set).
Toggling implies clearing the SBK bit before the break character has finished transmitting. As
long as SBK is set, the transmitter continues to send complete break characters (10 bits respectively 13 bit).
reset value: 0x0000
Table 72: Sci control
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Register sci status (0x04)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
External access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit Description
9 : AUTO_BAUD_TRIGGERED
set when new Baud value was copied automatically to baud config register after a
valid SNYC byte measurement (see also measurement control register ->
AUTO_BAUD)
cleared when reading the msb of the status word
8 : AUTO_MEAS_TRIGGERED
set when measurement was started automatically after reception of a valid break
(see also measurement control register -> AUTO_MEAS)
cleared when reading the msb of the status word
7 : TDRE - transmit data register empty
Clear TDRE by writing to sci data reg. Write will be ignored when transmit register
is not empty -> check if TDRE = 1 before writing to transmit register
6 : TC - transmit complete flag
TC is reset to '0' when a transmission is in progress
5 : RDRF - receive data register full flag
Clear RDRF by reading sci status with RDRF set and then reading sci data reg
NOTE: RDRF will be set:
a) in case of data reception: 1/8 nominal bit length after the recognized stop bit,
e.g. since the bits are sampled in the middle of a nominal bit length the flags and with it the
irq will be set after the estimated end of the active stop bit.
b) in case of break reception: see BRF description below
4 : BRF - break received flag (LIN-Mode dependent)
Clear BRF by reading sci status with BRF set and then reading sci data reg.
The BR flag will be set when the start bit is followed by 8 (respectively 9 when Lin Mode is
set) logic 0 data bits and a logic 0 where the stop bit should be.
When BRF is set also FE and RDRF will be set, the SCI data register will be cleared
Note: flag generation (incl BRF) will be suppressed when AUTO_MEAS is set
3 : OV - receiver overrun detected
Clear OV by reading sci status with OV set and then reading sci data reg.
OV will be set when a received data byte is not read before the data byte of the next frame
or a break character arrives. The second data byte will be disallowed
2 : MRUN - measurement running
1 : MF - measurement finish flag
Clear MF by read accessing the measurement counter
0 : FE - framing error flag
FE is set when the logic does not detect a logic 1 where the stop bit should be.
FE will be set and reset together with RDRF
reset value: 0x0000
Table 73: Sci status
Register sci data (in/out) (0x06)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Internal access
R
R
R
R
R
R
R
R
R/W R/W R/W R/W R/W R/W R/W R/W
R
R
R
R
R
R
R
R
R/W R/W R/W R/W R/W R/W R/W R/W
External access
Bit Description
7:0 : sci data register, write for transmitting byte, read received byte
reset value: 0x0000
Table 74: Sci data (in/out)
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Register sci measurement control (0x08)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
1
0
1
0
0
0
0
0
0
0
0
1
0
0
Internal access
R
R
R/W R/W R/W R/W R/W R/W
R
R
R
R
R/W R/W R/W R/W
External access
R
R
R/W R/W R/W R/W R/W R/W
R
R
R
R
R/W R/W R/W R/W
Bit Description
13:8 : DBC[6:1] - denounce filter threshold for baud rate measurement (MMODE=0)
DBC[0] is always set to logic 1.
DBC[6:0] form the upper threshold value for the denouncing filter.
Denounce filter is reset to 81 which results in minimum filter delay of
81x62,5ns=5,[email protected]
3 : AUTO_BAUD
automatically copy baud measurement result to baud config register after a valid baud
measurement (expecting SYNC Byte)
--> AUTO_BAUD_TRIGGERED will be set
NOTE: During baud measurement the receiver is disabled an therefore no data will be received, only the measurement logic is active which will generate a
measurement finish flag (configurable as interrupt)
2 : AUTO_MEAS
automatically start a baud rate measurement after reception of a valid break
--> AUTO_MEAS_TRIGGERED will be set
NOTE: AUTO_MEAS mode suppresses the flag specific flag generation (see sci_status -> BRF)
1 : MMODE measurement mode select
0 -> baud rate measurement, counter runs with system clock and measures time between 4
falling edges (8 bit length are measured), bouncer is enabled
Note: baud measurement expects a 0x55 data byte to measure, this is the SYNC byte in the
LIN protocol
1 -> break time measurement, counter runs with 16 x baud rate, measures time when RxD
line is zero
NOTE: only applicable together with MEN control bit
0 : MEN - measurement enable
Set to '1' to start a measurement
When measurement is finished, MEN bit will be cleared automatically
NOTE: When AUTO_MEAS bit is set MEN must not be used
NOTE: Writing a '0' to MEN resets the measurement logic and allows a clean restart
reset value: 0x2800
Table 75: Sci measurement control
Register sci measurement counter (0x0A)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
External access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit Description
15:0 : MEASUREMENT COUNTER
Counter is cleared by every start of a new measurement
When the measurement counter overflows the counter value is saturated to 0xFFFF and the
measurement will be stopped (MF flag set). The measurement should be
repeated with an adapted baud rate setting.
Note: In Baud measurement mode the result of the baud measurement (8 bit length) is divided by 4 and rounded (resulting 2 bit length value) the resulting 16 bit
can be fed into the baud divider register to adjust the baud rate.
reset value: 0x0000
Table 76: Sci measurement counter
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HALIOS® MULTI PURPOSE SENSOR FOR AUTOMOTIVE
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5.17 GPIO Module
ÿ Up to 8 GPIOs (see IO Port Multiplexer table)
ÿ Interrupt capable (configurable for positive and / or negative signal edge interrupt)
sync & irq
logic
input data
output data
direction
Figure 20: Principle io cell structure
5.17.1 GPIO Module Registers
Register Name
Address
Output data
0x00
Direction
0x02
Input data
0x04
Posedge interrupt enable
0x06
Posedge interrupt status
0x08
Posedge interrupt clear
0x0A
Negedge interrupt enable
0x0C
Negedge interrupt status
0x0E
Negedge interrupt clear
0x10
Port config
0x12
Description
Register output data (0x00)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal access
R
R
R
R
R
R
R
R
R/W R/W R/W R/W R/W R/W R/W R/W
External access
R
R
R
R
R
R
R
R
R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
7:0 : output data
reset value: 0x0000
Table 77: Output data
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HALIOS® MULTI PURPOSE SENSOR FOR AUTOMOTIVE
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Register direction (0x02)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Internal access
R
R
R
R
R
R
R
R
R/W R/W R/W R/W R/W R/W R/W R/W
External access
R
R
R
R
R
R
R
R
R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
7:0 : direction
0 - output, pull down disabled
1 - input, pull down enabled
reset value: 0x00FF
Table 78: Direction
Register input data (0x04)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
External access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit Description
7:0 : input data
reset value: 0x0000
Table 79: Input data
Register posedge interrupt enable (0x06)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal access
R
R
R
R
R
R
R
R
R/W R/W R/W R/W R/W R/W R/W R/W
External access
R
R
R
R
R
R
R
R
R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
7:0 : enable
0 - disabled
1 - a positive edge on related "input data" bit will set interrupt bit
reset value: 0x0000
Table 80: Posedge interrupt enable
Register posedge interrupt clear (0x0A)
7
6
5
4
3
2
1
0
Internal access
W
W
W
W
W
W
W
W
External access
W
W
W
W
W
W
W
W
Bit
15
14
13
12
11
10
9
8
Reset value
Bit Description
7:0 : clear
0 - no influence
1 - clears related interrupt bit
Table 81: Posedge interrupt clear
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HALIOS® MULTI PURPOSE SENSOR FOR AUTOMOTIVE
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Register negedge interrupt enable (0x0C)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal access
R
R
R
R
R
R
R
R
R/W R/W R/W R/W R/W R/W R/W R/W
External access
R
R
R
R
R
R
R
R
R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
7:0 : enable
0 - disabled
1 - a negative edge on related "input data" bit will set interrupt bit
reset value: 0x0000
Table 82: Negedge interrupt enable
Register negedge interrupt status (0x0E)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
External access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
10
9
8
7
6
5
4
3
2
1
0
Internal access
W
W
W
W
W
W
W
W
External access
W
W
W
W
W
W
W
W
Bit Description
7:0 : status
0 - no interrupt
1 - interrupt was asserted
reset value: 0x0000
Table 83: Negedge interrupt status
Register negedge interrupt clear (0x10)
Bit
15
14
13
12
11
Reset value
Bit Description
7:0 : clear
0 - no influence
1 - clears related interrupt bit
Table 84: Negedge interrupt clear
Register port config (0x12)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W R/W
External access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W R/W
Bit Description
1:0 : IO port config
for details see IO Port Multiplexer
reset value: 0x0000
Table 85: Port config
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HALIOS® MULTI PURPOSE SENSOR FOR AUTOMOTIVE
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5.17.2 IO Port Multiplexer
IO Port
JTAG Debug
TMODE=1
Normal Mode
cfg[1:0]=00
Normal Mode
cfg[1:0]=01
Normal Mode
cfg[1:0]=10
Normal Mode
cfg[1:0]=11
TMODE
1
0
0
0
0
IO0
GPIO00
GPIO00
GPIO00
GPIO00
GPIO00
IO1
GPIO01
GPIO01
GPIO01
GPIO01
GPIO01
IO2
GPIO02
GPIO02
TXD
GPIO02
TXD
IO3
GPIO03
GPIO03
RXD
GPIO03
RXD
IO4
TDO
GPIO04
GPIO04
SCK
SCK
IO5
TDI
GPIO05
GPIO05
MISO
MISO
IO6
TMS
GPIO06
GPIO06
MOSI
MOSI
IO7
TCK
GPIO07
GPIO07
CSB
CSB
6 Robustness
6.1 EMC
The contents of this chapter were not specified yet!
6.2 ESD
The ESD protection circuitry is measured according to AEC-Q100-002 with the following conditions:
Test Method (HBM):
VIN = 2000 V (according to device class H1C)
REXT = 1500 Ohm
CEXT = 100 pF
Test Method (CDM):
VIN = 500 V for all pins
VIN = 750 V for corner pins
6.3 Latch up Test
Test Method:
100 mA positive and negative pulses at 85 °C according to AEC-Q100-004.
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WARNING – Life Support Applications Policy
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