Command Mode SRAM HF88S05 Preliminary Product Specification Product Name KB Doc. No. HF88S05.doc Command Mode SRAM KB Product. No. HF88S05 – Table of Contents – 1. General Description _____________________________________________________2 2. Features ______________________________________________________________2 3. Pin Description_________________________________________________________3 4. Pad Diagram __________________________________________________________4 5. Pad Coordinates ________________________________________________________4 6. Function Block Diagram _________________________________________________5 7. Parallel Mode __________________________________________________________6 7.1. Parallel Write Command Mode __________________________________________6 7.2. Parallel Write Data Mode ______________________________________________7 7.3. Parallel Read Data Mode_______________________________________________7 7.4. Parallel Read Checksum Mode __________________________________________7 8. Serial Mode ___________________________________________________________8 8.1. Bi-directional Synchronous Serial Data Interface ___________________________8 8.2. Serial Write Command Mode____________________________________________9 8.3. Serial Write Data Mode ________________________________________________9 8.4. Serial Read Data Mode _______________________________________________10 8.5. Serial Read Checksum Mode___________________________________________10 9. Power consideration____________________________________________________ 11 10. Absolute Maximum Rating ____________________________________________ 11 11. AC Electrical Characteristics __________________________________________ 11 12. Electrical Characteristics______________________________________________12 13. Application Circuit___________________________________________________12 -1- 02/07/01 Command Mode SRAM HF88S05 1. General Description The HF88S05 is a command mode SRAM device. It features dual (parallel and serial) command access modes. Multiple device array can be accessed with only minimal additional device select pin. Simple Exclusive Or checksum provides error detection during data transfer between MCU and the device. The interface logic and protocol include setting up the starting address for data transfer, writing data into RAM, as well as read it back for verification, and error checking by Exclusive OR checksum. It can be used for Read/Write memory extension for all KB’s MCUs. Chip Select pins allows array of HF88S05 devices are used simultaneously for both parallel and serial transfer mode. In the serial mode, the HF88S05 is connected in daisy chain configuration to minimize the I/O pins required to use multi-chip array, while in parallel mode, the devices share most of the control pins and data bus except the chip select pins. 2. Features 9 9 9 9 9 9 Dual (parallel and serial) command access modes. Address automatically increment with each Read/Write data access. Exclusive or checksum error detection Multiple chip array is allowed with easy addressing logic Read access voltage range 2.7V ~ 5.5V Organization - Memory Cell Array: 64K x 8 9 Package – Dice form -2- 02/07/01 Command Mode SRAM HF88S05 3. Pin Description 1 2 3 4 5 6 7 8 9 P_SN VSS CS0N D_CN R_WN D0 D1 D2 D3 VDD CS1 SDO SDI SCLK D7 D6 D5 D4 18 17 16 15 14 13 12 11 10 HF88S05 Symbol P_Sn VSS CS0n D_Cn R_Wn D0 ~ D7 SCLK/ Strobe SDI SDO CS1 VDD Pin I/O Description No. I Input to select either parallel (when ‘1’) or serial (when ‘0’) interface is used for transferring data. I Negative power supply of the device I CS0n is active low chip select input pin. The device is selected when CS1 is high and CS0n is low simultaneously. Otherwise, it is deselected. I Input to select either the SRAM or Registers (TPP, TPH, TPL, Mode or Checksum) operations. I Input to select either a Read operation (when ‘1’) or a write operation (when ‘0’) is to be performed. I/O Bi-directional data bus for parallel transfer mode. I This pin is shared between parallel and serial modes. In serial mode, this pin is Serial Clock SCLK for transferring the data from/to SDI/SDO. In parallel mode, it is the strobe signal used to write the registers and SRAM as well as read the checksum and contents of SRAM. This pin is equipped with Schmidt type input structure to prevent the input from chattering due to slow rising clock source transition. I Serial Data Input for writing to either Registers or SRAM. O Serial Data Output for reading data from either Checksum Register or SRAM. I CS1 is active high chip select input. The device is selected when CS1 is high and CS0n is low simultaneously. Otherwise, it is deselected. I Positive power supply of the device -3- 02/07/01 Command Mode SRAM HF88S05 4. Pad Diagram 5. Pad Coordinates Pin number 1 2 3 4 5 6 7 8 9 10 11 Pin X Y Pin Pin name coordinate coordinate number name P_SN -1970.5 1260.4 12 D4 VSS -1970.5 960.41 13 D5 VSS -1970.5 707.54 14 D6 VSS -1970.5 394.22 15 D7 CS0N -1970.5 159.23 16 SCLK D_CN -1970.5 -177.15 17 SDI R_WN -1970.5 -465.52 18 SDO D0 -1970.5 -780.53 19 CS1 D1 -1725.02 -1088.97 20 VDD D2 -1521.22 -1088.97 21 VDD D3 -1152.68 -1088.97 22 VDD -4- X coordinate Y coordinate 1150.32 -1088.97 1375.93 -1088.97 1762.16 -1088.97 1964.53 -759.28 1964.53 -538.44 1964.53 -221.71 1964.53 -0.91 1964.53 347.7 1964.53 600.92 1964.53 831.74 1964.53 1114.36 02/07/01 Command Mode SRAM HF88S05 6. Function Block Diagram Several registers are used in the interface logic. The functions of the registers are described below and their initial values are as indicated in the following table. Register TPL TPH TPP Checksum Type W W W R DIN[7..0] TP[15..0] Description Address register 0 for A7 ~ A0 Address register 1 for A15 ~ A8 Address register 2 for A23 ~ A16 XOR checksum of data Initial Value “--------“ “--------“ “--------“ “--------“ 64Kx8 Static RAM ARRAY DOUT[7..0] +1 MUX MUX XOR S2P TPP TPH TPL CHKSUM D[7..0] P_Sn D_Cn R_Wn SDI SDO SCLK/Strobe CS0n CS1 MUX The Table Pointer register keeps the address of SRAM being written to or read from. It will automatically increment by one with each read/write access, but remains unchanged when writing command or reading checksum. -5- 02/07/01 Command Mode SRAM HF88S05 The Checksum Register keeps the Exclusive OR checksum of the data bytes as they are written to/read from SRAM. The Checksum register cannot be written but it is cleared by any access to the TPL, TPH and TPP registers. 7. Parallel Mode When in parallel mode, an 8-bit data bus D[7..0] are used to transfer information between MCU and SRAM. The advantage of parallel transfer mode is that higher speed can be achieved. To operate in parallel mode, the P_Sn pin should be driven with high level voltage. 7.1. Parallel Write Command Mode Loading of Addresses and Mode Register in parallel mode are by asserting the Strobe (going low and then high) in write command mode (both R_Wn and D_Cn are low), which will also clear the CHKSUM register at the same time. After the previous data transfer or when the device is just selected (CS1 is high and CS0n is low), the command data will be written to registers in the order of TPL, TPH, TPP, then Mode, TPL… So when unsure, a dummy data read or deselect and select the device again will reset the register select. The timing chart below exemplifies when original TP is 0x02017f, then 0x00, 0x01, 0x02 was written sequentially to TPL, TPH, then TPP, the TP becomes 0x020100. -6- 02/07/01 Command Mode SRAM HF88S05 7.2. Parallel Write Data Mode To write data to SRAM in parallel mode, assert Strobe in Data Write Mode (D_Cn @ Vih and R_Wn at Vil). The checksum register will be updated, and the TP register will be incremented at the rising edge of Strobe signal. 7.3. Parallel Read Data Mode To Read from SRAM in parallel mode, assert the Strobe in Read Data mode (R_Wn at high and D_Cn low). The data will appear on the Data bus after proper access time. The TP will increment and Checksum will update at the rising edge of Strobe. Register select will be reset by Read Data operation. 7.4. Parallel Read Checksum Mode To read the checksum result from previous data transfer (either from SRAM or to SRAM), assert the Strobe signal in Read Command mode (R_Wn is high and D_Cn low). -7- 02/07/01 Command Mode SRAM HF88S05 8. Serial Mode The serial interface is preferable to parallel interface in applications where I/O pins are limited. The interface logic circuit is basically the same as the parallel mode except that an internal shift register and bit counter are used to facilitate transferring serial data from/to external MCU. Multiple devices array can also be used in serial mode. The chip array is connected in daisy chain manner. The MCU’s serial data output pin drives the SDI pin of the first device. The SDO pin of the device then, in turn, drives the SDI pin of the next device in the chain. The SDO pin of the last device then connects back to the MCU’s SDI pin to complete the loop. There could be only one active device in the array at one time, while the other device must be deselected. 8.1. Bi-directional Synchronous Serial Data Interface The Serial interface is a Bi-directional Synchronous Serial Interface. The Serial Data can be written to Registers (such as TPL, TPH, TPP registers) as well as SRAM through the serial interface. The Checksum and SRAM contents can also be read through Serial Interface, too. The Serial Data Input SDI pin is connected to LSB of internal shift register. With each rising edge of SCLK pin, the SDI input is shifted into the shift register. At the eighth rising edge of SCLK, the content of shift Register is transferred from/to registers or SRAM depending on the status of D_Cn and R_Wn. If R_Wn is at “high” state at the eighth rising edge of SCLK then either the contents of -8- 02/07/01 Command Mode SRAM HF88S05 Checksum Register (if D_Cn is “low”) or SRAM been addressed (if D_Cn is “high”) will be latched into the internal shift register. Then the contents of Shift Register can be shifted out with the next eight rising edges of SCLK. So one thing important should be noted here when using the Serial Data Interface to read checksum register or SRAM data is that one dummy read should be performed before the real data can be shifted out from SDO pin. 8.2. Serial Write Command Mode The sequence of setting up addresses for data transfer is similar to the parallel mode. The register pointer will be reset by accesses to SRAM data in the same way as the parallel mode does. So immediately after completion of previous data transfers or when the device is just selected, the command writes will be made to TPL, TPH then TPP registers and then wrap around. If unsure any time during the transfer, a dummy data read can be made to reset the register select. 8.3. Serial Write Data Mode With each rising edge of SCLK signal in the serial data write mode (P_Sn @ logic ‘0’, R_Wn @ logic ‘0’, and D_Cn @ logic ‘1’), the Data on the SDI pin will be shifted into the internal shift register. The content of less significant 7 Bits of the internal shift register along with SDI pin will be transfer to SRAM at the eighth rising edge of SCLK. The checksum register will be updated, and the TP register will be incremented. The status of R_Wn, D_Cn and SDI must be held steady in the mean time. -9- 02/07/01 Command Mode SRAM HF88S05 8.4. Serial Read Data Mode If both R_Wn, and D_Cn are at high level at the eighth rising edge of SCLK then the contents of SRAM been addressed will be latched into the internal shift register. Then the contents of shift register can be shifted out with the next eight rising edges of SCLK. So one thing important should be noted here when using the Serial Data Interface to read SRAM data is that one dummy read should be performed before the real data can be shifted out from SDO pin. 8.5. Serial Read Checksum Mode Reading checksum in serial mode is similar to Read data mode except that the D_Cn is at low level instead of high. -10- 02/07/01 Command Mode SRAM HF88S05 9. Power consideration In order to conserve power consumed by the device, the static power consumption by SRAM Sense Amplifier need to be minimized. Since the Sense Amplifier is on whenever the device is selected and Strobe/SCLK is asserted low in Data Read Mode. Therefore the way to save power is to minimize the duty of the overall Strobe/SCLK signal to an extent that it is just long enough to satisfy the access time so that the static power consumption can be lowered. 10. Absolute Maximum Rating Items Supply Voltage Input Voltage Operating Temperature Storage Temperature Symbol VDD VIN TOPR TSTR Rating -0.3 to 6 V -0.3 to Vdd+0.3 V -0 to 70 °C -55 to 125 °C Condition 11. AC Electrical Characteristics READ CYCLE Item Access Time Symbol VCC=5V±0.5V Min Max VCC=2.7V±0.3V Min Max TBD TBD tacc -11- Unit ns 02/07/01 Command Mode SRAM HF88S05 12. Electrical Characteristics (VSS = 0V, VDD = 5.0 V, TOPR = 25°C unless otherwise noted) Parameter Sym. Min. Typ. Max Unit Supply Voltage VDD 2.4 - 5.5 V Operating Current IDD - TBD - mA No load Standby Current IDD - 10 - µA No load Input voltage VIH 0.7 - 1 VDD VDD = 4V ~ 6V VIL 0 - 0.3 IIL - - +/- 10 Input current leakage Condition µA 13. Application Circuit The application circuit diagram shows one of the KB’s MCU uses two HF88S05 as expansion RAMs. Please note that the SDO pin of the first device drive SDI pin of the second device and only one device select pin DEV1 is used to select between one of the two device. The P_Sn pins are tied to ground operate at serial mode. -12- 02/07/01 Command Mode SRAM HF88S05 11 12 K20 K27 K34 K5 K12 K19 K26 Option K33 K4 K11 K18 K25 Redial K32 K3 K10 K17 K24 K31 P155 P154 P153 P152 P151 P150 18p VDD C11 R8 103 C1 AVDD RING TIP RST PC0 PC1 PC2 PC3 PC4 PC5 PC6 464K C13 C9 104 R16 R13 D7 AVDD 60.4K 34K 34K D9 1N4148 2 R9 1N4148 D3 R10 1N4148 D4 C7 1N4004 C5 104/250V 1N4004 C6 104/250V T R 472/250V 472/250V D6 1N4004 0.22uF C8 D5 1N4004 2 430K430K L2 L1 100uH 100uH RV1 250V F1 4 LINE 3 2 FUSE 250V/0.25A 1 270K AGND 2 2 1 1 1 D8 1N4148 2 1 2 1 C10 33K 470K 1 + KTONE R14 VDD AGND R1 D2 High Pot! Keep Clearance! OFFHK KTONE DTMFO OFFHK D1 AVDD 2 1N4148 R11 R12 PHONE Phone Interface R 1 R2 53.6K 2 33p 1 C4 1 32768 2 33p Ring detector 104 104 T RNGDET 60K C3 J1 RJ11C -13- HOLD HF Mute AGND 0.22uF R15 02/07/01 P174 P173 P172 RNGDET 1 P171 P170 3 RNGRC P154 P155 P156 P157 P170 P171 P172 P173 P174 P175 P176 P177 + INP 16 15 14 13 12 11 10 9 8 7 6 5 4 2 CAP1 R17 Y1 PGM VDD 560K C2 VDD M5 M4 0 P156 R3 560K 270K PC7 DTMFO 3579545Hz 18p KTONE VTDET C15 R7 R6 560K Y2 C14 Dial DOWN Flash * 4 K29 KB88A42 87 86 INN GCFB 85 84 VREF VSSA 83 VDDA 82 K22 P153 P152 P151 P150 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG15 SEG14 SEG13 SEG16 28 S16/P140 27 S17/P141 26 S18/P142 25 S19/P143 24 S20/P144 23 S21/P145 22 S22/P146 21 S23/P147 20 S24/P150 19 S25/P151 18 S26/P152 17 S27/P153 30 31 29 RSTP PRTC0 PRTC1 PRTC2 K15 R4 560K CAP2 81 80 79 PRTC4 PRTC5 PRTC3 78 77 76 75 PRTC6 PRTC7 74 KEYTONE 8 5 K8 7 2 K1 U1 RNGDI 73 DTMFO 72 71 VDTR 70 VDD 69 K30 2 R5 560K S15 S14 S13 S12 SEG9 SEG11 SEG10 SEG12 32 33 34 35 S9 S11 S10 SEG6 SEG8 36 S8 S7 SEG4 SEG3 SEG5 SEG2 SEG1 SEG0 SEG7 37 S6 38 39 S5 40 S4 41 S3 43 44 42 S2 S1 S0 TSTP 67 66 SXI OPIN OPIP OPO 104 104 104 104 DTMFO C16 C17 C18 C19 SXO 104 100K K23 D10 1 S28/P154 S29/P155 S30/P156 S31/P157 S32/P170 S33/P171 S34/P172 S35/P173 S36/P174 S37/P175 S38/P176 S39/P177 RNGRC 68 R18 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 LC1 LC2 LVF LV1 LV2 LV3 LV4 GND OPIN OPIP OPO FXO FXI K16 2 1N4148 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 # K9 9 K2 D11 1 9 8 7 6 1N4148 6 2 3 1 1 D4 D3 D12 HF88S05 Pause 10 D5 D2 11 D6 D1 12 D7 13 2 1N4148 D0 14 SCLK R_WN SCLK 5 R_Wn SDI D_CN 15 18 17 DEV1 16 SDO CS1 SDO VDD CS0N P_SN VSS 4 3 2 1 D_Cn SEG[23..0] D13 1 UP Erase 2 1N4148 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 C12 M3 D14 1N4148 LCDPANEL LCD Panel M2 M1 1N4148 1 VDD M10 K13 M9 K6 M8 K35 M7 K28 M6 K21 2 R_Wn D_Cn DEV1 K14 D15 1 COM[7..0] K7 Auto D3 D2 D1 2 1N4148 9 8 7 15 SDI 14 SCLK 13 D16 D0 16 17 10 D4 D5 D6 D7 HF88S05 1 6 R_WN SCLK 5 SDI D_CN CS1 VDD SDO VSS P_SN CS0N 4 2 1 3 18 VDD