KB HF88S05

KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
HF88S05
SRAM Series
– Table of Contents –
1.
General Description____________________________________________________________ 2
2.
Features _____________________________________________________________________ 2
3.
Pin Description _______________________________________________________________ 3
4.
Pad Diagram & Coordinates _____________________________________________________ 4
5.
Function Block Diagram________________________________________________________ 5
6.
Parallel Mode_________________________________________________________________ 6
6.1. Parallel Write Command Mode ___________________________________________________ 6
6.2. Parallel Write Data Mode _______________________________________________________ 6
6.3. Parallel Read Data Mode _______________________________________________________ 7
6.4. Parallel Checksum Read Mode ___________________________________________________ 7
7.
Serial Mode __________________________________________________________________ 7
7.1. Bi-directional Synchronous Serial Data Interface ____________________________________ 7
7.2. Serial Command Write Mode ____________________________________________________ 8
7.3. Serial Data Write Mode _________________________________________________________ 8
7.4. Serial Data Read Mode _________________________________________________________ 9
7.5. Serial Command Read Mode____________________________________________________ 10
8.
Power consideration___________________________________________________________ 10
9.
Absolute Maximum Rating _____________________________________________________ 11
10. AC Electrical Characteristics ___________________________________________________ 11
11. Electrical Characteristics ______________________________________________________ 11
12. Application Circuit____________________________________________________________ 12
13. Update History _______________________________________________________________ 13
December 18, 2003
1
V1.00
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
HF88S05
SRAM Series
1. General Description
The HF88S05 is a command mode SRAM device. It features dual (parallel and serial) command access
modes. Multiple device arrays can be accessed with only minimal additional device select pin. Simple
Exclusive OR checksum provides error detection during data transfer between MCU and the device. The
interface logic and protocol include setting up the starting address for data transfer, writing data into
RAM, as well as read it back for verification, and error checking by Exclusive OR checksum. It can be
used for Read/Write memory extension for all KB’s MCUs.
Chip Select pins allows array of HF88S05 devices are used simultaneously for both parallel and serial
transfer mode. In the serial mode, the HF88S05 is connected in daisy chain configuration to minimize
the I/O pins required to use multi-chip array, while in parallel mode, the devices share most of the control
pins and data bus except the chip select pins.
2. Features
9
9
9
9
9
9
9
Dual (parallel and serial) command access modes.
Address automatically increment with each Read/Write data access.
Exclusive or checksum error detection
Multiple chip array is allowed with easy addressing logic
Read access voltage range 2.7V ~ 3.6V
Organization -- Memory Cell Array: 64K × 8
Package – Dice form
December 18, 2003
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KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
HF88S05
SRAM Series
3. Pin Description
1
2
3
4
5
6
7
8
9
P_SN
VSS
CS0N
D_CN
R_WN
D0
D1
D2
D3
VDD
CS1
SDO
SDI
SCLK
D7
D6
D5
D4
18
17
16
15
14
13
12
11
10
HF88S05
Symbol
P_Sn
VSS
CS0n
D_Cn
R_Wn
D0 ~ D7
SCLK/
Strobe
SDI
SDO
CS1
VDD
I/O Description
I
I
I
Input to select either parallel (when ‘1’) or serial (when ‘0’) interface is used for transferring data.
Negative power supply of the device
CS0n is active low chip select input pin. The device is selected when CS1 is high and CS0n is
low simultaneously. Otherwise, it is deselected.
I Input to select either the SRAM or Registers (TPP, TPH, TPL, Mode or Checksum) operations.
I Input to select either a Read operation (when ‘1’) or a write operation (when ‘0’) is to be
performed.
I/O Bi-directional data bus for parallel transfer mode.
I This pin is shared between parallel and serial modes. In serial mode, this pin is Serial Clock
SCLK for transferring the data from/to SDI/SDO. In parallel mode, it is the strobe signal used to
write the registers and SRAM as well as read the checksum and contents of SRAM. This pin is
equipped with Schmidt type input structure to prevent the input from chattering due to slow rising
clock source transition.
I Serial Data Input for writing to either Registers or SRAM.
O Serial Data Output for reading data from either Checksum Register or SRAM.
I CS1 is active high chip select input. The device is selected when CS1 is high and CS0n is low
simultaneously. Otherwise, it is deselected.
I Positive power supply of the device
December 18, 2003
3
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KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
HF88S05
SRAM Series
4. Pad Diagram & Coordinates
Pin Number Pin Name X Coordinate Y CoordinatePin NumberPin NameX Coordinate Y Coordinate
1
P_SN
-1970.5
1260.4
12
D4
1150.32
-1088.97
2
VSS
-1970.5
960.41
13
D5
1375.93
-1088.97
3
VSS
-1970.5
707.54
14
D6
1762.16
-1088.97
4
VSS
-1970.5
394.22
15
D7
1964.53
-759.28
5
CS0N
-1970.5
159.23
16
SCLK
1964.53
-538.44
6
D_CN
-1970.5
-177.15
17
SDI
1964.53
-221.71
7
R_WN
-1970.5
-465.52
18
SDO
1964.53
-0.91
8
D0
-1970.5
-780.53
19
CS1
1964.53
347.7
9
D1
-1725.02
-1088.97
20
VDD
1964.53
600.92
10
D2
-1521.22
-1088.97
21
VDD
1964.53
831.74
11
D3
-1152.68
-1088.97
22
VDD
1964.53
1114.36
December 18, 2003
4
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HF88S05
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
SRAM Series
5. Function Block Diagram
Several registers are used in the interface logic. The functions of the registers are described below and
their initial values are as indicated in the following table.
DIN[7..0]
TP[15..0]
64Kx8
Static
RAM
ARRAY
DOUT[7..0]
+1
MUX
MUX
XOR
S2P
CHKSUM
Register
TPL
TPH
TPP
Checksum
Type
W
W
W
R
Description
Address register 0 for A7 ~ A0
Address register 1 for A15 ~ A8
Address register 2 for A23 ~ A16
XOR checksum of data
D[7..0]
P_Sn
D_Cn
R_Wn
SDI
SDO
SCLK/Strobe
CS0n
MUX
CS1
TPP
TPH
TPL
Initial Value
“--------“
“--------“
“--------“
“--------“
The Table Pointer register keeps the address of SRAM being written to or read from. It will
automatically increment by one with each read/write access, but remains unchanged when writing
command or reading checksum.
The Checksum Register keeps the Exclusive OR checksum of the data bytes as they are written to/read
from SRAM. The Checksum register cannot be written but it is cleared by any access to the TPL, TPH
December 18, 2003
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HF88S05
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
SRAM Series
and TPP registers.
6. Parallel Mode
When in parallel mode, an 8-bit data bus D[7..0] are used to transfer information between MCU and
SRAM. The advantage of parallel transfer mode is that higher speed can be achieved. To operate in
parallel mode, the P_Sn pin should be driven with high level voltage.
6.1. Parallel Write Command Mode
Loading of Addresses and Mode Register in parallel mode are by asserting the Strobe (going low and then
high) in write command mode (both R_Wn and D_Cn are low), which will also clear the CHKSUM
register at the same time. After the previous data transfer or when the device is just selected (CS1 is
high and CS0n is low), the command data will be written to registers in the order of TPL, TPH, TPP, then
Mode, TPL… So when unsure, a dummy data read or deselect and select the device again will reset the
register select.
The timing chart below exemplifies when original TP is unknown, then 0x00, 0x01, 0x02 addresses were
written sequentially to TPL, TPH, and then TPP, the TP becomes 0x020100h.
TAss
CS0_n
CS1
P_Sn
D_Cn
R_Wn
TPL
00
D[7:0]
TSetup
TPH
01
TPP
02
55
aa
78
THold
SCLK
TP
xxxxxx
(TPP, TPH, TPL)
xxxx00
xx0100
020100
020101
020102
020103
Parallel Command/Data Write Mode
6.2. Parallel Write Data Mode
To write data to SRAM in parallel mode, assert Strobe in Data Write Mode (D_Cn @ Vih and R_Wn at
Vil). The checksum register will be updated, and the TP register will be incremented at the rising edge of
Strobe signal.
December 18, 2003
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HF88S05
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
SRAM Series
6.3. Parallel Read Data Mode
To Read from SRAM in parallel mode, assert the Strobe in Read Data mode (R_Wn at high and D_Cn
low). The data will appear on the Data bus after proper access time. The TP will increment and
Checksum will update at the rising edge of Strobe. Register select will be reset by Read Data operation.
TAss
CS0_n
CS1
P_Sn
D_Cn
R_Wn
TPL
00
D[7:0]
TSetup
TPH
01
TPP
02
THold
55
TCG
aa
78
3F
Checksum
TRD
SCLK
TP
xxxxxx
(TPP, TPH, TPL)
xxxx00
xx0100
020100
020101
020102
020103
Parallel Data/Checksum Read Mode
6.4. Parallel Checksum Read Mode
To read the checksum result from previous data transfer (either from SRAM or to SRAM), assert the
Strobe signal in Read Command mode (R_Wn is high and D_Cn low).
7. Serial Mode
The serial interface is preferable to parallel interface in applications where I/O pins are limited. The
interface logic circuit is basically the same as the parallel mode except that an internal shift register and
bit counter are used to facilitate transferring serial data from/to external MCU.
Multiple devices array can also be used in serial mode. The chip array is connected in daisy chain
manner. The MCU’s serial data output pin drives the SDI pin of the first device. The SDO pin of the
device then, in turn, drives the SDI pin of the next device in the chain. The SDO pin of the last device
then connects back to the MCU’s SDI pin to complete the loop.
There could be only one active device in the array at one time, while the other device must be deselected.
7.1. Bi-directional Synchronous Serial Data Interface
The Serial interface is a Bi-directional Synchronous Serial Interface. The Serial Data can be written to
Registers (such as TPL, TPH, TPP registers) as well as SRAM through the serial interface. The
December 18, 2003
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HF88S05
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
SRAM Series
Checksum and SRAM contents can also be read through Serial Interface, too.
The Serial Data Input SDI pin is connected to LSB of internal shift register. With each rising edge of
SCLK pin, the SDI input is shifted into the shift register. At the eighth rising edge of SCLK, the content
of shift Register is transferred from/to registers or SRAM depending on the status of D_Cn and R_Wn.
If R_Wn is at “high” state at the eighth rising edge of SCLK then either the contents of Checksum
Register (if D_Cn is “low”) or SRAM been addressed (if D_Cn is “high”) will be latched into the internal
shift register. Then the contents of Shift Register can be shifted out with the next eight rising edges of
SCLK.
So one thing important should be noted here when using the Serial Data Interface to read checksum
register or SRAM data is that one dummy read should be performed before the real data can be shifted
out from SDO pin.
7.2. Serial Command Write Mode
The sequence of setting up addresses for data transfer is similar to the parallel mode. The register
pointer will be reset by accesses to SRAM data in the same way as the parallel mode does. So
immediately after completion of previous data transfers or when the device is just selected, the command
writes will be made to TPL, TPH then TPP registers and then wrap around. If unsure any time during
the transfer, a dummy data read can be made to reset the register select.
CS0_n
CS1
P_Sn
D_Cn
R_Wn
SDI
b7
SDO
b6
b5
b4
b3
b2
b1
b0
b7
b6
b5
b4
b3
b2
b1
b0
b7
b6
The bit 7 shall be shifted into register first.
SCLK
TP
(TPP, TPH, TPL)
xxxxxx
Update TPL
Update TPH
Series Command Write Mode
7.3. Serial Data Write Mode
With each rising edge of SCLK signal in the serial data write mode (P_Sn @ logic ‘0’, R_Wn @ logic ‘0’,
and D_Cn @ logic ‘1’), the Data on the SDI pin will be shifted into the internal shift register. The content
December 18, 2003
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HF88S05
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
SRAM Series
of less significant 7 Bits of the internal shift register along with SDI pin will be transfer to SRAM at the
eighth rising edge of SCLK. The checksum register will be updated, and the TP register will be
incremented. The status of R_Wn, D_Cn and SDI must be held steady in the mean time.
CS0_n
CS1
P_Sn
D_Cn
R_Wn
SDI
User shall update the initial address (TP) before
writing the data into SRAM.
b7
SDO
b6
b5
b4
b3
b2
b1
b0
b7
b6
b5
b4
b3
b2
b1
b0
b7
b6
The bit 7 shall be shifted into register first.
SCLK
TP
(TPP, TPH, TPL)
020100
020101
020102
Series Data Write Mode
7.4. Serial Data Read Mode
If both R_Wn, and D_Cn are at high level at the eighth rising edge of SCLK then the contents of SRAM
been addressed will be latched into the internal shift register. Then the contents of shift register can be
shifted out with the next eight rising edges of SCLK.
So one thing important should be noted here when using the Serial Data Interface to read SRAM data
is that one dummy read should be performed before the real data can be shifted out from SDO pin.
December 18, 2003
9
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HF88S05
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
SRAM Series
CS0_n
CS1
P_Sn
D_Cn
R_Wn
User shall update the initial address (TP) before
reading the data from SRAM.
SDI
b7 b6 b5 b4 b3
b2 b1 b0 b7
User shall dummy read 8 bits, and then the real
first msb b7 will be output.
SDO
Internal
Strobe
The bit 7 shall be shifted into register first
b6
b5
b4
b3
b2
b1
b0
b7
b6
Internal Strobe signal is used to latch SRAM data into shifter register, and generated at each 8th sclk.
SCLK
TP
(TPP, TPH, TPL)
020101
020100
020102
Series Data Read Mode
7.5. Serial Command Read Mode
Reading checksum in serial mode is similar to Read data mode except that the D_Cn is at low level
instead of high.
8. Power consideration
In order to conserve power consumed by the device, the static power consumption by SRAM sense
amplifier need to be minimized. Since the sense amplifier is on whenever the device is selected and
Strobe/SCLK is asserted low in Data Read Mode. Therefore the way to save power is to minimize the
duty of the overall Strobe/SCLK signal to an extent that it is just long enough to satisfy the access time so
that the static power consumption can be lower.
December 18, 2003
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HF88S05
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
SRAM Series
9. Absolute Maximum Rating
Items
Supply Voltage
Input Voltage
Operating Temperature
Storage Temperature
Symbol
VDD
VIN
TOPR
TSTR
Rating
Condition
-0.3 to 4.0 V
-0.3 to Vdd+0.3 V
-0 to 70 °C
-55 to 125 °C
10. AC Electrical Characteristics
Item
Chip Asserted Time
Data Setup Time
Data Hold Time
Pre-charge Time
Data Ready Time
VCC=3.0V
Symbol
Min
100
200
150
120
250
TAss
TSetup
THold
TCG
TRD
Unit
Max
-
ns
ns
ns
ns
ns
11. Electrical Characteristics
(VDD = 3.0 V, TOPR = 25°C unless otherwise noted)
Parameter
Symbol
Min. Typ.
Supply Voltage
VDD
2.7
Operating Current
IDD
TBD
Standby Current
IDD
10
VIH
0.7
Input voltage
VIL
0
Input current leakage
IIL
-
December 18, 2003
11
Max
3.6
1
0.3
+/- 10
Unit
V
mA
µA
Condition
No load
No load
VDD
VDD = 4V ~ 6V
µA
V1.00
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HF88S05
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
SRAM Series
12. Application Circuit
11
12
13
Redial
M10
K18
K25
K32
K3
K10
K17
K24
K31
M9
Option
K11
M8
K4
M7
K33
M6
K26
M5
M4
M3
M2
#
HF
K23
K30
0
Mute
K15
K22
K29
*
4
8
5
K8
7
2
K1
PGM
P156
P155
P154
P153
P152
P151
P150
R7
R6
560K
P153
R4
560K
U1
VDD
C11
R8
103
C1
1
CAP1
AVDD
P174
RNGDET
2
P173
3
P172
P154
P155
P156
P157
P170
P171
P172
P173
P174
P175
P176
P177
P171
16
15
14
13
12
11
10
9
8
7
6
5
4
RNGRC
INP
P170
560K
87
86
INN
GCFB
R3
560K
KB88A42
+
P152
P151
P150
SEG23
SEG22
HOLD
Flash
9
6
K16
2
R5
560K
85
VREF
Dial
DOWN
UP
Erase
3
K9
1
D4
D3
9
8
7
K2
D10
84
VSSA
83
VDDA
82
K19
2
1
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
K12
D11
28
S16/P140
27
S17/P141
26
S18/P142
25
S19/P143
24
S20/P144
23
S21/P145
22
S22/P146
21
S23/P147
20
S24/P150
19
S25/P151
18
S26/P152
17
S27/P153
RSTP
PRTC0
PRTC1
PRTC2
K5
Pause
10
D5
D2
11
D6
D1
12
D7
D0
13
6
1N4148
CAP2
81
80
79
78
PRTC3
77
PRTC4
PRTC6
PRTC7
PRTC5
76
75
74
K34
2
1
RNGDI
73
KEYTONE
72
KTONE
DTMFO
71
VDTR
DTMFO
VDD
70
VTDET
K27
D12
1
S15
29
31
32
30
S14
S13
S12
SEG9
SEG11
33
S11
SEG8
SEG10
34
36
35
S9
S8
S7
S10
SEG5
SEG6
SEG4
SEG3
SEG2
SEG1
SEG0
SEG7
37
38
S6
39
S5
S4
40
S3
41
42
44
43
S1
S0
S2
SXI
SXO
TSTP
67
66
69
104 104 104 104
K20
2
1N4148
HF88S05
S28/P154
S29/P155
S30/P156
S31/P157
S32/P170
S33/P171
S34/P172
S35/P173
S36/P174
S37/P175
S38/P176
S39/P177
RNGRC
68
C16 C17 C18 C19
OPIN
OPIP
OPO
K13
D13
1
R_WN SCLK
14 SCLK
SDI
5
R_Wn
D_CN
15
18
17 DEV1
16 SDO
CS1
SDO
VDD
CS0N
P_SN
VSS
4
3
2
1
D_Cn
COM[7..0]
104
100K
K6
2
1N4148
SEG[23..0]
R18
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
LC1
LC2
LVF
LV1
LV2
LV3
LV4
GND
OPIN
OPIP
OPO
FXO
FXI
K35
D14
1N4148
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
K28
M1
R_Wn
DEV1
D_Cn
1N4148
1N4148
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
C12
K21
2
1
LCDPANEL
LCD Panel
K14
D15
1
VDD
K7
Auto
D3
2
1N4148
9
D2
D1
8
7
16
17
10
D4
D6
D5
D7
D16
D0
R_WN SCLK
HF88S05
1
6
SDI
D_CN
5
CS1
VDD
SDO
VSS
P_SN
CS0N
4
2
1
3
18
VDD
15 SDI
14 SCLK
The application circuit diagram shows one of the KB’s MCU uses two HF88S05 as expansion RAMs.
Please note that the SDO pin of the first device drive SDI pin of the second device and only one device
select pin DEV1 is used to select between one of the two devices. The P_Sn pins are tied to ground
operate at serial mode.
AGND
Y2
18p
VDD
464K
R17
C13
C2
104
104
R16
R13
D7
AVDD
60.4K
34K 34K
2
1
2
1
D8
1N4148 2
1
D9
1N4148 2
R9
1N4148
D3
R10
1N4148
430K430K
D4
C8
C7
D6
1N4004
1N4004
C5
104/250V
1N4004
C6
104/250V
T
R
472/250V
472/250V
D5
1N4004
0.22uF
High Pot! Keep Clearance!
L2
L1
100uH
100uH
RV1
250V
F1
4
LINE
3
1
FUSE
250V/0.25A
2
270K
AGND
1
1
C10
33K
470K
2
R14
VDD
AGND
R1
D2
+
KTONE
OFFHK
OFFHK
KTONE
DTMFO
DTMFO
D1
AVDD
2
1N4148
R11 R12
PHONE
Phone Interface
R
1
R2
53.6K
2
33p
1
C4
2
32768
1
33p
1
C3
Y1
2
104
Ring detector
60K
RNGDET
C9
VDD
T
0.22uF
RING
TIP
RST
PC0
PC1
PC2
PC3
PC4
PC5
3579545Hz
18p
270K
R15
PC6
C15
PC7
C14
J1
RJ11C
December 18, 2003
12
V1.00
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
HF88S05
SRAM Series
13. Update History
Version
V1.0
Date
12/17/03
December 18, 2003
Revision Description
Modify the SRAM access timing diagram.
13
V1.00
This specification is subject to change without notice. Please contact sales person for the latest version before use.