NB100LVEP222 2.5V/3.3V 1:15 Differential ECL/PECL ÷1/÷2 Clock Driver The NB100LVEP222 is a low skew 1:15 differential ÷1/÷2 ECL fanout buffer designed with clock distribution in mind. The LVECL/LVPECL input signal pairs can be used in a differential configuration or single-ended (with VBB output reference bypassed and connected to the unused input of a pair). Either of two fully differential clock inputs may be selected. Each of the four output banks of 2, 3, 4, and 6 differential pairs may be independently configured to fanout 1X or 1/2X of the input frequency. The LVEP222 specifically guarantees low output to output skew. Optimal design, layout, and processing minimize skew within a device and from lot to lot. This device is an improved version of the MC100LVE222 with higher speed capability and reduced skew. The fsel pins and CLK_Sel pin are asynchronous control inputs. Any changes may cause indeterminate output states requiring an MR pulse to resynchronize any 1/2X outputs (See Figure 3). Unused output pairs should be left unterminated (open) to reduce power and switching noise. The NB100LVEP222, as with most ECL devices, can be operated from a positive VCC supply in LVPECL mode. This allows the LVEP222 to be used for high performance clock distribution in +2.5/3.3 V systems. In a PECL environment series or Thevenin line, terminations are typically used as they require no additional power supplies. For more information on using PECL, designers should refer to Application Note AN1406/D. For a SPICE model, refer to Application Note AN1560/D. The VBB pin, an internally generated voltage supply, is available to this device only. For single- ended LVPECL input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. Single- ended CLK input operation is limited to a VCC ≥ 3.0 V in LVPECL mode, or VEE -3.0 V in NECL mode. • • • • • http://onsemi.com MARKING DIAGRAM* NB100 LVEP222 AWLYYWW 52-LEAD LQFP THERMALLY ENHANCED CASE 848H FA SUFFIX A WL YY WW 52 1 = Assembly Location = Wafer Lot = Year = Work Week *For additional information, see Application Note AND8002/D ORDERING INFORMATION Device NB100LVEP222FA Package Shipping LQFP-52 160 Units/Tray NB100LVEP222FAR2 LQFP-52 1500/Tape & Reel 20 ps Output-to-Output Skew 85 ps Part-to-Part Skew Selectable 1x or 1/2x Frequency Outputs LVPECL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -2.375 V to -3.8 V Internal Input Pulldown Resistors • • Performance Upgrade to ON Semiconductor’s MC100LVE222 • VBB Output Semiconductor Components Industries, LLC, 2003 January, 2003- Rev. 8 1 Publication Order Number: NB100LVEP222/D Qc0 Qc1 Qc1 Qc2 Qc2 Qc3 Qc3 VCC0 NC NC 39 40 38 37 36 35 34 33 32 31 30 29 28 VCC0 Qc0 VCC0 VCC0 NB100LVEP222 27 26 Qd0 Qb2 41 25 Qd0 Qb2 42 24 Qd1 Qb1 43 23 Qd1 Qb1 44 22 Qd2 Qb0 45 21 Qd2 Qb0 46 20 Qd3 VCC0 47 19 Qd3 Qa1 48 18 Qd4 Qa1 49 17 Qd4 Qa0 50 16 Qd5 Qa0 51 15 Qd5 VCC0 52 14 VCC0 CLK0 CLK_Sel CLK1 9 10 11 12 13 VEE 8 fseld 7 fselc 6 VBB 5 CLK1 4 CLK0 MR 3 fselb 2 fsela 1 VCC NB100LVEP222 All VCC, VCCO, and VEE pins must be externally connected to appropriate Power Supply to guarantee proper operation. The thermally conductive exposed pad on package bottom (see package case drawing) must be attached to a heat-sinking conduit. This exposed pad is electrically connected to VEE internally. Figure 1. 52-Lead LQFP Pinout (Top View) PIN DESCRIPTION FUNCTION TABLE Function PIN FUNCTION CLK0*, CLK0** CLK1*, CLK1** CLK_Sel* MR* Qa0:1, Qa0:1 Qb0:2, Qb0:2 Qc0:3, Qc0:3 Qd0:5, Qd0:5 fseln* VBB VCC, VCCO VEE*** NC ECL Differential Input Clock ECL Differential Input Clock ECL Clock Select ECL Master Reset ECL Differential Outputs ECL Differential Outputs ECL Differential Outputs ECL Differential Outputs ECL 1 or 2 Select Reference Voltage Output Positive Supply Negative Supply No Connect Input L H MR CLK_Sel fseln Active CLK0 ÷1 Reset CLK1 ÷2 * Pins will default LOW when left open. ** Pins will default HIGH when left open. *** The thermally conductive exposed pad on the bottom of the package is electrically connected to VEE internally. http://onsemi.com 2 NB100LVEP222 MR CLK0 CLK0 ÷1 CLK1 2 ÷2 Qa0:1 Qa0:1 CLK1 CLK_SEL VBB fsela 3 Qb0:2 Qb0:2 fselb 4 Qc0:3 Qc0:3 VCC VEE fselc 6 Qd0:5 Qd0:5 fseld Figure 2. Logic Diagram CLK MR Q (2) Q (1) Figure 3. Master Reset (MR) Timing Diagram http://onsemi.com 3 NB100LVEP222 ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor 37.5 k ESD Protection Human Body Model Machine Model Charged Device Model > 2 kV > 200 V > 2 kV Moisture Sensitivity (Note 1) Level 3 Flammability Rating Oxygen Index: 28 to 34 UL 94 V-0 @ 0.125″ Transistor Count 821 Devices Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, refer to Application Note AND8003/D. MAXIMUM RATINGS (Note 2) Symbol Parameter Condition 1 Condition 2 Rating Units VCC PECL Mode Power Supply VEE = 0 V 6 V VEE NECL Mode Power Supply VCC = 0 V -6 V VI Input PECL Mode In ut Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 to 0 -6 to 0 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ±0.5 mA TA Operating Temperature Range -40 to +85 °C Tstg Storage Temperature Range -65 to +150 °C JA Thermal Resistance (Junction-to-Ambient) (See Application Information) 0 LFPM 500 LFPM 52 LQFP 52 LQFP 35.6 30 °C/W °C/W JC Thermal Resistance (Junction-to-Case) (See Application Information) 0 LFPM 500 LFPM 52 LQFP 52 LQFP 3.2 6.4 °C/W °C/W Tsol Wave Solder 265 °C VI ≤ VCC VI ≥ VEE < 2 to 3 sec @ 248°C 2. Maximum Ratings are those values beyond which device damage may occur. LVPECL DC CHARACTERISTICS VCC = 2.5 V; VEE = 0 V (Note 3) -40 °C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit IEE Power Supply Current 100 125 150 104 130 156 112 140 168 mA VOH Output HIGH Voltage (Note 4) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV VOL Output LOW Voltage (Note 4) 555 680 900 555 680 900 555 680 900 mV VIH Input HIGH Voltage (Single-Ended) (Note 5) 1335 1620 1335 1620 1275 1620 mV VIL Input LOW Voltage (Single-Ended) (Note 5) 555 900 555 900 555 900 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 6) (Figure 5) 1.2 2.5 1.2 2.5 1.2 2.5 V IIH Input HIGH Current 150 A IIL Input LOW Current 150 CLK CLK 0.5 -150 0.5 -150 NOTE: 3. 4. 5. 6. 150 0.5 -150 A 100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. Input and output parameters vary 1:1 with VCC. VEE can vary + 0.125 V to -1.3 V. All loading with 50 to VCC - 2.0 V. Do not use VBB Pin #10 at VCC < 3.0 V (see AND8066). VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 NB100LVEP222 LVPECL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V (Note 7) -40 °C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit IEE Power Supply Current 100 125 150 104 130 156 112 140 168 mA VOH Output HIGH Voltage (Note 8) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV VOL Output LOW Voltage (Note 8) 1355 1480 1700 1355 1480 1700 1355 1480 1700 mV VIH Input HIGH Voltage (Single-Ended) 2135 2420 2135 2420 2135 2420 mV VIL Input LOW Voltage (Single-Ended) 1355 1700 1355 1700 1355 1700 mV VBB Output Reference Voltage (Note 9) 1775 1975 1775 1975 1775 1975 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 10) (Figure 5) 1.2 3.3 1.2 3.3 1.2 3.3 V IIH Input HIGH Current 150 A IIL Input LOW Current 1875 1875 150 CLK CLK 1875 150 0.5 -150 0.5 -150 A 0.5 -150 NOTE: 100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 7. Input and output parameters vary 1:1 with VCC. VEE can vary + 0.925 V to -0.5 V. 8. All loading with 50 to VCC-2.0 V. 9. Single ended input operation is limited VCC ≥ 3.0 V in LVPECL mode. 10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. LVNECL DC CHARACTERISTICS VCC = 0.0 V; VEE = -3.8 V to -2.375 V (Note 11) -40 °C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 100 125 150 104 130 156 112 140 168 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 12) -1 145 -1020 -895 -1 145 -1020 -895 -1 145 -1020 -895 mV VOL Output LOW Voltage (Note 12) -1945 -1820 -1600 -1945 -1820 -1600 -1945 -1820 -1600 mV VIH Input HIGH Voltage (Single Ended) -1 165 -880 -1 165 -880 -1 165 -880 mV VIL Input LOW Voltage (Single Ended) -1945 -1600 -1945 -1600 -1945 -1600 mV VBB Output Reference Voltage (Note 13) -1525 -1325 -1525 -1325 -1525 -1325 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 14) (Figure 5) 0.0 V IIH Input HIGH Current 150 A IIL Input LOW Current -1425 VEE + 1.2 0.0 VEE + 1.2 150 CLK CLK 0.5 -150 -1425 0.0 VEE + 1.2 150 0.5 -150 NOTE: -1425 0.5 -150 A 100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 11. Input and output parameters vary 1:1 with VCC. 12. All loading with 50 to VCC - 2.0 V. 13. Single ended input operation is limited VEE ≤ -3.0V in NECL mode. 14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 5 NB100LVEP222 AC CHARACTERISTICS VCC = 2.375 to 3.8 V; VEE = 0.0 V or VCC = 0.0 V; VEE = -2.375 to -3.8 V (Note 15) -40 °C 25°C Min Typ fout = 50 MHz fout = 0.8 GHz fout = 1.0 GHz 500 550 500 600 650 650 tPLH tPHL Propagation Delay (Differential Configuration) CLKx-Q X MR-Q XX 650 700 800 900 900 1200 tskew Within-Device Skew (Note 16) (÷1 Mode) Qa[0:1] Qb[0:2] Qc[0:3] Qd[0:5] 10 10 20 10 - QaN, QbN, QdN - All Outputs Symbol VOpp tskew Min Typ 500 525 425 600 650 650 700 700 875 900 1000 1200 40 40 60 40 10 10 20 10 10 20 40 60 Qa[0:1] Qb[0:2] Qc[0:3] Qd[0:5] 15 15 20 15 - QaN, QbN, QdN - All Outputs Characteristic Differential Output Voltage (Figure 4) Max 85°C Max Min Typ Max 500 500 400 600 650 600 850 700 975 900 1150 1200 40 40 60 40 10 10 20 10 40 40 60 40 10 20 40 60 10 20 40 60 70 70 70 70 10 10 20 10 40 40 50 40 15 10 15 15 70 40 70 70 15 20 70 70 10 20 40 50 15 15 70 70 85 300 85 300 85 300 Unit mV Within-Device Skew (Note 16) (÷2 Mode) ps ps - ps - tskew Device-to-Device Skew (Differential Configuration) (Note 17) ps tJITTER Random Clock Jitter (Figure 4) (RMS) 1 5 1 4 1 5 ps VPP Input Swing (Differential Configuration) (Note 18) (Figure 5) 150 800 1200 150 800 1200 150 800 1200 mV DCO Output Duty Cycle 49.5 50 50.5 49.5 50 50.5 49.5 50 50.5 % tr/tf Output Rise/Fall Time 20%-80% 100 200 300 100 200 300 150 250 350 ps 15. Measured with LVPECL 750 mV source, 50% duty cycle clock source. All outputs loaded with 50 to VCC - 2 V. 16. Skew is measured between outputs under identical transitions and operating conditions. 17. Device-to-Device skew for identical transitions at identical VCC levels. 18. VPP is the differential configuration input voltage swing required to maintain AC characteristics including tPD and device-to-device skew. 10 9.0 800 Q AMP (÷ 2) 700 8.0 7.0 6.0 600 Q AMP (÷ 1) 5.0 500 4.0 400 3.0 2.0 RMS JITTER 300 RMS JITTER (ps) VOPP, OUTPUT VOLTAGE (mV) 900 1.0 200 0.1 0.5 1.0 1.5 0 2.0 INPUT FREQUENCY (GHz) Figure 4. Output Voltage (VOPP) versus Input Frequency and Random Clock Jitter (tJITTER) @ 25C http://onsemi.com 6 NB100LVEP222 VCC(LVPECL) VIH(DIFF) VIHCMR VPP VIL(DIFF) VEE Figure 5. LVPECL Differential Input Levels Q D Driver Device Receiver Device D Q 50 50 VTT VTT = VCC - 2.0 V Figure 6. Typical Termination for Output Driver and Device Evaluation (Refer to Application Note AND8020 - Termination of ECL Logic Devices) Resource Reference of Application Notes AN1405 - ECL Clock Distribution Techniques AND8002 - Marking and Date Codes AND8009 - ECLinPS Plus Spice I/O Model Kit AND8020 - Termination of ECL Logic Devices AND8066 - Interfacing with ECLinPS For an updated list of Application Notes, please see our website at http://onsemi.com. http://onsemi.com 7 NB100LVEP222 APPLICATIONS INFORMATION Using the thermally enhanced package of the NB100LVEP222 The NB100LVEP222 uses a thermally enhanced 52-lead LQFP package. The package is molded so that a portion of the leadframe is exposed at the surface of the package bottom side. This exposed metal pad will provide the low thermal impedance that supports the power consumption of the NB100LVEP222 high-speed bipolar integrated circuit and will ease the power management task for the system design. In multilayer board designs, a thermal land pattern on the printed circuit board and thermal vias are recommended to maximize both the removal of heat from the package and electrical performance of the NB100LVEP222. The size of the land pattern can be larger, smaller, or even take on a different shape than the exposed pad on the package. However, the solderable area should be at least the same size and shape as the exposed pad on the package. Direct soldering of the exposed pad to the thermal land will provide an efficient thermal conduit. The thermal vias will connect the exposed pad of the package to internal copper planes of the board. The number of vias, spacing, via diameters and land pattern design depend on the application and the amount of heat to be removed from the package. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. The recommended thermal land design for NB100LVEP222 applications on multi-layer boards comprises a 4 X 4 thermal via array using a 1.2 mm pitch as shown in Figure 7 providing an efficient heat removal path. supply enough solder paste to fill those vias and not starve the solder joints. The attachment process for the exposed pad package is equivalent to standard surface mount packages. Figure 8, “Recommended solder mask openings”, shows a recommended solder mask opening with respect to a 4 X 4 thermal via array. Because a large solder mask opening may result in a poor rework release, the opening should be subdivided as shown in Figure 8. For the nominal package standoff of 0.1 mm, a stencil thickness of 5 to 8 mils should be considered. All Units mm 0.2 1.0 1.0 4.6 0.2 4.6 Thermal Via Array (4 X 4) 1.2 mm Pitch 0.3 mm Diameter Exposed Pad Land Pattern Figure 8. Recommended Solder Mask Openings All Units mm Proper thermal management is critical for reliable system operation. This is especially true for high-fanout and high output drive capability products. For thermal system analysis and junction temperature calculation the thermal resistance parameters of the package is provided: 4.6 Table 1. Thermal Resistance * 4.6 Thermal Via Array (4 X 4) 1.2 mm Pitch 0.3 mm Diameter LFPM JA C/W JC C/W 0 35.6 3.2 100 32.8 4.9 500 30.0 6.4 * Junction to ambient and Junction to board, four-conductor layer test board (2S2P) per JESD 51-8 These recommendations are to be used as a guideline, only. It is therefore recommended that users employ sufficient thermal modeling analysis to assist in applying the general recommendations to their particular application to assure adequate thermal performance. The exposed pad of the NB100LVEP222 package is electrically shorted to the substrate of the integrated circuit and VEE. The thermal land should be electrically connected to VEE. Exposed Pad Land Pattern Figure 7. Recommended Thermal Land Pattern The via diameter should be approximately 0.3 mm with 1 oz. copper via barrel plating. Solder wicking inside the via may result in voiding during the solder process and must be avoided. If the copper plating does not plug the vias, stencil print solder paste onto the printed circuit pad. This will http://onsemi.com 8 NB100LVEP222 PACKAGE DIMENSIONS LQFP 52 LEAD EXPOSED PAD PACKAGE CASE 848H-01 ISSUE A 4 PL M M/2 -Z- 0.20 (0.008) T X−Y Z AJ AJ 52 40 39 1 PLATING -X- ÇÇÇÇ ÉÉÉÉ ÉÉÉÉ ÇÇÇÇ AA -Y- L B J AB B/2 L/2 D REF 13 27 0.08 (0.003) 26 14 M Y T−U DETAIL AJ-AJ A/2 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MM. 3. DATUM PLANE E" IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING PLANE. 4. DATUM X", Y" AND Z" TO BE DETERMINED AT DATUM PLANE DATUM E". BASE METAL 5. DIMENSIONS M AND L TO BE DETERMINED AT SEATING PLANE DATUM T". 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLAND E". 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM D DIMENSION BY MORE THAN 0.08 (0.003). DAMBAR CANNOT Z BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003). 0.20 (0.008) E X−Y Z A DIM A B C D F G H J K L M N P R S V W AA AB AC AD AE DETAIL AH -E-T- AG G SEATING PLANE AG 48 PL D 0.10 (0.004) T 52 PL 0.08 (0.003) M T X−Y V Z 0.05 (0.002) R S AC AD EXPOSED PAD 14 26 S C 27 13 W N K P F H AE DETAIL AH 39 1 52 40 VIEW AG-AG http://onsemi.com 9 0.25 GAGE PLANE MILLIMETERS MIN MAX 10.00 BSC 10.00 BSC 1.30 1.50 0.22 0.40 0.45 0.75 0.65 BSC 1.00 REF 0.09 0.20 0.05 0.20 12.00 BSC 12.00 BSC 0.20 REF 0 7 0 −−− −−− 1.70 12 REF 12 REF 0.20 0.35 0.07 0.16 0.08 0.20 4.58 4.78 4.58 4.78 INCHES MIN MAX 0.394 BSC 0.394 BSC 0.051 0.059 0.009 0.016 0.018 0.030 0.026 BSC 0.039 BSC 0.004 0.008 0.002 0.008 0.472 BSC 0.472 BSC 0.008 REF 0 7 0 −−− −−− 0.067 12 REF 12 REF 0.008 0.014 0.003 0.006 0.003 0.008 0.180 0.188 0.180 0.188 NB100LVEP222 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: [email protected] JAPAN: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 Email: [email protected] ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. N. American Technical Support: 800-282-9855 Toll Free USA/Canada http://onsemi.com 10 NB100LVEP222/D