MC10EP016, MC100EP016 3.3V / 5VECL 8-Bit Synchronous Binary Up Counter The MC10/100EP016 is a high–speed synchronous, presettable, cascadeable 8–bit binary counter. Architecture and operation are the same as the MC10E016 in the ECLinPS family. The counter features internal feedback to TC gated by the TCLD (Terminal Count Load) pin. When TCLD is LOW (or left open, in which case it is pulled LOW by the internal pulldowns), the TC feedback is disabled, and counting proceeds continuously, with TC going LOW to indicate an all–one state. When TCLD is HIGH, the TC feedback causes the counter to automatically reload upon TC = LOW, thus functioning as a programmable counter. The Qn outputs do not need to be terminated for the count function to operate properly. To minimize noise and power, unused Q outputs should be left unterminated. COUT and COUT provide differential outputs from a single, non–cascaded counter or divider application. COUT and COUT should not be used in cascade configuration. Only TC should be used for a counter or divider cascade chain output. A differential clock input has also been added to improve performance. The 100 Series contains temperature compensation. • 500 ps Typical Propagation Delay • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V • • • • • • • • • • with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = –3.0 V to –5.5 V Open Input Default State http://onsemi.com MARKING DIAGRAM* MCxxx EP016 AWLYYWW LQFP–32 FA SUFFIX CASE 873A 32 1 xxx A WL YY WW = 10 OR 100 = Assembly Location = Wafer Lot = Year = Work Week *For additional information, see Application Note AND8002/D ORDERING INFORMATION Device Package Shipping MC10EP016FA LQFP–32 250 Units/Tray MC10EP016FAR2 LQFP–32 2000 Tape & Reel 8–Bit MC100EP016FA LQFP–32 Differential Clock Input MC100EP016FAR2 LQFP–32 2000 Tape & Reel Safety Clamp on Inputs Internal TC Feedback (Gated) Addition of COUT and COUT 250 Units/Tray VBB Output Fully Synchronous Counting and TC Generation Asynchronous Master Reset Semiconductor Components Industries, LLC, 2002 September, 2002 – Rev. 10 1 Publication Order Number: MC10EP016/D MC10EP016, MC100EP016 VBB CLK CLK P0 24 23 22 21 P1 P2 P3 P4 20 19 18 17 PIN DESCRIPTION 25 PE 16 P5 PIN FUNCTION P0–P7* ECL Parallel Data (Preset) Inputs CE 26 15 P6 Q0–Q7 ECL Data Outputs MR 27 14 P7 CE* ECL Count Enable Control Input VEE 28 Q0 29 MC10EP016 MC100EP016 13 VCC 12 TC PE* ECL Parallel Load Enable Control Input MR* ECL Master Reset CLK*, CLK* ECL Differential Clock TC ECL Terminal Count Output Q1 30 11 COUT Q2 31 10 TCLD* COUT COUT, COUT VCC 32 9 VCC Positive Supply VEE Negative Supply VBB Reference Voltage Output 1 2 3 4 5 6 7 VEE 8 ECL TC–Load Control Input ECL Differential Output * Pins will default LOW when left open. VCC Q3 Q4 Q5 Q6 Q7 TCLD VCC Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. 32–Lead LQFP Pinout (Top View) FUNCTION TABLES CE PE X L L H X X L H H H X X TCLD MR X L H X X X FUNCTION CLK L L L L L H Z Z Z Z ZZ X Load Parallel (Pn to Qn) Continuous Count Count; Load Parallel on TC = LOW Hold Masters Respond, Slaves Hold Reset (Qn : = LOW, TC : = HIGH) ZZ = Clock Pulse (High–to–Low) Z = Clock Pulse (Low–to–High) FUNCTION TABLE Function PE CE MR TCLD CLK P7–P4 P3 P2 P1 P0 Q7–Q4 Q3 Q2 Q1 Q0 TC COUT COUT Load Count L H H H H X L L L L L L L L L X L L L L Z Z Z Z Z H X X X X H X X X X H X X X X L X X X X L X X X X H H H H L H H H H L H H H H L L L H H L L H L H L H H H L H H H H L H L L L H L Load Hold L H H X H H L L L X X X Z Z Z H X X H X X H X X L X X L X X H H H H H H H H H L L L L L L H H H H H H L L L Load on Terminal Count H H H H H H L L L L L L L L L L L L H H H H H H Z Z Z Z Z Z H H H H H H L L L L L L H H H H H H H H H H H H L L L L L L H H H H H H H H H L L H H H H H H L L H H H H L H L H L H L H H L H H H H H L H H H L L H L L L Reset X X H X X X X X X X L L L L L H H L http://onsemi.com 2 MC10EP016, MC100EP016 Q1 Q0 Q7 PE TCLD Q0M MASTER Q0M SLAVE CE Q0 CE CE Q Q1 0 Q2 Q3 Q4 Q5 Q BIT 1 BIT 0 BIT 7 6 P0 P1 P7 MR CLK BITS 2–6 CLK TC 5 VBB COUT COUT VEE Note that this diagram is provided for understanding of logic operation only. It should not be used for propagation delays as many gate functions are achieved internally without incurring a full gate delay. Figure 2. 8-BIT Binary Counter Logic Diagram ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor ESD Protection N/A Human Body Model Machine Model Charged Device Model Moisture Sensitivity (Note 1) Flammability Rating > 2 kV > 100 V > 2 kV Level 2 Oxygen Index: 28 to 34 Transistor Count UL 94 V–0 @ 0.125 in 897 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. http://onsemi.com 3 MC10EP016, MC100EP016 MAXIMUM RATINGS (Note 2) Symbol Parameter Condition 1 Condition 2 Rating Units VCC PECL Mode Power Supply VEE = 0 V 6 V VEE NECL Mode Power Supply VCC = 0 V –6 V VI Input PECL Mode In ut Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 –6 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ± 0.5 mA TA Operating Temperature Range –40 to +85 °C Tstg Storage Temperature Range –65 to +150 °C θJA Thermal Resistance (Junction–to–Ambient) 0 LFPM 500 LFPM 32 LQFP 32 LQFP 80 55 °C/W °C/W θJC Thermal Resistance (Junction–to–Case) std bd 32 LQFP 12 to 17 °C/W 265 °C VI VCC VI VEE Tsol Wave Solder <2 to 3 sec @ 248°C 2. Maximum Ratings are those values beyond which device damage may occur. 10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3) –40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit IEE Power Supply Current 120 160 200 120 160 200 120 160 200 mA VOH Output HIGH Voltage (Note 4) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mV VOL Output LOW Voltage (Note 4) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mV VIH Input HIGH Voltage (Single–Ended) 2090 2415 2155 2480 2215 2540 mV VIL Input LOW Voltage (Single–Ended) 1365 1690 1460 1755 1490 1815 mV VBB Output Voltage Reference 1790 1990 1855 2055 1915 2115 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 5) 3.3 2.0 3.3 2.0 3.3 V IIH Input HIGH Current 150 µA IIL Input LOW Current 1890 2.0 1955 150 0.5 2015 150 0.5 µA 0.5 NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to –2.2 V. 4. All loading with 50 to VCC–2.0 volts. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6) –40°C Symbol Characteristic Min Typ 25°C Max Min Typ 85°C Max Min Typ Max Unit IEE Power Supply Current (Note 7) 120 160 200 120 160 200 120 160 200 mA VOH Output HIGH Voltage (Note 8) 3865 3990 4115 3930 4055 4180 3990 4115 4240 mV VOL Output LOW Voltage (Note 8) 3065 3190 3315 3130 3255 3380 3190 3315 3440 mV VIH Input HIGH Voltage (Single–Ended) 3790 4115 3855 4180 3915 4240 mV VIL Input LOW Voltage (Single–Ended) 3065 3390 3130 3455 3190 3515 mV VBB Output Voltage Reference 3490 3690 3555 3755 3615 3815 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 9) 5.0 2.0 5.0 2.0 5.0 V IIH Input HIGH Current 150 µA IIL Input LOW Current 3590 2.0 150 0.5 3655 150 0.5 0.5 3715 µA NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to –0.5 V. 7. Required 500 lfpm air flow when using +5 V power supply. For (VCC – VEE) >3.3 V, 5 to 10 in line with VEE required for maximum thermal protection at elevated temperatures. Recommend VCC–VEE operation at 3.3 V. 8. All loading with 50 to VCC–2.0 volts. 9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 MC10EP016, MC100EP016 10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = –5.5 V to –3.0 V (Note 10) –40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit IEE Power Supply Current (Note 11) 120 160 200 120 160 200 120 160 200 mA VOH Output HIGH Voltage (Note 12) –1135 –1010 –885 –1070 –945 –820 –1010 –885 –760 mV VOL Output LOW Voltage (Note 12) –1935 –1810 –1685 –1870 –1745 –1620 –1810 –1685 –1560 mV VIH Input HIGH Voltage (Single–Ended) –1210 –885 –1145 –820 –1085 –760 mV VIL Input LOW Voltage (Single–Ended) –1935 –1610 –1870 –1545 –1810 –1485 mV VBB Output Voltage Reference –1510 –1310 –1445 –1245 –1385 –1185 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 13) 0.0 V IIH Input HIGH Current 150 µA –1410 VEE+2.0 0.0 –1345 VEE+2.0 150 0.0 –1285 VEE+2.0 150 IIL Input LOW Current 0.5 0.5 0.5 µA NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 10. Input and output parameters vary 1:1 with VCC. 11. Required 500 lfpm air flow when using –5 V power supply. For (VCC – VEE) >3.3 V, 5 to 10 in line with VEE required for maximum thermal protection at elevated temperatures. Recommend VCC–VEE operation at 3.3 V. 12. All loading with 50 to VCC–2.0 volts. 13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 14) Symbol Characteristic Min –40°C Typ Max Min 25°C Typ Max Min 85°C Typ Max Unit IEE Power Supply Current 120 160 200 120 160 200 120 160 200 mA VOH Output HIGH Voltage (Note 15) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV VOL Output LOW Voltage (Note 15) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV VIH Input HIGH Voltage (Single–Ended) 2075 2420 2075 2420 2075 2420 mV VIL Input LOW Voltage (Single–Ended) 1355 1675 1355 1675 1355 1675 mV VBB Output Voltage Reference 1775 1975 1775 1975 1775 1975 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 16) 3.3 2.0 3.3 2.0 3.3 V IIH Input HIGH Current 150 µA IIL Input LOW Current 1875 2.0 1875 150 0.5 1875 150 0.5 µA 0.5 NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 14. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to –2.2 V. 15. All loading with 50 to VCC–2.0 volts. 16. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 17) –40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit IEE Power Supply Current (Note 18) 120 160 200 120 160 200 120 160 200 mA VOH Output HIGH Voltage (Note 19) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mV VOL Output LOW Voltage (Note 19) 3055 3180 3305 3055 3180 3305 3055 3180 3305 mV VIH Input HIGH Voltage (Single–Ended) 3775 4120 3775 4120 3775 4120 mV VIL Input LOW Voltage (Single–Ended) 3055 3375 3055 3375 3055 3375 mV VBB Output Voltage Reference 3475 3675 3475 3675 3475 3675 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 20) 5.0 2.0 5.0 2.0 5.0 V IIH Input HIGH Current 150 µA IIL Input LOW Current 3575 2.0 150 0.5 3575 150 0.5 0.5 3575 µA NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 17. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to –0.5 V. 18. Required 500 lfpm air flow when using +5 V power supply. For (VCC – VEE) >3.3 V, 5 to 10 in line with VEE required for maximum thermal protection at elevated temperatures. Recommend VCC–VEE operation at 3.3 V. 19. All loading with 50 to VCC–2.0 volts. 20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 5 MC10EP016, MC100EP016 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = –5.5 V to –3.0 V (Note 21) –40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 120 160 200 120 160 200 120 160 200 mA IEE Power Supply Current (Note 22) VOH Output HIGH Voltage (Note 23) –1145 –1020 –895 –1145 –1020 –895 –1145 –1020 –895 mV VOL Output LOW Voltage (Note 23) –1945 –1820 –1695 –1945 –1820 –1695 –1945 –1820 –1695 mV VIH Input HIGH Voltage (Single–Ended) –1225 –880 –1225 –880 –1225 –880 mV VIL Input LOW Voltage (Single–Ended) –1945 –1625 –1945 –1625 –1945 –1625 mV VBB Output Voltage Reference –1525 –1325 –1525 –1325 –1525 –1325 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 24) 0.0 V IIH Input HIGH Current 150 µA IIL Input LOW Current –1425 VEE+2.0 0.0 –1425 VEE+2.0 0.0 150 0.5 –1425 VEE+2.0 150 0.5 µA 0.5 NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 21. Input and output parameters vary 1:1 with VCC. 22. Required 500 lfpm air flow when using –5 V power supply. For (VCC – VEE) >3.3 V, 5 to 10 in line with VEE required for maximum thermal protection at elevated temperatures. Recommend VCC–VEE operation at 3.3 V. 23. All loading with 50 to VCC–2.0 volts. 24. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. AC CHARACTERISTICS VEE = –3.0 V to –5.5 V; VCC = 0 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 25) –40°C Symbol fCOUNT Characteristic Min Typ 25°C Max Min Typ 85°C Max Min Typ Max Unit Maximum Frequency >1 > 800 Q, TC COUT/COUT tPLH tPHL Propagation Delay (10) (10) (10) (10) (10) (10) (100) (100) (100) (100) (100) (100) tS >1 > 800 350 400 400 350 450 400 400 450 400 450 450 500 500 500 500 450 550 500 550 590 550 590 600 640 –50 300 300 300 100 500 500 500 –50 300 300 300 100 500 500 500 300 300 350 250 400 300 350 400 350 400 400 450 460 400 420 350 470 400 500 550 500 550 550 600 Setup Time Pn CE PE TCLD 100 500 500 500 tH Hold Time Pn CE PE TCLD 100 500 500 500 tJITTER Clock Random Jitter (RMS >1000 Waveforms) tRR Reset Recovery Time 200 80 200 80 200 80 ps tPW Minimum Pulse Width CLK, MR 550 300 550 300 550 300 ps tr tf Output Rise/Fall Times 20% – 80% 120 210 120 220 150 250 8.5 320 400 450 400 400 450 450 480 520 480 520 530 570 560 580 550 510 600 560 630 670 630 670 680 720 –50 300 300 300 100 500 500 500 –50 300 300 300 ps –50 300 300 300 100 500 500 500 –50 300 300 300 ps 2.5 650 600 600 550 700 650 700 750 700 750 800 850 GHz MHz CLK to Q MR to Q CLK to TC MR to TC CLK to COUT MR to COUT CLK to Q MR to Q CLK to TC MR to TC CLK to COUT MR to COUT 2.6 600 500 550 450 650 550 650 700 650 700 750 800 >1 > 800 8.0 320 25. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC–2.0 V. http://onsemi.com 6 2.5 700 700 700 600 800 700 780 820 780 820 880 920 8.0 450 ps ps ps MC10EP016, MC100EP016 Applications Information Cascading Multiple EP016 Devices For applications which call for larger than 8-bit counters multiple EP016s can be tied together to achieve very wide bit width counters. The active low terminal count (TC) output and count enable input (CE) greatly facilitate the cascading of EP016 devices. Two EP016s can be cascaded without the need for external gating, however for counters wider than 16 bits external OR gates are necessary for cascade implementations. Figure 3 below pictorially illustrates the cascading of 4 EP016s to build a 32-bit high frequency counter. Note the EP01 gates used to OR the terminal count outputs of the lower order EP016s to control the counting operation of the higher order bits. When the terminal count of the preceding device (or devices) goes low (the counter reaches an all 1s state) the more significant EP016 is set in its count mode and will count one binary digit upon the next positive clock transition. In addition, the preceding devices will also count one bit thus sending their terminal count outputs back to a high state disabling the count operation of the more significant counters and placing them back into hold modes. Therefore, for an EP016 in the chain to count, all of the lower order terminal count outputs must be in the low state. The bit width of the counter can be increased or decreased by simply adding or subtracting EP016 devices from Figure 3 and maintaining the logic pattern illustrated in the same figure. The maximum frequency of operation for a cascaded counter chain is set by the propagation delay of the TC output, the necessary setup time of the CE input, and the propagation delay through the OR gate controlling it (for 16–bit counters the limitation is only the TC propagation delay and the CE setup time). Figure 3 shows EP01 gates used to control the count enable inputs, however, if the frequency of operation is slow enough, a LVECL OR gate can be used. Using the worst case guarantees for these parameters. LOAD Q0 to Q7 LO CE PE EP016 LSB CLK CLK TC Q0 to Q7 PE CE PE CE EP016 CLK CLK CE EP016 CLK CLK TC PE EP016 MSB CLK CLK TC TC EP01 EP01 P0 to P7 Q0 to Q7 Q0 to Q7 P0 to P7 P0 to P7 P0 to P7 CLK CLK Figure 3. 32-Bit Cascaded EP016 Counter TCLD pin (load on terminal count) when asserted reloads the data present at the parallel input pin (Pn’s) upon reaching terminal count (an all 1s state on the outputs). Because this feedback is built internal to the chip, the programmable division operation will run at very nearly the same frequency as the maximum counting frequency of the device. Figure 4 below illustrates the input conditions necessary for utilizing the EP016 as a programmable divider set up to divide by 113. Note that this assumes the trace delay between the TC outputs and the CE inputs are negligible. If this is not the case estimates of these delays need to be added to the calculations. Programmable Divider The EP016 has been designed with a control pin which makes it ideal for use as an 8-bit programmable divider. The http://onsemi.com 7 MC10EP016, MC100EP016 Applications Information (continued) H L L P7 P6 P5 H PE L CE H L H H H H P4 P3 P2 P1 P0 Table 1. Preset Values for Various Divide Ratios Ratio P7 P6 P5 P4 P3 P2 P1 P0 2 3 4 5 • • 112 113 114 • • 254 255 256 H H H H • • H H H • • L L L H H H H • • L L L • • L L L H H H H • • L L L • • L L L H H H H • • H L L • • L L L H H H H • • L H H • • L L L H H H L • • L H H • • L L L H L L H • • L H H • • H L L L H L H • • L H L • • L H L TC TCLD COUT CLK CLK Q7 Q6 Q5 COUT Q4 Q3 Q2 Q1 Q0 Figure 4. Mod 2 to 256 Programmable Divider To determine what value to load into the device to accomplish the desired division, the designer simply subtracts the binary equivalent of the desired divide ratio from the binary value for 256. As an example for a divide ratio of 113: Pn’s = 256 – 113 = 8F16 = 1000 1111 where: P0 = LSB and P7 = MSB Forcing this input condition as per the setup in Figure 4 will result in the waveforms of Figure 5. Note that the TC output is used as the divide output and the pulse duration is equal to a full clock period. For even divide ratios, twice the desired divide ratio can be loaded into the EP016 and the TC output can feed the clock input of a toggle flip flop to create a signal divided as desired with a 50% duty cycle. Load 1001 0000 Preset Data Inputs Divide de A single EP016 can be used to divide by any ratio from 2 to 256 inclusive. If divide ratios of greater than 256 are needed multiple EP016s can be cascaded in a manner similar to that already discussed. When EP016s are cascaded to build larger dividers the TCLD pin will no longer provide a means for loading on terminal count. Because one does not want to reload the counters until all of the devices in the chain have reached terminal count, external gating of the TC pins must be used for multiple EP016 divider chains. 1001 0001 1111 1100 ••• 1111 1101 1111 1110 1111 1111 CLK ••• PE ••• TC DIVIDE BY 113 Figure 5. Divide by 113 EP016 Programmable Divider Waveforms http://onsemi.com 8 Load MC10EP016, MC100EP016 Applications Information (continued) EP01 Q0 to Q7 LO CE PE EP016 LSB CLK CLK TC Q0 to Q7 CE Q0 to Q7 PE CE EP016 CLK CLK PE CE EP016 CLK CLK TC PE EP016 MSB CLK CLK TC EP01 P0 to P7 Q0 to Q7 TC EP01 P0 to P7 P0 to P7 P0 to P7 CLK CLK Figure 6. 32-Bit Cascaded EP016 Programmable Divider Maximizing EP016 Count Frequency Figure 6 shows a typical block diagram of a 32-bit divider chain. Once again to maximize the frequency of operation EP01 OR gates were used. For lower frequency applications a slower OR gate could replace the EP01. Note that for a 16-bit divider the OR function feeding the PE (program enable) input CANNOT be replaced by a wire OR tie as the TC output of the least significant EP016 must also feed the CE input of the most significant EP016. If the two TC outputs were OR tied the cascaded count operation would not operate properly. Because in the cascaded form the PE feedback is external and requires external gating, the maximum frequency of operation will be significantly less than the same operation in a single device. The EP016 device produces 9 fast transitioning single–ended outputs, thus VCC noise can become significant in situations where all of the outputs switch simultaneously in the same direction. This VCC noise can negatively impact the maximum frequency of operation of the device. Since the device does not need to have the Q outputs terminated to count properly, it is recommended that if the outputs are not going to be used in the rest of the system they should be left unterminated. In addition, if only a subset of the Q outputs are used in the system only those outputs should be terminated. Not terminating the unused outputs will not only cut down the VCC noise generated but will also save in total system power dissipation. Following these guidelines will allow designers to either be more aggressive in their designs or provide them with an extra margin to the published data book specifications. http://onsemi.com 9 MC10EP016, MC100EP016 Q D Receiver Device Driver Device Q D 50 50 VTT VTT = VCC – 2.0 V Figure 7. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 – Termination of ECL Logic Devices.) Resource Reference of Application Notes AN1404 – ECLinPS Circuit Performance at Non–Standard VIH Levels AN1405 – ECL Clock Distribution Techniques AN1406 – Designing with PECL (ECL at +5.0 V) AN1504 – Metastability and the ECLinPS Family AN1568 – Interfacing Between LVDS and ECL AN1650 – Using Wire–OR Ties in ECLinPS Designs AN1672 – The ECL Translator Guide AND8001 – Odd Number Counters Design AND8002 – Marking and Date Codes AND8009 – ECLinPS Plus Spice I/O Model Kit AND8020 – Termination of ECL Logic Devices For an updated list of Application Notes, please see our website at http://onsemi.com. http://onsemi.com 10 MC10EP016, MC100EP016 PACKAGE DIMENSIONS A 32 –T–, –U–, –Z– LQFP FA SUFFIX 32–LEAD PLASTIC PACKAGE CASE 873A–02 ISSUE A 4X A1 0.20 (0.008) AB T-U Z 25 1 –U– –T– B V AE P B1 DETAIL Y 17 8 AE DETAIL Y 9 4X –Z– 9 V1 0.20 (0.008) AC T-U Z S1 S DETAIL AD G –AB– 0.10 (0.004) AC AC T-U Z –AC– BASE METAL ÉÉ ÉÉ ÉÉ ÉÉ F 8X M R M N D J 0.20 (0.008) SEATING PLANE SECTION AE–AE W K X DETAIL AD Q GAUGE PLANE H 0.250 (0.010) C E http://onsemi.com 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12 REF 0.090 0.160 0.400 BSC 1 5 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12 REF 0.004 0.006 0.016 BSC 1 5 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF MC10EP016, MC100EP016 ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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