VR4131 VR Series 64-Bit MIPS® RISC Microprocessor Description The VR4131 is the newest member of NEC’s VR Series™ product line. This high-performance 64-bit RISC microprocessor employing the MIPS I, II, III, and MIPS16 instruction sets delivers 1545 MIPS per watt, one of the highest-performance, lowest power ratios currently available. In addition to an ultra-low-power-consuming VR4130 CPU core, the device has cache memory, two-way superscalar pipeline, memory management unit, and peripherals including a DMA interface, serial interface, IrDA® interface, and real-time clock, among others. The VR4131 also has a 32-bit external memory bus and supports a PCI bus interface for external devices. Specifications • High performance/low power ratio of 1545 MIPS per watt • Low power consumption – 220 mW at 200 MHz (typical) – 275 mW at 250 MHz (typical) • High-performance operation – 340 Dhrystone MIPS at 200 MHz – 425 Dhrystone MIPS at 250 MHz Applications • • • • • • Supply voltage: 1.5 V (internal) and 3.3 V (external) • 224-pin FPBGA (16 mm x 16 mm) • Pin-compatible with NEC’s VR4122 (except N-wire) • Full industrial -40˚C to +85˚C ambient operating temperature range Storage systems Wireless LAN access points Network interface cards (NICs) Server farms Information appliances – Portable Internet appliances – Pocket PCs – Cellular telephones Block Diagram 32.768 kHz 18.432 kHz OSB OSB VRC 4173 Touch Panel LCD Panel PLL RTC GIU ICU LED PMU CSI CMU DSIU DCU SIU VR 4130 CPU Core PC Card LCDC PCIU SDRAMU BCU DMAAU VR 4131 ROM/ Flash Memory FIR 48 MHz IR Driver 01RC-0138B (5/01) SDRAM RS-232-C Driver Features CPU • • • • 64-bit MIPS RISC CPU core (VR 4130 equivalent) Two-way superscalar pipeline Internal 64-bit data processing Big and little endian modes Powerful MIPS Instructions • • • • MIPS I, II, III instruction sets (without FPU instructions) MIPS16 instruction set High-speed product/sum instructions Multiply-add instruction for product-sum operation of 32 x 32 + 64 bits with one clock Clocks • • • • External clock input: 32.768 kHz Internal CPU core and peripheral unit operation: 18.432 MHz IrDA interface: 48 MHz Programmable clock management for each on-chip peripheral Power Management Modes • Full speed: normal operation with all clocks functional • Standby: internal clocks stop except for timer or interrupt-related clocks • Suspend: bus clock and internal clocks stop except for timer or interruptrelated clocks • eXsuspend: same as Suspend mode, except that can turn off the internal PLL • Hibernate: clocks generated by the CPU core stop function Memory • • • • • On-chip two-way set associative cache: 16 KB instruction and 16 KB data Synchronous DRAM interface with access at 100 MHz Memory controller for ROM, synchronous DRAM, and flash memory Independent ROM and RAM with 16-/32-bit bus width Cache locking for critical code execution Peripherals • • • • • • • • • • 32-bit PCI version 2.1 interface operating at 33 MHz Fast IR processing in compliance with IrDA specification 1.1 DMA controller Interrupt controller General-purpose I/O ports Two-channel 16550-compatible serial interface Serial interface Serial debugging interfaces Synchronous three-line serial clock Real-time clock VR4131 64-Bit MIPS® RISC Microprocessor Ordering Information Part Number Package µPD30131F1 224-pin FPGA VR4131 64-Bit MIPS® RISC Microprocessor The information in this document is current as of October 2001. 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