Preliminary HY5V52CF 4 Banks x 2M x 32Bit Synchronous DRAM DESCRIPTION The Hynix HY5V52CF is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY5V52CF is organized as 4banks of 2,097,152x32. HY5V52CF is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.) FEATURES • JEDEC standard 3.3V power supply • Auto refresh and self refresh • All device pins are compatible with LVTTL interface • 4096 refresh cycles / 64ms • 90Ball FBGA with 0.8mm of pin pitch • Programmable Burst Length and Burst Type • All inputs and outputs referenced to positive edge of system clock • Data mask function by DQM0,1,2 and 3 • Internal four banks operation - 1, 2, 4, 8 or full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst • Programmable CAS Latency ; 2, 3 Clocks • Burst Read Single Write operation ORDERING INFORMATION Part No. Clock Frequency Organization Interface Package HY5V52(L)F-8 125MHz 4Banks x 2Mbits x32 LVTTL 90Ball FBGA HY5V52(L)F-P 100MHz 4Banks x 2Mbits x32 LVTTL 90Ball FBGA HY5V52(L)F-S 100MHz 4Banks x 2Mbits x32 LVTTL 90Ball FBGA This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.2/Jun 02 HY5V52CF Ball CONFIGURATION 1 2 3 4 5 6 7 8 9 D Q 26 D Q 24 VSS VDD D Q 23 D Q 21 D Q 28 VDDQ VSSQ VDDQ VSSQ D Q 19 VSSQ D Q 27 D Q 25 D Q 22 D Q 20 VDDQ VSSQ D Q 29 D Q 30 D Q 17 D Q 18 VDDQ VDDQ D Q 31 NC NC D Q 16 VSSQ VSS DQM3 A3 A2 DQM2 VDD A4 A5 A6 A 10 A0 A1 A B C D E F G T o p V ie w H A7 A8 NC NC BA1 A 11 C LK CKE A9 BA0 /C S /R A S DQM1 NC NC /C A S /W E DQM0 VDDQ DQ8 VSS VDD DQ7 VSSQ VSSQ D Q 10 DQ9 DQ6 DQ5 VDDQ VSSQ D Q 12 D Q 14 DQ1 DQ3 VDDQ D Q 11 VDDQ VSSQ VDDQ VSSQ DQ4 D Q 13 D Q 15 VSS VDD DQ0 J K L M N P R DQ2 Ball DESCRIPTION PIN PIN NAME DESCRIPTION CLK Clock The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK. CKE Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh CS Chip Select Enables or disables all inputs except CLK, CKE and DQM BA0, BA1 Bank Address Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity A0 ~ A11 Address Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8 Auto-precharge flag : A10 RAS, CAS, WE Row Address Strobe, Column Address Strobe, Write Enable RAS, CAS and WE define the operation Refer function truth table for details DQM0~3 Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode DQ0 ~ DQ31 Data Input/Output Multiplexed data input / output pin VDD/VSS Power Supply/Ground Power supply for internal circuits and input buffers VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers NC No Connection No connection Rev. 0.2/Jun 02 3 HY5V52CF ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Ambient Temperature TA 0 ~ 70 °C Storage Temperature TSTG -55 ~ 125 °C Voltage on Any Pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD relative to VSS VDD, VDDQ -1.0 ~ 4.6 V Short Circuit Output Current IOS 50 mA Power Dissipation PD 1 W Soldering Temperature ⋅ Time TSOLDER 260 ⋅ 10 °C ⋅ Sec Note : Operation at above absolute maximum rating can adversely affect device reliability DC OPERATING CONDITION (TA=0 to 70°C) Parameter Symbol Min Typ. Max Unit Note 3.135 3.3 3.6 V 1 Power Supply Voltage VDD, VDDQ Input high voltage VIH 2.0 3.0 VDDQ + 0.3 V 1,2 Input low voltage VIL VSSQ - 0.3 0 0.8 V 1,3 Note Note : 1.All voltages are referenced to VSS = 0V 2.VIH (max) is acceptable 5.6V AC pulse width with ≤3ns of duration with no input clamp diodes 3.VIL (min) is acceptable -2.0V AC pulse width with ≤3ns of duration with no input clamp diodes AC OPERATING CONDITION (TA=0 to 70°C, 3.0V ≤VDD ≤3.6V, VSS=0V - Note1) Parameter Symbol Value Unit AC input high / low level voltage VIH / VIL 2.4/0.4 V Vtrip 1.4 V Input rise / fall time tR / tF 1 ns Output timing measurement reference level Voutref 1.4 V CL 30 pF Input timing measurement reference level voltage Output load capacitance for access time measurement 1 Note : 1.Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF) For details, refer to AC/DC output load circuit Rev. 0.2/Jun 02 4 HY5V52CF CAPACITANCE (TA=25°C, f=1MHz, VDD=3.3V) Parameter Pin Input capacitance Data input / output capacitance Symbol Min Max Unit CLK CI1 tbd tbd pF A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS, WE, DQM0~3 CI2 tbd tbd pF DQ0 ~ DQ31 CI/O tbd tbd pF OUTPUT LOAD CIRCUIT Vtt=1.4V Vtt=1.4V RT=500 Ω Output RT=50 Ω Z0 = 50Ω Output 30pF 30pF DC Output Load Circuit AC Output Load Circuit DC CHARACTERISTICS I (DC operating conditions unless otherwise noted) Parameter Symbol Min. Max Unit Note Input leakage current ILI -1 1 uA 1 Output leakage current ILO -1 1 uA 2 Output high voltage VOH 2.4 - V IOH = -2mA Output low voltage VOL - 0.4 V IOL = +2mA Note : 1.VIN = 0 to 3.6V, All other pins are not under test = 0V 2.DOUT is disabled, VOUT=0 to 3.6V Rev. 0.2/Jun 02 5 HY5V52CF DC CHARACTERISTICS II (DC operating conditions unless otherwise noted) speed Parameter Symbol Test Condition -8 -P S tbd tbd tbd Operating Current IDD1 Burst length=1, One bank active tRC ≥ tRC(min), IOL=0mA Precharge Standby Current in power down mode IDD2P CKE ≤ VIL(max), tCK = 10ns tbd IDD2PS CKE ≤ VIL(max), tCK = ∞ tbd IDD2N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 10ns Input signals are changed one time during 2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V tbd IDD2NS CKE ≥ VIH(min), tCK = ∞ Input signals are stable. tbd IDD3P CKE ≤ VIL(max), tCK = 10ns tbd IDD3PS CKE ≤ VIL(max), tCK = ∞ tbd IDD3N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 10ns Input signals are changed one time during 2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V tbd IDD3NS CKE ≥ VIH(min), tCK = ∞ Input signals are stable. tbd Precharge Standby Current in non power down mode Active Standby Current in power down mode Active Standby Current in non power down mode ttCK ≥ tCK(min), IOL=0mA Burst Mode Operating Current IDD4 Auto Refresh Current IDD5 tRC ≥ tRC(min), All banks active Self Refresh Current IDD6 CKE ≤ 0.2V All banks active Unit Note mA 1 mA mA mA mA CL=3 tbd tbd tbd CL=2 - tbd tbd tbd tbd tbd mA 1 mA 2 3 tbd mA tbd 4 Note : 1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open 2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3.HY5V52CF-8/P/S 4.HY5V52CL:F-8/P/S Rev. 0.2/Jun 02 6 HY5V52CF AC CHARACTERISTICS I (AC operating conditions unless otherwise noted) -8 Parameter CAS Latency = 3 tCK3 Max 8 Min Max 10 1000 Min Max 10 1000 -10 Clock high pulse width tCHW 3 - 3 - 3 - ns 1 Clock low pulse width tCLW 3 - 3 - 3 - ns 1 CAS Latency = 3 tAC3 - 6 - 6 - 6 ns CAS Latency = 2 tAC2 - 6 - 6 - 6 ns Data-out hold time tOH 2 - 2 - 2 - ns 3 Data-Input setup time tDS 2 - 2 - 2 - ns 1 Data-Input hold time tDH 1 - 1 - 1 - ns 1 Address setup time tAS 2 - 2 - 2 - ns 1 Address hold time tAH 1 - 1 - 1 - ns 1 CKE setup time tCKS 2 - 2 - 2 - ns 1 CKE hold time tCKH 1 - 1 - 1 - ns 1 Command setup time tCS 2 - 2 - 2 - ns 1 Command hold time tCH 1 - 1 - 1 - ns 1 CLK to data output in low Z-time tOLZ 1 - 1 - 1 - ns CAS Latency = 3 tOHZ3 - 6 - 6 - 6 ns CAS Latency = 2 tOHZ2 - 6 - 6 - 6 ns CLK to data output in high Z-time 10 ns 1000 tCK2 Access time from clock CAS Latency = 2 -S Unit Note Min System clock cycle time -P Symbol 12 ns 2 Note : 1.Assume tR / tF (input rise and fall time ) is 1ns 2.Access times to be measured with input signals of 1v/ns edge rate, 0.8v to 2.0v 3.Data-out hold time to be measured under 30pF load condition, without Vt termination Rev. 0.2/Jun 02 7 HY5V52CF AC CHARACTERISTICS II (AC operating conditions unless otherwise noted) -8 Parameter -P -S Symbol Unit Min Max Min Max Min Max Operation tRC 64 - 70 - 70 - ns Auto Refresh tRRC 64 - 70 - 70 - ns RAS to CAS delay tRCD 20 - 20 - 20 - ns RAS active time tRAS 48 100 K 50 100 K 50 100 K ns RAS precharge time tRP 20 - 20 - 20 - ns RAS to RAS bank active delay tRRD 2 - 20 - 20 - CLK CAS to CAS delay tCCD 1 - 1 - 1 - CLK Write command to data-in delay tWTL 0 - 0 - 0 - CLK Data-in to precharge command tDPL 1 - 1 - 1 - CLK Data-in to active command tDAL 4 - 4 - 4 - CLK DQM to data-out Hi-Z tDQZ 2 - 2 - 2 - CLK DQM to data-in mask tDQM 0 - 0 - 0 - CLK MRS to new command tMRD 2 - 2 - 2 - CLK CAS Latency = 3 tPROZ3 3 - 3 - 3 - CLK CAS Latency = 2 tPROZ2 2 - 2 - 2 - CLK Power down exit time tPDE 1 - 1 - 1 - CLK Self refresh exit time tSRE 1 - 1 - 1 - CLK Refresh Time tREF - 64 - 64 - 64 ms Not e RAS cycle time Precharge to data output Hi-Z 1 Note : 1. A new command can be given tRRC after self refresh exit Rev. 0.2/Jun 02 8 HY5V52CF COMMAND TRUTH TABLE Command A10/ AP CKEn-1 CKEn CS RAS CAS WE DQM Mode Register Set H X L L L L X OP code H X X X No Operation H X X X L H H H Bank Active H X L L H H X H X L H L H X ADDR RA Read L V H Write L H X L H L L X CA Write with Autoprecharge H X L L H L X Precharge selected Bank Burst Stop H DQM H Auto Refresh H H L L L Burst-Read-SingleWRITE H X L L Entry H L L H Exit L H Entry V H Precharge All Banks H X L H H L H X L V X X X V X H X X L L X A9 Pin High (Other Pins OP code) L L H X X X X X MRS Mode X X L H H H H X X X L H H H H X X X L H H H H X X X L V V V L Precharge power down X X Exit Clock Suspend Note V CA Read with Autoprecharge Self Refresh1 BA Entry Exit L H L H X L H X X X X Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high 2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address, Opcode = Operand Code, NOP = No Operation 3. The burst read sigle write mode is entered by programming the write burst mode bit (A9) in the mode register to a logic 1. Rev. 0.2/Jun 02 9 HY5V52CF PACKAGE INFORMATION 90Ball FBGA with 0.8mm of pin pitch ( using ‘Multi Chip Package’ Technology) 1.30 Rev. 0.2/Jun 02 10