HYNIX HY57V643220CT-6

HY57V643220C
4 Banks x 512K x 32Bit Synchronous DRAM
DESCRIPTION
The Hynix HY57V643220C is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the memory applications
which require wide data I/O and high bandwidth. HY57V643220C is organized as 4banks of 524,288x32.
HY57V643220C is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very
high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
•
JEDEC standard 3.3V power supply
•
Auto refresh and self refresh
•
All device pins are compatible with LVTTL interface
•
4096 refresh cycles / 64ms
•
JEDEC standard 400mil 86pin TSOP-II with 0.5mm of
pin pitch
•
Programmable Burst Length and Burst Type
•
All inputs and outputs referenced to positive edge of
system clock
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
•
Data mask function by DQM0,1,2 and 3
•
Programmable CAS Latency ; 2, 3 Clocks
•
Internal four banks operation
•
Burst Read Single Write operation
ORDERING INFORMATION
Part No.
Clock Frequency
HY57V643220C(L)T-47
212MHz
HY57V643220C(L)T-5
200MHz
HY57V643220C(L)T-55
183MHz
HY57V643220C(L)T-6
166MHz
HY57V643220C(L)T-7
143MHz
HY57V643220C(L)T-8
125MHz
HY57V643220C(L)T-P
100MHz
HY57V643220C(L)T-S
100MHz
Power
Organization
Interface
Package
Normal/
Low Power
4Banks x
512Kbits x32
LVTTL
400mil 86pin
TSOP II
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.8/Aug. 02
1
HY57V643220C
PIN CONFIGURATION
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDD
DQM 0
/W E
/C A S
/R A S
/C S
NC
BA0
BA1
A 1 0 /A P
A0
A1
A2
DQM 2
VDD
NC
DQ 16
VSSQ
DQ 17
DQ 18
VDDQ
DQ 19
DQ 20
VSSQ
DQ 21
DQ 22
VDDQ
DQ 23
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
8 6 p in T S O P II
4 0 0 m il x 8 7 5 m il
0 .5 m m p in p itc h
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VSS
DQ 15
VSSQ
DQ 14
DQ 13
VDDQ
DQ 12
DQ 11
VSSQ
DQ 10
DQ9
VDDQ
DQ8
NC
VSS
DQM 1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM 3
VSS
NC
DQ 31
VDDQ
DQ 30
DQ 29
VSSQ
DQ 28
DQ 27
VDDQ
DQ 26
DQ 25
VSSQ
DQ 24
VSS
PIN DESCRIPTION
PIN
PIN NAME
DESCRIPTION
CLK
Clock
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK.
CKE
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
CS
Chip Select
Enables or disables all inputs except CLK, CKE and DQM
BA0, BA1
Bank Address
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
A0 ~ A10
Address
Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS, CAS, WE
Row Address Strobe,
Column Address Strobe,
Write Enable
RAS, CAS and WE define the operation
Refer function truth table for details
DQM0~3
Data Input/Output Mask
Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ31
Data Input/Output
Multiplexed data input / output pin
VDD/VSS
Power Supply/Ground
Power supply for internal circuits and input buffers
VDDQ/VSSQ
Data Output Power/Ground
Power supply for output buffers
NC
No Connection
No connection
Rev. 0.8/Aug. 02
2
HY57V643220C
FUNCTIONAL BLOCK DIAGRAM
512Kbit x 4banks x 32 I/O Synchronous DRAM
Self Refresh Logic
& Timer
Refresh
Counter
512Kx32 Bank 3
CLK
Row Active
Row
Pre
Decoder
512Kx32 Bank 2
CS
Y decoder
A0
A1
DQ1
DQ30
DQ31
Column Add
Counter
Address
Register
Address buffers
Rev. 0.8/Aug. 02
DQ0
I/O Buffer & Logic
Column
Pre
Decoder
Bank Select
A10
BA0
BA1
Memory
Cell
Array
Sense AMP & I/O Gate
Column
Active
X decoder
WE
DQM0
DQM1
DQM2
DQM3
512Kx32 Bank 0
X decoder
CAS
State Machine
RAS
512Kx32 Bank 1
X decoder
X decoder
CKE
Burst
Counter
Mode Register
CAS Latency
Data Out Control
Pipe Line Control
3
HY57V643220C
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Ambient Temperature
TA
0 ~ 70
°C
Storage Temperature
TSTG
-55 ~ 125
°C
Voltage on Any Pin relative to VSS
VIN, VOUT
-1.0 ~ 4.6
V
Voltage on VDD relative to VSS
VDD, VDDQ
-1.0 ~ 4.6
V
Short Circuit Output Current
IOS
50
mA
Power Dissipation
PD
1
W
Soldering Temperature . Time
TSOLDER
260 . 10
°C ⋅ Sec
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITION (TA=0 to 70°C)
Parameter
Symbol
Min
Typ.
Max
Unit
Note
Power Supply Voltage
VDD, VDDQ
3.0
3.3
3.6
V
1,2
Input high voltage
VIH
2.0
3.0
VDDQ + 0.3
V
1,3
Input low voltage
VIL
VSSQ - 0.3
0
0.8
V
1,4
Note
Note :
1.All voltages are referenced to VSS = 0V
2.VDD/VDDQ(min) is 3.15V for HY57V643220C(L)T-47/5/55/6
3.VIH (max) is acceptable 5.6V AC pulse width with ≤3ns of duration with no input clamp diodes
4.VIL (min) is acceptable -2.0V AC pulse width with ≤3ns of duration with no input clamp diodes
AC OPERATING CONDITION (TA=0 to 70°C, 3.0V ≤VDD ≤3.6V, VSS=0V - Note1)
Parameter
Symbol
Value
Unit
AC input high / low level voltage
VIH / VIL
2.4/0.4
V
Vtrip
1.4
V
Input rise / fall time
tR / tF
1
ns
Output timing measurement reference level
Voutref
1.4
V
CL
30
pF
Input timing measurement reference level voltage
Output load capacitance for access time measurement
2
Note :
1.3.15V ≤VDD ≤3.6V is applied for HY57V643220C(L)T-47/5/55/6
2.Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF)
For details, refer to AC/DC output load circuit
Rev. 0.8/Aug. 02
4
HY57V643220C
CAPACITANCE (TA=25×C, f=1MHz, VDD=3.3V)
Parameter
Pin
Input capacitance
Data input / output capacitance
Symbol
Min
Max
Unit
CLK
CI1
2.5
3.5
pF
A0 ~ A10, BA0, BA1, CKE, CS, RAS,
CAS, WE, DQM0~3
CI2
2.5
3.8
pF
DQ0 ~ DQ31
CI/O
4
6.5
pF
OUTPUT LOAD CIRCUIT
Vtt=1.4V
Vtt=1.4V
RT=500 Ω
Output
RT=50 Ω
Z0 = 50Ω
Output
30pF
30pF
DC Output Load Circuit
AC Output Load Circuit
DC CHARACTERISTICS I (DC operating conditions unless otherwise noted)
Parameter
Symbol
Min.
Max
Unit
Note
Input leakage current
ILI
-1
1
uA
1
Output leakage current
ILO
-1
1
uA
2
Output high voltage
VOH
2.4
-
V
IOH = -2mA
Output low voltage
VOL
-
0.4
V
IOL = +2mA
Note :
1.VIN = 0 to 3.6V, All other pins are not under test = 0V
2.DOUT is disabled, VOUT=0 to 3.6V
Rev. 0.8/Aug. 02
5
HY57V643220C
DC CHARACTERISTICS II (DC operating conditions unless otherwise noted)
Speed
Parameter
Symbol
Test Condition
-47
-5
-55
-6
-7
-8
-P
-S
220
200
190
180
170
150
150
150
Operating Current
IDD1
Burst Length=1, One bank active
tRAS ≥tRAS(min), tRP ≥tRP(min),
IOL=0mA
Precharge Standby
Current
in power down mode
IDD2P
CKE ≤VIL(max), tCK = 15ns
IDD2PS
CKE ≤VIL(max), tCK =
IDD2N
CKE ≥VIH(min), CS ≥VIH(min), tCK = 15ns
Input signals are changed one time during
2clks. All other pins ≥VDD-0.2V or ≤0.2V
15
IDD2NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
10
IDD3P
CKE ≤VIL(max), tCK = 15ns
3
IDD3PS
CKE ≤VIL(max), tCK =
IDD3N
CKE ≥VIH(min), CS ≥VIH(min), tCK = 15ns
Input signals are changed one time during
2clks. All other pins ≥VDD-0.2V or ≤0.2V
IDD3NS
CKE ≥ VIH(min), tCK =
stable
Burst Mode Operating
Current
IDD4
tCK ≥ tCK(min),
tRAS ≥ tRAS(min), IOL=0mA
All banks active
Auto Refresh Current
IDD5
tRRC ≥ tRRC(min), 2 banks active
Self Refresh Current
IDD6
CKE ≤ 0.2V
Precharge Standby
Current
in non power down mode
Active Standby Current
in power down mode
Active Standby Current
in non power down mode
Unit
Note
mA
1
2
mA
∞
2
mA
mA
∞
3
40
mA
∞Input signals are
25
CL=3
290
280
260
240
210
180
180
CL=2
160
160
160
160
160
160
160
260
250
235
220
210
190
210
180
190
mA
1
mA
2
2
3
mA
1
4
Note :
1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3.HY57V643220CT-47/5/55/6/7/8/P/S
4.HY57V643220CLT-47/5/55/6/7/8/P/S
Rev. 0.8/Aug. 02
6
HY57V643220C
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
-47
Parameter
CAS Latency = 3
tCK3
Max
4.7
Min
Max
5
1000
-6
-7
-8
-P
-S
Min
Max
5.5
1000
Max
6
1000
10
Min
Max
7
1000
10
Min
Max
8
1000
10
Min
Max
10
1000
-10
Min
Max
10
1000
10
ns
1000
10
Clock high pulse width
tCHW
1.65
-
2
-
2.25
-
2.5
-
3
-
3
-
3
-
3
-
ns
1
Clock low pulse width
tCLW
1.65
-
2
-
2.25
-
2.5
-
3
-
3
-
3
-
3
-
ns
1
CAS Latency = 3
tAC3
-
4.5
-
4.5
-
5
-
5.5
-
5.5
-
6
-
6
-
6
ns
CAS Latency = 2
tAC2
-
6
-
6
-
6
-
6
-
6
-
6
-
6
-
6
ns
Data-out hold time
tOH
1.5
-
1.5
-
2
-
2
-
2
-
2
-
2
-
2
-
ns
3
Data-Input setup time
tDS
1.3
-
1.5
-
1.5
-
1.5
-
1.75
-
2
-
2
-
2
-
ns
1
Data-Input hold time
tDH
0.8
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
ns
1
Address setup time
tAS
1.3
-
1.5
-
1.5
-
1.5
-
1.75
-
2
-
2
-
2
-
ns
1
Address hold time
tAH
0.8
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
ns
1
CKE setup time
tCKS
1.3
-
1.5
-
1.5
-
1.5
-
1.75
-
2
-
2
-
2
-
ns
1
CKE hold time
tCKH
0.8
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
ns
1
Command setup time
tCS
1.3
-
1.5
-
1.5
-
1.5
-
1.75
-
2
-
2
-
2
-
ns
1
Command hold time
tCH
0.8
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
ns
1
CLK to data output in low Z-time
tOLZ
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
ns
CAS Latency = 3
tOHZ3
-
4
-
4.5
-
5
-
5.5
-
5.5
-
6
-
6
-
6
ns
CAS Latency = 2
tOHZ2
-
6
-
6
-
6
-
6
-
6
-
6
-
6
-
6
ns
CLK to data output
in high Z-time
10
Min
tCK2
Access time from
clock
CAS Latency = 2
-55
Unit Note
Min
System clock
cycle time
-5
Symbol
12
ns
2
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate, 0.8v to 2.0v
3.Data-out hold time to be measured under 30pF load condition, without Vt termination
Rev. 0.8/Aug. 02
7
HY57V643220C
AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
-47
Parameter
-5
-55
-6
-7
-8
-P
-S
Symbol
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Operation
tRC
51.7
-
55
-
55
-
60
-
63
-
64
-
70
-
70
-
ns
Auto Refresh
tRRC
51.7
-
55
-
55
-
60
-
63
-
64
-
70
-
70
-
ns
RAS to CAS delay
tRCD
14.1
-
15
-
16.5
-
18
-
20
-
20
-
20
-
20
-
ns
RAS active time
tRAS
37.6
100K
38.7
100
K
38.7
100
K
42
100
K
42
100
K
48
100
K
50
100
K
50
100
K
ns
RAS precharge time
tRP
14.1
-
15
-
16.5
-
18
-
20
-
20
-
20
-
20
-
ns
RAS to RAS bank active delay
tRRD
2
-
2
-
2
-
2
-
2
-
2
-
2
-
2
-
CLK
CAS to CAS delay
tCCD
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
Write command to data-in delay
tWTL
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
CLK
Data-in to precharge command
tDPL
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
Data-in to active command
tDAL
4
-
4
-
4
-
4
-
4
-
4
-
4
-
4
-
CLK
DQM to data-out Hi-Z
tDQZ
2
-
2
-
2
-
2
-
2
-
2
-
2
-
2
-
CLK
DQM to data-in mask
tDQM
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
CLK
MRS to new command
tMRD
2
-
2
-
2
-
2
-
2
-
2
-
2
-
2
-
CLK
CAS Latency = 3 tPROZ3
3
-
3
-
3
-
3
-
3
-
3
-
3
-
3
-
CLK
CAS Latency = 2 tPROZ2
-
-
2
-
2
-
2
-
2
-
2
-
2
-
2
-
CLK
Note
RAS cycle time
Precharge to
data output Hi-Z
Power down exit time
tPDE
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
Self refresh exit time
tSRE
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
Refresh Time
tREF
-
64
-
64
-
64
-
64
-
64
-
64
-
64
-
64
ms
1
Note :
1. A new command can be given tRRC after self refresh exit
Rev. 0.8/Aug. 02
8
HY57V643220C
DEVICE OPERATING OPTION TABLE
HY57V643220C(L)T-47
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
212MHz(4.7ns)
3CLKs
3CLKs
37.6ns
12CLKs
3CLKs
4ns
1.5ns
200MHz(5ns)
3CLKs
3CLKs
38.5ns
11CLKs
3CLKs
4.5ns
1.5ns
183MHz(5.5ns)
3CLKs
3CLKs
38.5ns
10CLKs
3CLKs
5ns
2ns
HY57V643220C(L)T-5
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
200MHz(5ns)
3CLKs
3CLKs
38.5ns
11CLKs
3CLKs
4.5ns
1.5ns
183MHz(5.5ns)
3CLKs
3CLKs
38.5ns
10CLKs
3CLKs
5ns
2ns
166MHz(6ns)
3CLKs
3CLKs
7CLKs
10CLKs
3CLKs
5.5ns
2ns
tRCD
tRAS
tRC
tRP
tAC
tOH
HY57V643220C(L)T-55
CAS Latency
183MHz(5.5ns)
3CLKs
3CLKs
7CLKs
10CLKs
3CLKs
5ns
2ns
166MHz(6ns)
3CLKs
3CLKs
7CLKs
10CLKs
3CLKs
5.5ns
2ns
143MHz(7ns)
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
5.5ns
2ns
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
166MHz(6ns)
3CLKs
3CLKs
7CLKs
10CLKs
3CLKs
5.5ns
2ns
143MHz(7ns)
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
5.5ns
2ns
125MHz(8ns)
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
6ns
2.5ns
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
143MHz(7ns)
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
5.5ns
2ns
125MHz(8ns)
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
6ns
2ns
100MHz(10ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
2ns
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
2ns
HY57V643220C(L)T-6
HY57V643220C(L)T-7
HY57V64322C(L)T-8
125MHz(8ns)
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
6ns
100MHz(10ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
2ns
83MHz(12ns)
2CLKs
2CLKs
4CLKs
6CLKs
2CLKs
6ns
2.5ns
Rev. 0.8/Aug. 02
9
HY57V643220C
HY57V643220C(L)T- P
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
100MHz(10ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
2ns
83MHz(12ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
2.5ns
66MHz(15ns)
2CLKs
2CLKs
4CLKs
6CLKs
2CLKs
6ns
2.5ns
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
100MHz(10ns)
3CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
2ns
83MHz(12ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
2.5ns
66MHz(15ns)
2CLKs
2CLKs
4CLKs
6CLKs
2CLKs
6ns
2.5ns
HY57V643220C(L)T- S
Rev. 0.8/Aug. 02
10
HY57V643220C
COMMAND TRUTH TABLE
A10/
AP
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
Mode Register Set
H
X
L
L
L
L
X
OP code
H
X
X
X
No Operation
H
X
X
X
L
H
H
H
Command
Bank Active
H
X
L
L
H
H
X
H
X
L
H
L
H
X
ADDR
RA
Read
L
V
H
Write
L
H
X
L
H
L
L
X
CA
Write with Autoprecharge
H
X
L
L
H
L
X
Burst Stop
H
DQM
H
Auto Refresh
H
H
L
L
L
Burst-READ-Single-WRITE
H
X
L
L
Entry
H
L
L
H
Exit
L
H
H
X
L
H
H
L
X
L
V
X
X
V
X
H
X
X
L
L
X
A9 Pin High
(Other Pins OP code)
L
L
H
X
X
X
X
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
L
Precharge
power down
H
X
Precharge selected Bank
Entry
V
H
Precharge All Banks
X
X
Exit
Clock
Suspend
Note
V
CA
Read with Autoprecharge
Self Refresh1
BA
Entry
Exit
L
H
L
H
X
L
H
X
X
X
X
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don’t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,
Opcode = Operand Code, NOP = No Operation
Rev. 0.8/Aug. 02
11
HY57V643220C
PACKAGE INFORMATION
400mil 86pin Thin Small Outline Package
Unit : mm(inch)
11.938(0.4700)
11.735(0.4620)
22.327(0.8790)
22.149(0.8720)
10.262(0.4040)
10.058(0.3960)
0.150(0.0059)
0.050(0.0020)
0.50(0.0197)
Rev. 0.8/Aug. 02
0.21(0.008)
0.18(0.007)
1.194(0.0470)
0.991(0.0390)
5deg
0deg
0.597(0.0235)
0.406(0.0160)
0.210(0.0083)
0.120(0.0047)
12