ETC HYM71V73C3201TN-75

32x72 bits
PC133 SDRAM Registered DIMM
with PLL, based on 32Mx4 SDRAM with LVTTL, 4 banks & 4K Refresh
HYM71V73C3201 N-Series
s
DESCRIPTION
The Hyundai HYM71V73C3201 N-Series are 32Mx72bits ECC Synchronous DRAM Modules. The modules are
composed of eighteen 32Mx4bit CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, two 18bits driver ICs in
56pin TSSOP package, one PLL clock driver in 24pin TSSOP package and one 2Kbit EEPROM in 8pin TSSOP package
on a 168pin glass-epoxy printed circuit board. One 0.22uF and one 0.0022uF decoupling capacitors per each SDRAM
are mounted on the PCB.
The HYM71V73C3201 N-Series are Dual In-line Memory Modules suitable for easy interchange and addition of
256Mbytes memory. The HYM71V73C3201 N-Series are offering fully synchronous operation referenced to a positive
edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are
internally pipelined to achieve very high bandwidth. The DIMM /CAS latency in registered mode is one clock later than
the device /CAS latency because of the register.
FEATURES
• PC133/PC100MHz support
• SDRAM internal banks : four banks
• 168pin SDRAM Registered DIMM
• Module bank : one physical bank
• Serial Presence Detect with EEPROM
• Auto refresh and self refresh
• 1.70” (43.18mm) Height PCB with Double Sided
components
• 4096 refresh cycles / 64ms
• Single 3.3 ± 0.3V power supply
• All devices pins are compatible with LVTTL interface
• Data mask function by DQM
• Programmable Burst Length and Burst Type
-. 1, 2, 4, 8 or Full Page for Sequential Burst
-. 1, 2, 4 or 8 for Interleave Burst
• Programmable /CAS Latency : 2, 3 Clocks
ORDERING INFORMATION
PART NO.
MAX.
FREQUENCY
INTERNAL
BANK
REF.
POWER
SDRAM
PACKAGE
PLATING
HYM71V73C3201TN-75
133MHz
4 Banks
4K
Normal
TSOP-II
Gold
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.1/Dec.99
1999 Hyundai MicroElectronics
PC133 SDRAM Registered DIMM
HYM71V73C3201 N-Series
PIN DESCRIPTION
PIN NAME
DESCRIPTION
CK0~CK3
Clock Inputs
The System Clock Input. All other inputs are registered to the
SDRAM on the rising edge of CLK.
CKE0
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM
will be one of the states among power down, suspend or self
refresh.
/S0, /S2
Chip Select
Enables or disables all inputs except CK, CKE and DQM.
BA0, BA1
SDRAM Bank Address
A0~A11
Address Inputs
/RAS
Row Address Strobe
/CAS
Column Address Strobe
/WE
Write Enable
REGE
Register Enable
Register Enable pin which permits the DIMM to operation in
Buffered Mode when REGE input is Low, in Registered Mode
when REGE input is High.
DQM0~DQM7
Data Input/Output Mask
Controls output buffers in read mode and masks input data in
write mode.
DQ0~DQ63
Data Input/Output
Multiplexed data input/output pins
CB0~CB7
ECC Data Input/Output
Error Checking and Correction Bits
VCC
Power Supply (3.3V)
Power supply for internal circuits and input/output buffers
VSS
Ground
Ground
SCL
SPD Clock Input
Serial Presence Detect Clock Input
SDA
SPD Data Input/Output
Serial Presence Detect Data input/output
SA0~SA2
SPD Address Input
Serial Presence Detect Address input
WP
Write Protect for SPD
Write Protect for Serial Presence Detect on DIMM
NC
No Connect
No Connect or Don’ t Use
Rev. 1.1/Dec.99
Select bank to be activated during /RAS activity.
Select bank to be read/written during /CAS activity
Row address : RA0~RA11, Column address : CA0~CA9, CA11
Auto-precharge flag : A10
/RAS define the operation.
Refer to the function truth table for details.
/CAS define the operation.
Refer to the function truth table for details.
/WE define the operation.
Refer to the function truth table for details.
2
PC133 SDRAM Registered DIMM
HYM71V73C3201 N-Series
PIN ASSIGNMENTS
FRONT SIDE
BACK SIDE
FRONT SIDE
BACK SIDE
PIN NO.
NAME
PIN NO.
NAME
PIN NO.
NAME
PIN NO.
NAME
1
VSS
85
VSS
41
VCC
125
*CK1
2
3
DQ0
DQ1
86
87
DQ32
DQ33
42
43
CK0
VSS
126
127
NC
VSS
4
DQ2
88
DQ34
44
NC
128
CKE0
5
DQ3
89
DQ35
45
/S2
129
NC
6
VCC
90
VCC
46
DQM2
130
DQM6
7
8
DQ4
DQ5
91
92
DQ36
DQ37
47
48
DQM3
NC
131
132
DQM7
NC
9
DQ6
93
DQ38
49
VCC
133
VCC
10
DQ7
94
DQ39
50
NC
134
NC
51
NC
135
NC
DQ40
52
53
CB2
CB3
136
137
CB6
CB7
Architecture Key
11
DQ8
95
12
VSS
96
VSS
54
VSS
138
VSS
13
DQ9
97
DQ41
55
DQ16
139
DQ48
14
DQ10
98
DQ42
56
DQ17
140
DQ49
15
16
DQ11
DQ12
99
100
DQ43
DQ44
57
58
DQ18
DQ19
141
142
DQ50
DQ51
17
DQ13
101
DQ45
59
VCC
143
VCC
18
VCC
102
VCC
60
DQ20
144
DQ52
19
DQ14
103
DQ46
61
NC
145
NC
20
21
DQ15
CB0
104
105
DQ47
CB4
62
63
NC
NC
146
147
NC
REGE
22
CB1
106
CB5
64
VSS
148
VSS
23
VSS
107
VSS
65
DQ21
149
DQ53
24
25
NC
NC
108
109
NC
NC
66
67
DQ22
DQ23
150
151
DQ54
DQ55
26
VCC
110
VCC
68
VSS
152
VSS
27
/WE
111
/CAS
69
DQ24
153
DQ56
28
DQM0
112
DQM4
70
DQ25
154
DQ57
29
30
DQM1
/S0
113
114
DQM5
NC
71
72
DQ26
DQ27
155
156
DQ58
DQ59
31
NC
115
/RAS
73
VCC
157
VCC
32
VSS
116
VSS
74
DQ28
158
DQ60
33
A0
117
A1
75
DQ29
159
DQ61
34
35
A2
A4
118
119
A3
A5
76
77
DQ30
DQ31
160
161
DQ62
DQ63
36
A6
120
A7
78
VSS
162
VSS
37
A8
121
A9
79
*CK2
163
*CK3
38
A10/AP
122
BA0
80
NC
164
NC
39
40
BA1
VCC
123
124
A11
VCC
81
82
WP
SDA
165
166
SA0
SA1
83
SCL
167
SA2
84
VCC
168
VCC
Voltage Key
Note : *. CK1~CK3 are connected with termination R/C. (Refer to the Block Diagram.)
Rev. 1.1/Dec.99
3
PC133 SDRAM Registered DIMM
HYM71V73C3201 N-Series
BLOCK DIAGRAM
Note : 1. The serial resistor values of DQs are 10 Ohms.
2. The padding capacitance of termination R/C for CK1~CK3 is 12pF.
Rev. 1.1/Dec.99
4
PC133 SDRAM Registered DIMM
HYM71V73C3201 N-Series
SERIAL PRESENCE DETECT
BYTE
FUNCTION
FUNCTION
VALUE
NUMBER
DESCRIBED
-75
-75
BYTE0
# of Bytes Written into Serial Memory
at Module Manufacturer
128 Bytes
80h
BYTE1
Total # of Bytes of SPD Memory Device
256 Bytes
08h
BYTE2
Fundamental Memory Type
BYTE3
SDRAM
04h
# of Row Addresses on This Assembly
12
0Ch
BYTE4
# of Column Addresses on This Assembly
11
0Bh
BYTE5
# of Module Banks on This Assembly
1 Banks
01h
BYTE6
Data Width of This Assembly
72 Bits
48h
BYTE7
Data Width of This Assembly (Continued)
-
00h
BYTE8
Voltage Interface Standard of This Assembly
LVTTL
01h
BYTE9
SDRAM Cycle Time @ /CAS Latency=3
7.5ns
75h
BYTE10
Access Time from Clock @ /CAS Latency=3
5.4ns
54h
BYTE11
DIMM Configuration Type
ECC
02h
15.625µs
/ Self Refresh Supported
80h
BYTE12
Refresh Rate/Type
BYTE13
Primary SDRAM Width
x4
04h
BYTE14
Error Checking SDRAM Width
x4
04h
BYTE15
Minimum Clock Delay Back to Back Random
Column Address
tCCD = 1 CLK
01h
BYTE16
Burst Lengths Supported
1,2,4,8,Full Page
8Fh
BYTE17
# of Banks on Each SDRAM Device
4 Banks
04h
BYTE18
SDRAM Device Attributes, CAS # Latency
/CAS Latency=2,3
06h
BYTE19
SDRAM Device Attributes, CS # Latency
/CS Latency=0
01h
BYTE20
SDRAM Device Attributes, Write Latency
/WE Latency=0
01h
BYTE21
SDRAM Module Attributes
Registered Buffered Input with PLL
1Fh
BYTE22
SDRAM Device Attributes, General
+/-10% voltage tolerance, Burst
Read Single bit Write, Precharge
All, Auto Precharge, Early RAS
Precharge
0Eh
BYTE23
SDRAM Cycle Time @ /CAS Latency=2
10ns
A0h
BYTE24
Access Time from Clock @ /CAS Latency=2
6ns
60h
BYTE25
SDRAM Cycle Time @ /CAS Latency=1
-
00h
BYTE26
Access Time from Clock @ /CAS Latency=1
-
00h
BYTE27
Minimum Row Precharge Time (tRP)
20ns
14h
BYTE28
Minimum Row Active to Row Active Delay (tRRD)
15ns
0Fh
BYTE29
Minimum /RAS to /CAS Delay (tRCD)
20ns
14h
BYTE30
Minimum /RAS Pulse width (tRAS)
45ns
2Dh
BYTE31
Module Bank Density
BYTE32
Command and Address Signal Input Setup Time
BYTE33
Command and Address Signal Input Hold Time
0.8ns
08h
BYTE34
Data Signal Input Setup Time
1.5ns
15h
BYTE35
Data Signal Input Hold Time
0.8ns
08h
BYTE36
–61
Superset Information (may be used in future)
-
00h
BYTE62
SPD Revision
BYTE63
Checksum for Bytes 0~62
BYTE64
Manufacturer JEDEC ID Code
BYTE65
~71
....Manufacturer JEDEC ID Code
BYTE72
Manufacturing Location
Rev. 1.1/Dec.99
256MB
40h
1.5ns
15h
Intel SPD 1.2
12h
-
F9h
Hyundai JEDEC ID
ADh
Unused
FFh
HEI (Korea)
HEA (United States)
HEU (Europe)
NOTE
1
2
3, 8
01h
02h
03h
5
PC133 SDRAM Registered DIMM
HYM71V73C3201 N-Series
Continued
BYTE
FUNCTION
FUNCTION
VALUE
NUMBER
DESCRIBED
-75
-75
7 (SDRAM)
37h
4, 5
1
31h
4, 5
V (3.3V, LVTTL)
56h
4, 5
NOTE
BYTE73
Manufacturer’ s Part Number (Component)
BYTE74
Manufacturer’ s Part Number (128Mb based)
BYTE75
Manufacturer’ s Part Number (Voltage Interface)
BYTE76
Manufacturer’ s Part Number (Data Width)
7
37h
4, 5
BYTE77
....Manufacturer’ s Part Number (Data Width)
3
33h
4, 5
BYTE78
Manufacturer’ s Part Number (Module Type)
C
43h
4, 5
BYTE79
Manufacturer’ s Part Number (Memory Depth)
3
33h
4, 5
BYTE80
…
.Manufacturer’ s Part Number (Memory Depth)
2
32h
4, 5
BYTE81
Manufacturer’ s Part Number (Refresh)
0 (4K Refresh)
30h
4, 5
BYTE82
Manufacturer’ s Part Number (Internal Banks)
1 (4 Banks)
31h
4, 5
BYTE83
Manufacturer’ s Part Number (Package Type)
T (TSOPII)
54h
4, 5
BYTE84
Manufacturer’ s Part Number (Module Type)
N (x4 based)
4Eh
4, 5
BYTE85
Manufacturer’ s Part Number (Hyphen)
- (Hyphen)
2Dh
4, 5
BYTE86
Manufacturer’ s Part Number (Min. Cycle Time)
7
37h
4, 5
BYTE87
....Manufacturer’ s Part Number (Min. Cycle Time)
5
35h
4, 5
BYTE88
~90
Manufacturer’ s Part Number
Blanks
20h
4, 5
BYTE91
Revision Code (for Component)
Process Code
-
4, 6
BYTE92
....Revision Code (for PCB)
Process Code
-
4, 6
BYTE93
Manufacturing Date
Work Week
-
3, 6
BYTE94
....Manufacturing Date
Year
-
3, 6
BYTE95
~98
Assembly Serial Number
Serial Number
-
6
BYTE99
~125
Manufacturer Specific Data (may be used in
future)
None
00h
BYTE126
Reserved
Refer to Note9
64h
8, 9
BYTE127
Reserved
Refer to Note9
87h
8, 9
BYTE128
~256
Unused Storage Locations
-
00h
Note: 1. The bank address is excluded.
2. 1,2,4,8 for Interleave Burst Type
3. BCD adopted.
4. ASCII adopted.
5. Basically HYUNDAI writes Part No. except for ` HYM ` in Byte 73-90 to use the limited 18 bytes from byte 73 to 90 efficiently.
6. Not fixed but dependent.
7. CLK0 connected on the DIMM, TBD junction temp, CL2(3) support, Intel defined Concurrent Auto Precharge support
8. Refer to most recent version Intel and JEDEC SPD Specification.
9. These values are applied to PC100 applicationsonly per Intel PC SDRAM specification
Rev. 1.1/Dec.99
6
PC133 SDRAM Registered DIMM
HYM71V73C3201 N-Series
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
0 ~ 70
°C
Ambient Temperature
TA
Storage Temperature
TSTG
-55 ~ 125
°C
Voltage on any Pin relative to VSS
VIN, VOUT
-1.0 ~ 4.6
V
Voltage on VDD relative to VSS
VDD, VDDQ
-1.0 ~ 4.6
V
Short Circuit Output Current
IOS
50
MA
Power Dissipation
PD
9
W
Soldering Temperature · Time
TSOLDER
260 · 10
°C · Sec
Note : Operation at above absolute maximum can adversely affect device reliability.
DC OPERATING CONDITION
(TA = 0 to 70°C)
PARAMETER
SYMBOL
MIN
TYP.
MAX
UNIT
NOTE
Power Supply Voltage
VCC
3.0
3.3
3.6
V
1
Input High Voltage
VIH
2.0
3.0
VCC + 0.3
V
1, 2
Input Low Voltage
VIL
– 0.3
0
0.8
V
1, 3
Note : 1. All voltage are referenced to VSS = 0V.
2. VIH (max) is acceptable 5.6V AC pulse width with ≤ 3ns of duration.
3. VIL (min) is acceptable –2.0V AC pulse width with ≤ 3ns of duration.
AC OPERATING CONDITION
(TA = 0 to 70°C, VDD = 3.3 ± 0.3V, VSS = 0V)
PARAMETER
SYMBOL
VALUE
UNIT
2.4 / 0.4
V
1.4
V
AC Input High / Low Level Voltage
VIH / VIL
Input Timing Measurement Reference Level Voltage
Vtrip
Input Rise / Fall Time
tR / tF
1
ns
Output Timing Measurement Reference Level Voltage
Voutref
1.4
V
Output Load Capacitance for Access Time Measurement
CL
*Note
pF
Note : *. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF).
For details, refer to AC/DC output circuit.
Rev. 1.1/Dec.99
7
PC133 SDRAM Registered DIMM
HYM71V73C3201 N-Series
CAPACITANCE
(TA = 25°C, f = 1MHz)
PARAMETER
Input Capacitance
Data Input/Output Capacitance
PIN
SYMBOL
MIN
MAX
TYP.
UNIT
CK0
CIN1
-
30
-
pF
CKE0
CIN2
-
15
-
pF
/S0, /S1
CIN3
-
15
-
pF
A0~A11, BA0, BA1
CIN4
-
15
-
pF
/RAS, /CAS, /WE
CIN5
-
15
-
pF
DQM0~DQM7
CIN6
-
15
-
pF
DQ0~DQ63, CB0~CB7
CI/O
-
15
-
pF
OUTPUT LOAD CIRCUIT
Rev. 1.1/Dec.99
8
PC133 SDRAM Registered DIMM
HYM71V73C3201 N-Series
DC CHARACTERISTICS I
(TA = 0 to 70°C, VDD = 3.3 ± 0.3V)
PARAMETER
SYMBOL
MIN
MAX
UNIT
NOTE
Input Leakage Current
ILI
-10
10
uA
1
Output Leakage Current
ILO
-1
1
uA
2
Output High Voltage
VOH
2.4
-
V
IOH = -4mA
Output Low Voltage
VOL
-
0.4
V
IOL = +4mA
Note : 1. VIN = 0 to 3.6V. All other pins are not tested under VIN = 0V.
2. DOUT is disabled. VOUT = 0 to 3.6V.
DC CHARACTERISTICS II
(TA = 0 to 70°C, VDD = 3.3 ± 0.3V, VSS = 0V)
SPEED
PARAMETER
SYMBOL
TEST CONDITION
UNIT
NOTE
1
-75
Operating Current
Precharge Standby Current
in Power Down Mode
IDD1
Burst Length = 1, One bank active
tRC ≥ tRC(min), IOL = 0mA
2660
mA
IDD2P
CKE ≤ VIL(max), tCK = min
356
mA
IDD2PS
CKE ≤ VIL(max), tCK = ∞
117
mA
IDD2N
CKE ≥ VIH(min), /CS ≥ VIH(min), tCK = min
Input signals are changed one time during
2clks. All other pins ≥ VDD – 0.2V or ≤ 0.2V
760
mA
IDD2NS
CKE ≥ VIH(max), tCK = ∞
Input signals are stable.
270
mA
IDD3P
CKE ≤ VIL(max), tCK = min
446
mA
IDD3PS
CKE ≤ VIL(max), tCK = ∞
216
mA
IDD3N
CKE ≥ VIH(min), /CS ≥ VIH(min), tCK = min
Input signals are changed one time during
2clks. All other pins ≥ VDD – 0.2V or ≤ 0.2V
1120
mA
IDD3NS
CKE ≥ VIH(max), tCK = ∞
Input signals are stable.
810
mA
Precharge Standby Current
in Non Power Down Mode
Active Standby Current
in Power Down Mode
Active Standby Current
in Non Power Down Mode
tCK ≥ tCK(min), IOL = 0mA
Burst Mode Operating
Current
IDD4
Auto Refresh Current
IDD5
tRRC ≥ tRRC(min), All banks active
Self Refresh Current
IDD6
CKE ≤ 0.2V
All banks active
CL = 3
3200
CL = 2
2900
mA
1
5060
mA
2
276
mA
Note : 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open.
2. Min. of tRRC (Refresh /RAS cycle time) is shown at AC CHARACTERISTICS II.
Rev. 1.1/Dec.99
9
PC133 SDRAM Registered DIMM
HYM71V73C3201 N-Series
AC CHARACTERISTICS I
(AC operating conditions unless otherwise noted)
-75
PARAMETER
SYMBOL
UNIT
MIN
/CAS Latency = 3
tCK3
7.5
/CAS Latency = 2
tCK2
10
Clock High Pulse Width
tCHW
Clock Low Pulse Width
System Clock
Cycle Time
NOTE
MAX
1000
ns
2.5
-
ns
I
tCLW
2.5
-
ns
I
/CAS Latency = 3
tAC3
-
5.4
ns
2
/CAS Latency = 2
tAC2
-
6
Data-Out Hold Time
tOH
2.7
-
ns
Data-Input Setup Time
tDS
1.5
-
ns
1
Data-Input Hold Time
tDH
0.8
-
ns
1
Address Setup Time
tAS
1.5
-
ns
1
Address Hold Time
tAH
0.8
-
ns
1
CKE Setup Time
tCKS
1.5
-
ns
1
CKE Hold Time
tCKH
0.8
-
ns
1
Command Setup Time
tCS
1.5
-
ns
1
Command Hold Time
tCH
0.8
-
ns
1
CLK to Data Output in Low-Z time
tOLZ
1
-
ns
CLK to Data
Output
in
High-Z time
tOHZ3
2.7
5.4
ns
Access Time
from Clock
/CAS Latency = 3
Note :
1. Assume tR / tF (input rise and fall time ) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter
2. Access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v.
If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter
Rev. 1.1/Dec.99
10
PC133 SDRAM Registered DIMM
HYM71V73C3201 N-Series
AC CHARACTERISTICS II
-75
PARAMETER
SYMBOL
UNIT
MIN
Operation
tRC
65
Auto Refresh
tRRC
65
/RAS to /CAS Delay
tRCD
/RAS Active Time
/RAS
Time
Cycle
-
ns
20
-
ns
tRAS
45
100K
ns
/RAS Precharge Time
tRP
20
-
/RAS to /RAS Bank Active Delay
tRRD
15
-
ns
/CAS to /CAS Delay
tCCD
1
-
CLK
Write Command to Data-in Delay
tWTL
1
-
CLK
Data-in to Precharge Command
tDPL
1
-
CLK
Data-in to Active Command
tDAL
4
-
CLK
DQM to Data-out Hi-Z
tDQZ
3
-
CLK
DQM to Data-in Mask
tDQM
0
-
CLK
MRS to New Command
tMRD
2
-
CLK
/CAS Latency = 3
tPROZ3
4
-
/CAS Latency = 2
tPROZ2
3
-
Power Down Exit Time
tPDE
1
-
CLK
Self Refresh Exit Time
tSRE
1
-
CLK
Refresh Time
tREF
-
64
ms
Precharge to
Data
Output
Hi-Z
NOTE
MAX
CLK
1
Note : 1. A new command can be given tRRC after self refresh exit.
Rev. 1.1/Dec.99
11
PC133 SDRAM Registered DIMM
HYM71V73C3201 N-Series
OPERATING OPTION TABLE
HYM71V73C3201TN-75
/CAS
LATENCY
tRCD
tRAS
tRC
tRP
tAC
tOH
133MHz (7.5ns)
3CLKS
3CLKS
6CLKS
9CLKS
3CLKS
5.4ns
2.7ns
125MHz (8.0ns)
3CLKS
3CLKS
6CLKS
9CLKS
3CLKS
6ns
3ns
100MHz (10.0ns)
2CLKS
2CLKS
5CLKS
7CLKS
2CLKS
6ns
3ns
Note : DIMM /CAS Latency = Device CL + 1 (Registered mode)
COMMAND TRUTH TABLE
A10/
AP
CKEn-1
CKEn
/CS
/RAS
/CAS
/WE
DQM
Mode Register Set
H
X
L
L
L
L
X
OP code
H
X
X
X
No Operation
H
X
X
X
L
H
H
H
Bank Active
H
X
L
L
H
H
X
H
X
L
H
L
H
X
ADDR
RA
BA
NOTE
V
Read
L
CA
V
Read with Autoprecharge
H
Write
L
H
X
L
H
L
L
X
CA
V
Write with Autoprecharge
H
Precharge All Banks
H
X
L
L
H
L
X
Precharge Selected Bank
Burst Stop
H
X
DQM
H
Auto Refresh
H
H
L
L
L
Entry
H
L
L
L
H
X
Exit
L
H
H
H
H
L
X
X
V
X
H
X
X
L
H
X
X
X
X
Self Refresh
Entry
L
X
L
V
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
L
Precharge
Power Down
H
X
1
X
X
Exit
Entry
L
H
H
X
L
X
Clock Suspend
X
Exit
L
H
X
X
Note : 1. Existing Self Refresh occurs by asynchronously bringing CKE from low to high.
2. X = Don’ t care, H = Logic High, L = logic Low, BA = Bank Address, CA = Column Address, OP code = Operand code,
NOP = No operation
Rev. 1.1/Dec.99
12
PC133 SDRAM Registered DIMM
HYM71V73C3201 N-Series
PACKAGE DIMENSIONS
Rev. 1.1/Dec.99
13