ETC HYM7V65401BTQG

4Mx64 bits
PC100 SDRAM SO DIMM
based on 4Mx16 SDRAM with LVTTL, 4 banks & 4K Refresh
HYM7V65401B Q-Series
DESCRIPTION
The Hynix HYM7V65401B Q-Series are 4Mx64bits Synchronous DRAM Modules. The modules are composed of four
4Mx16bit CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package and 2Kbit EEPROM in 8pin TSSOP package
on a 144pin glass-epoxy printed circuit board. Three 0.1uF decoupling capacitors per each SDRAM are mounted on the
PCB.
The HYM7V65401B Q-Series are Small Outline Dual In-line Memory Modules suitable for easy interchange and addition
of 32Mbytes memory. The HYM7V65401B Q-Series are offering fully synchronous operation referenced to a positive
edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are
internally pipelined to achieve very high bandwidth.
FEATURES
• PC100MHz support
• SDRAM internal banks : four banks
• 144pin SDRAM SO DIMM
• Module bank : one physical bank
• Serial Presence Detect with EEPROM
• Auto refresh and self refresh
• 1.00” (25.40mm) Height PCB with Double Sided
components
• 4096 refresh cycles / 64ms
• Single 3.3 ± 0.3V power supply
• All devices pins are compatible with LVTTL interface
• Data mask function by DQM
• Programmable Burst Length and Burst Type
-. 1, 2, 4, 8, or Full Page for Sequential Burst
-. 1, 2, 4 or 8 for Interleave Burst
• Programmable /CAS Latency
-. 2, 3 Clocks
ORDERING INFORMATION
PART NO.
MAX.
FREQUENCY
HYM7V65401BTQG-8
125MHz
HYM7V65401BTQG-10P
100MHz
HYM7V65401BTQG-10S
100MHz
HYM7V65401BLTQG-8
125MHz
HYM7V65401BLTQG-10P
100MHz
HYM7V65401BLTQG-10S
100MHz
INTERNAL
BANK
REF.
POWER
SDRAM
PACKAGE
PLATING
TSOP-II
Gold
Normal
4 Banks
4K
Low Power
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not
assume any responsibility for use of circuits described. No patent licenses are implied.
1
Rev. 1.2/Dec. 01
PC100 SDRAM SO DIMM
HYM7V65401B Q-Series
PIN DESCRIPTION
PIN NAME
DESCRIPTION
CK0, CK1
Clock Inputs
The System Clock Input. All other inputs are registered to the
SDRAM on the rising edge of CLK.
CKE0
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM
will be one of the states among power down, suspend or self
refresh.
/S0
Chip Select
Enables or disables all inputs except CK, CKE and DQM.
BA0, BA1
SDRAM Bank Address
A0~A11
Address Inputs
/RAS
Row Address Strobe
/CAS
Column Address Strobe
/WE
Write Enable
DQM0~DQM7
Data Input/Output Mask
Controls output buffers in read mode and masks input data in
write mode.
DQ0~DQ63
Data Input/Output
Multiplexed data input/output pins
VCC
Power Supply (3.3V)
Power supply for internal circuits and input/output buffers
VSS
Ground
Ground
SCL
SPD Clock Input
Serial Presence Detect Clock Input
SDA
SPD Data Input/Output
Serial Presence Detect Data input/output
NC
No Connect
No Connect or Don’t Use
Rev. 1.2/Dec. 01
Select bank to be activated during /RAS activity.
Select bank to be read/written during /CAS activity
Row address : RA0~RA11, Column address : CA0~CA7
Auto-precharge flag : A10
/RAS define the operation.
Refer to the function truth table for details.
/CAS define the operation.
Refer to the function truth table for details.
/WE define the operation.
Refer to the function truth table for details.
2
PC100 SDRAM SO DIMM
HYM7V65401B Q-Series
PIN ASSIGNMENTS
FRONT SIDE
PIN NO.
NAME
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
VSS
DQM0
DQM1
VCC
A0
A1
A2
VSS
DQ8
DQ9
DQ10
DQ11
VCC
DQ12
DQ13
DQ14
DQ15
VSS
NC
NC
PIN NO.
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
BACK SIDE
NAME
VSS
DQ32
DQ33
DQ34
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
VSS
DQM4
DQM5
VCC
A3
A4
A5
VSS
DQ40
DQ41
DQ42
DQ43
VCC
DQ44
DQ45
DQ46
DQ47
VSS
NC
NC
Voltage Key
61
63
65
67
69
CK0
VCC
/RAS
/WE
/S0
62
64
66
68
70
CKE0
VCC
/CAS
NC
NC
FRONT SIDE
PIN NO.
NAME
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
NC
NC
VSS
NC
NC
VCC
DQ16
DQ17
DQ18
DQ19
VSS
DQ20
DQ21
DQ22
DQ23
VCC
A6
A8
VSS
A9
A10/AP
VCC
DQM2
DQM3
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
SDA
VCC
PIN NO.
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
BACK SIDE
NAME
NC
*CK1
VSS
NC
NC
VCC
DQ48
DQ49
DQ50
DQ51
VSS
DQ52
DQ53
DQ54
DQ55
VCC
A7
BA0
VSS
BA1
A11
VCC
DQM6
DQM7
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
SCL
VCC
Note : *. CK1 is connected with termination R/C. (Refer to the Block Diagram.)
Rev. 1.2/Dec. 01
3
PC100 SDRAM SO DIMM
HYM7V65401B Q-Series
BLOCK DIAGRAM
Note : 1. The serial resistor values of DQs are 10 Ohms.
2. The padding capacitance of termination R/C for CK1 is 10pF.
Rev. 1.2/Dec. 01
4
PC100 SDRAM SO DIMM
HYM7V65401B Q-Series
SERIAL PRESENCE DETECT
BYTE
FUNCTION
NUMBER
DESCRIBED
FUNCTION
-8
VALUE
-10P
-10S
-8
-10P
# of Bytes Written into Serial Memory
at Module Manufacturer
128 Bytes
80h
BYTE1
Total # of Bytes of SPD Memory Device
256 Bytes
08h
BYTE2
Fundamental Memory Type
BYTE3
BYTE0
-10S
SDRAM
04h
# of Row Addresses on This Assembly
12
0Ch
BYTE4
# of Column Addresses on This Assembly
8
08h
BYTE5
# of Module Banks on This Assembly
1 Bank
01h
BYTE6
Data Width of This Assembly
64 Bits
40h
BYTE7
Data Width of This Assembly (Continued)
BYTE8
Voltage Interface Standard of This Assembly
BYTE9
SDRAM Cycle Time @ /CAS Latency=3
8ns
10ns
10ns
80h
A0h
A0h
BYTE10
Access Time from Clock @ /CAS Latency=3
6ns
6ns
6ns
60h
60h
60h
BYTE11
DIMM Configuration Type
BYTE12
Refresh Rate/Type
BYTE13
Primary SDRAM Width
BYTE14
Error Checking SDRAM Width
BYTE15
Minimum Clock Delay Back to Back Random
Column Address
BYTE16
Burst Lengths Supported
BYTE17
# of Banks on Each SDRAM Device
BYTE18
SDRAM Device Attributes, CAS # Latency
BYTE19
SDRAM Device Attributes, CS # Latency
BYTE20
SDRAM Device Attributes, Write Latency
BYTE21
SDRAM Module Attributes
-
00h
LVTTL
01h
None
00h
15.625µs
/ Self Refresh Supported
80h
x16
10h
None
00h
tCCD = 1 CLK
01h
1,2,4,8,Full Page
8Fh
4 Banks
04h
/CAS Latency=2,3
06h
/CS Latency=0
01h
/WE Latency=0
01h
Neither Buffered nor Registered
00h
+/-10% voltage tolerance, Burst
Read Single bit Write, Precharge
All, Auto Precharge, Early RAS
Precharge
0Eh
1
2
BYTE22
SDRAM Device Attributes, General
BYTE23
SDRAM Cycle Time @ /CAS Latency=2
10ns
10ns
12ns
A0h
A0h
C0h
BYTE24
Access Time from Clock @ /CAS Latency=2
6ns
6ns
6ns
60h
60h
60h
BYTE25
SDRAM Cycle Time @ /CAS Latency=1
-
-
-
00h
00h
00h
BYTE26
Access Time from Clock @ /CAS Latency=1
-
-
-
00h
00h
00h
BYTE27
Minimum Row Precharge Time (tRP)
20ns
20ns
20ns
14h
14h
14h
BYTE28
Minimum Row Active to Row Active Delay (tRRD)
16ns
20ns
20ns
10h
14h
14h
BYTE29
Minimum /RAS to /CAS Delay (tRCD)
20ns
20ns
20ns
14h
14h
14h
BYTE30
Minimum /RAS Pulse width (tRAS)
48ns
50ns
50ns
30h
32h
32h
BYTE31
Module Bank Density
BYTE32
Command and Address Signal Input Setup Time
2ns
2ns
2ns
20h
20h
BYTE33
Command and Address Signal Input Hold Time
1ns
1ns
1ns
10h
10h
10h
BYTE34
Data Signal Input Setup Time
2ns
2ns
2ns
20h
20h
20h
BYTE35
Data Signal Input Hold Time
1ns
1ns
1ns
10h
10h
10h
BYTE36
–61
Superset Information (may be used in future)
BYTE62
SPD Revision
BYTE63
Checksum for Bytes 0~62
BYTE64
Manufacturer JEDEC ID Code
BYTE65
~71
....Manufacturer JEDEC ID Code
BYTE72
Manufacturing Location
Rev. 1.2/Dec. 01
32MB
08h
-
12h
DEh
04h
Hynix JEDEC ID
ADh
Unused
FFh
Hynix (Korea Area)
HSA (United States Area)
HSE (Europe Area)
HSJ (Japan Area)
HSS (Singapore)
Asia Area
20h
00h
Intel SPD 1.2A
-
NOTE
0*h
1*h
2*h
3*h
4*h
5*h
3, 8
24h
9
5
PC100 SDRAM SO DIMM
HYM7V65401B Q-Series
Continued
BYTE
FUNCTION
NUMBER
DESCRIBED
BYTE73
Manufacturer’s Part Number (Component)
BYTE74
Manufacturer’s Part Number (Voltage Interface)
BYTE75
FUNCTION
-8
-10P
VALUE
-10S
-8
-10P
-10S
NOTE
7 (SDRAM)
37h
V (3.3V, LVTTL)
56h
4, 5
4, 5
Manufacturer’s Part Number (Data Width)
6
36h
4, 5
BYTE76
....Manufacturer’s Part Number (Data Width)
5
35h
4, 5
BYTE77
Manufacturer’s Part Number (Memory Depth)
4
34h
4, 5
BYTE78
Manufacturer’s Part Number (Refresh)
0 (4K Refresh)
30h
4, 5
BYTE79
Manufacturer’s Part Number (Internal Banks)
BYTE80
Manufacturer’s Part Number (Generation)
BYTE81
Manufacturer’s Part Number (Package Type)
BYTE82
Manufacturer’s Part Number (Module Type)
BYTE83
Manufacturer’s Part Number (Plating Type)
G (Gold)
47h
4, 5
BYTE84
Manufacturer’s Part Number (Hyphen)
- (Hyphen)
2Dh
4, 5
BYTE85
Manufacturer’s Part Number (Min. Cycle Time)
8
1
1
38h
31h
31h
4, 5
BYTE86
....Manufacturer’s Part Number (Min. Cycle Time)
Blank
0
0
20h
30h
30h
4, 5
BYTE87
....Manufacturer’s Part Number (Min. Cycle Time)
Blank
P
S
20h
50h
53h
4, 5
BYTE88
~90
Manufacturer’s Part Number
BYTE91
Revision Code (for Component)
Process Code
-
4, 6
BYTE92
....Revision Code (for PCB)
Process Code
-
4, 6
BYTE93
Manufacturing Date
BYTE94
....Manufacturing Date
BYTE95
~98
Assembly Serial Number
BYTE99
~125
Manufacturer Specific Data (may be used in
future)
BYTE126
System Frequency Support
BYTE127
Intel Specification Details for 100MHz Support
BYTE128
~256
Unused Storage Locations
1 (4 Banks)
31h
4, 5
B
42h
4, 5
T (TSOPII)
54h
4, 5
Q (x16 based SO DIMM)
51h
4, 5
Blanks
20h
4, 5
Year
-
3, 6
Work Week
-
3, 6
Serial Number
-
6
None
00h
100MHz
64h
Refer to Note7
87h
-
87h
8
85h
7, 8
00h
Note: 1. The bank address is excluded.
2. 1,2,4,8 for Interleave Burst Type
3. BCD adopted.
4. ASCII adopted.
5. Basically Hynix writes Part No. except for ` HYM ` in Byte 73-90 to use the limited 18 bytes from byte 73 to 90 efficiently.
6. Not fixed but dependent.
7. CLK0 connected on the DIMM, TBD junction temp, CL2(3) support, Intel defined Concurrent Auto Precharge support
8. Refer to Intel SPD Specification Rev.1.2A.
9. Refer to Hynix Web Site
BYTE81~88 for L-Part (HYM7V65401BLTQG)
BYTE
FUNCTION
NUMBER
DESCRIBED
BYTE81
Manufacturer’s Part Number (Power)
BYTE82
Manufacturer’s Part Number (Package Type)
BYTE83
FUNCTION
-8
-10P
VALUE
-10S
-8
-10P
-10S
NOTE
L (Low Power)
4Ch
4, 5
T (TSOPII)
54h
4, 5
Manufacturer’s Part Number (Module Type)
Q (x16 based SO DIMM)
51h
4, 5
BYTE84
Manufacturer’s Part Number (Plating Type)
G (Gold)
47h
4, 5
BYTE85
Manufacturer’s Part Number (Hyphen)
- (Hyphen)
2Dh
4, 5
BYTE86
Manufacturer’s Part Number (Min. Cycle Time)
8
1
1
38h
31h
31h
4, 5
BYTE87
....Manufacturer’s Part Number (Min. Cycle Time)
Blank
0
0
20h
30h
30h
4, 5
BYTE88
....Manufacturer’s Part Number (Min. Cycle Time)
Blank
P
S
20h
50h
53h
4, 5
Rev. 1.2/Dec. 01
6
PC100 SDRAM SO DIMM
HYM7V65401B Q-Series
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
0 ~ 70
°C
Ambient Temperature
TA
Storage Temperature
TSTG
-55 ~ 125
°C
Voltage on any Pin relative to VSS
VIN, VOUT
-1.0 ~ 4.6
V
Voltage on VDD relative to VSS
VDD, VDDQ
-1.0 ~ 4.6
V
Short Circuit Output Current
IOS
50
MA
Power Dissipation
PD
4
W
Soldering Temperature · Time
TSOLDER
260 · 10
°C · Sec
Note : Operation at above absolute maximum can adversely affect device reliability.
DC OPERATING CONDITION
(TA = 0 to 70°C)
PARAMETER
SYMBOL
MIN
TYP.
MAX
UNIT
NOTE
Power Supply Voltage
VCC
3.0
3.3
3.6
V
1
Input High Voltage
VIH
2.0
3.0
VCC + 2.0
V
1, 2
Input Low Voltage
VIL
VSS – 2.0
0
0.8
V
1, 3
Note : 1. All voltage are referenced to VSS = 0V.
2. VIH (max) is acceptable 5.6V AC pulse width with ≤ 3ns of duration.
3. VIL (min) is acceptable –2.0V AC pulse width with ≤ 3ns of duration.
AC OPERATING CONDITION
(TA = 0 to 70°C, VDD = 3.3 ± 0.3V, VSS = 0V)
PARAMETER
SYMBOL
VALUE
UNIT
2.4 / o.4
V
1.4
V
AC Input High / Low Level Voltage
VIH / VIL
Input Timing Measurement Reference Level Voltage
Vtrip
Input Rise / Fall Time
tR / tF
1
ns
Output Timing Measurement Reference Level Voltage
Voutref
1.4
V
Output Load Capacitance for Access Time Measurement
CL
*Note
pF
Note : *. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF).
For details, refer to AC/DC output circuit.
Rev. 1.2/Dec. 01
7
PC100 SDRAM SO DIMM
HYM7V65401B Q-Series
CAPACITANCE
(TA = 25°C, f = 1MHz)
PARAMETER
Input Capacitance
Data Input/Output Capacitance
PIN
SYMBOL
MIN
MAX
TYP.
UNIT
CK0
CIN1
-
45
-
pF
CKE0
CIN2
-
40
-
pF
/S0
CIN3
-
40
-
pF
A0~A11, BA0, BA1
CIN4
-
40
-
pF
/RAS, /CAS, /WE
CIN5
-
45
-
pF
DQM0~DQM7
CIN6
-
15
-
pF
DQ0~DQ63
CI/O
-
15
-
pF
OUTPUT LOAD CIRCUIT
Rev. 1.2/Dec. 01
8
PC100 SDRAM SO DIMM
HYM7V65401B Q-Series
DC CHARACTERISTICS I
(TA = 0 to 70°C, VDD = 3.3 ± 0.3V)
PARAMETER
SYMBOL
MIN
MAX
UNIT
NOTE
Input Leakage Current
ILI
-4
4
uA
1
Output Leakage Current
ILO
-1
1
uA
2
Output High Voltage
VOH
2.4
-
V
IOH = -4mA
Output Low Voltage
VOL
-
0.4
V
IOL = +4mA
Note : 1. VIN = 0 to 3.6V. All other pins are not tested under VIN = 0V.
2. DOUT is disabled. VOUT = 0 to 3.6V.
DC CHARACTERISTICS II
(TA = 0 to 70°C, VDD = 3.3 ± 0.3V, VSS = 0V)
PARAMETER
SYMBOL
SPEED
TEST CONDITION
-8
-10P
-10S
320
280
280
UNIT
NOTE
mA
1
Operating Current
IDD1
Burst Length = 1, One bank active
tRC ≥ tRC(min), IOL = 0mA
Precharge Standby Current
in Power Down Mode
IDD2P
CKE ≤ VIL(max), tCK = min
8
mA
IDD2PS
CKE ≤ VIL(max), tCK = ∞
8
mA
IDD2N
CKE ≥ VIH(min), /CS ≥ VIH(min), tCK = min
Input signals are changed one time during
2clks. All other pins ≥ VDD – 0.2V or ≤ 0.2V
60
mA
IDD2NS
CKE ≥ VIH(max), tCK = ∞
Input signals are stable.
60
mA
IDD3P
CKE ≤ VIL(max), tCK = min
20
mA
IDD3PS
CKE ≤ VIL(max), tCK = ∞
20
mA
IDD3N
CKE ≥ VIH(min), /CS ≥ VIH(min), tCK = min
Input signals are changed one time during
2clks. All other pins ≥ VDD – 0.2V or ≤ 0.2V
120
mA
IDD3NS
CKE ≥ VIH(max), tCK = ∞
Input signals are stable.
120
mA
Precharge Standby Current
in Non Power Down Mode
Active Standby Current
in Power Down Mode
Active Standby Current
in Non Power Down Mode
Burst
Mode
Current
Operating
IDD4
tCK ≥ tCK(min), IOL = 0mA
CL = 3
440
360
360
All banks active
CL = 2
360
360
360
800
720
720
Auto Refresh Current
IDD5
tRRC ≥ tRRC(min), All banks active
Self Refresh Current
IDD6
CKE ≤ 0.2V
mA
1
mA
2
8
mA
2
mA
3
Note : 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open.
2. Min. of tRRC (Refresh /RAS cycle time) is shown at AC CHARACTERISTICS II.
3. L-part (HYM7V65401BLTQG)
Rev. 1.2/Dec. 01
9
PC100 SDRAM SO DIMM
HYM7V65401B Q-Series
AC CHARACTERISTICS I
(AC operating conditions unless otherwise noted)
PARAMETER
-8
SYMBOL
MIN
-10P
MAX
MIN
MAX
/CAS Latency = 3
tCK3
8
/CAS Latency = 2
tCK2
10
Clock High Pulse Width
tCHW
3
-
3
-
Clock Low Pulse Width
tCLW
3
-
3
/CAS Latency = 3
tAC3
-
6
/CAS Latency = 2
tAC2
-
Data-Out Hold Time
tOH
Data-Input Setup Time
tDS
System Clock
Cycle Time
Access Time
from Clock
1000
10
-10S
1000
MIN
10
UNIT
NOTE
MAX
1000
ns
3
-
ns
I
-
3
-
ns
I
-
6
-
6
ns
2
6
-
6
-
6
3
-
3
-
3
-
ns
2
-
2
-
2
-
ns
10
12
1
Data-Input Hold Time
tDH
1
-
1
-
1
-
ns
1
Address Setup Time
tDS
2
-
2
-
2
-
ns
1
Address Hold Time
tDH
1
-
1
-
1
-
ns
1
CKE Setup Time
tDS
2
-
2
-
2
-
ns
1
CKE Hold Time
tDH
1
-
1
-
1
-
ns
1
Command Setup Time
tDS
2
-
2
-
2
-
ns
1
Command Hold Time
tDH
1
-
1
-
1
-
ns
1
CLK to Data Output in Low-Z time
tOLZ
1
-
1
-
1
-
ns
CLK to Data
Output
in
High-Z time
/CAS Latency = 3
tOHZ3
3
6
3
6
3
6
/CAS Latency = 2
tOHZ2
3
6
3
6
3
6
ns
Note : 1. Assume tR / tF (input rise and fall time) is 1ns.
2. Access times to be measured with input signals of 1v/ns edge rate.
Rev. 1.2/Dec. 01
10
PC100 SDRAM SO DIMM
HYM7V65401B Q-Series
AC CHARACTERISTICS II
PARAMETER
-8
SYMBOL
MIN
-10P
MAX
MIN
MAX
Operation
tRC
68
Auto Refresh
tRRC
68
/RAS to /CAS Delay
tRCD
20
-
20
-
/RAS Active Time
tRAS
48
100K
50
/RAS Precharge Time
tRP
20
-
/RAS to /RAS Bank Active Delay
tRRD
16
/CAS to /CAS Delay
tCCD
1
Write Command to Data-in Delay
tWTL
Data-in to Precharge Command
Data-in to Active Command
DQM to Data-out Hi-Z
/RAS
Time
Cycle
-
MIN
70
UNIT
ns
20
-
ns
100K
50
100K
ns
20
-
20
-
ns
-
20
-
20
-
ns
-
1
-
1
-
CLK
0
-
0
-
0
-
CLK
tDPL
1
-
1
-
1
-
CLK
tDAL
4
-
3
-
3
-
CLK
tDQZ
2
-
2
-
2
-
CLK
DQM to Data-in Mask
tDQM
0
-
0
-
0
-
CLK
MRS to New Command
tMRD
2
-
2
-
2
-
CLK
Precharge to
Data
Output
Hi-Z
/CAS Latency = 3
tPROZ3
3
-
3
-
3
-
/CAS Latency = 2
tPROZ2
2
-
2
-
2
-
tPDE
1
-
1
-
1
-
CLK
Self Refresh Exit Time
tSRE
1
-
1
-
1
-
CLK
Refresh Time
tREF
-
64
-
64
-
64
ms
70
NOTE
MAX
-
Power Down Exit Time
-
70
-10S
70
CLK
1
Note : 1. A new command can be given tRRC after self refresh exit.
Rev. 1.2/Dec. 01
11
PC100 SDRAM SO DIMM
HYM7V65401B Q-Series
OPERATING OPTION TABLE
HYM7V65401BTQG-8 / HYM7V65401BLTQG-8
/CAS
LATENCY
tRCD
tRAS
tRC
tRP
tAC
tOH
125MHz (8.0ns)
3CLKS
3CLKS
6CLKS
9CLKS
3CLKS
6ns
3ns
100MHz (10.0ns)
2CLKS
2CLKS
5CLKS
7CLKS
2CLKS
6ns
3ns
83MHz (12.0ns)
2CLKS
2CLKS
4CLKS
6CLKS
2CLKS
6ns
3ns
HYM7V65401BTQG-10P / HYM7V65401BLTQG-10P
/CAS
LATENCY
tRCD
tRAS
tRC
tRP
tAC
tOH
100MHz (10.0ns)
2CLKS
2CLKS
5CLKS
7CLKS
2CLKS
6ns
3ns
83MHz (12.0ns)
2CLKS
2CLKS
5CLKS
7CLKS
2CLKS
6ns
3ns
66MHz (15.0ns)
2CLKS
2CLKS
4CLKS
6CLKS
2CLKS
6ns
3ns
HYM7V65401BTQG-10S / HYM7V65401BLTQG-10S
/CAS
LATENCY
tRCD
tRAS
tRC
tRP
tAC
tOH
100MHz (10.0ns)
3CLKS
2CLKS
5CLKS
7CLKS
2CLKS
6ns
3ns
83MHz (12.0ns)
2CLKS
2CLKS
5CLKS
7CLKS
2CLKS
6ns
3ns
66MHz (15.0ns)
2CLKS
2CLKS
4CLKS
6CLKS
2CLKS
6ns
3ns
Rev. 1.2/Dec. 01
12
PC100 SDRAM SO DIMM
HYM7V65401B Q-Series
COMMAND TRUTH TABLE
CKEn
/CS
/RAS
/CAS
/WE
DQM
Mode Register Set
H
X
L
L
L
L
X
OP code
No Operation
H
X
H
X
X
X
L
H
H
H
X
X
Bank Active
H
X
L
L
H
H
X
H
X
L
H
L
H
X
CA
H
X
L
H
L
L
X
CA
H
X
L
L
H
L
X
X
Burst Stop
H
X
L
H
H
L
X
X
DQM
H
V
X
Auto Refresh
H
H
L
L
L
H
X
X
Entry
H
L
L
L
L
H
X
Exit
L
H
H
X
X
X
L
H
H
H
Entry
H
L
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
Read
Read with Autoprecharge
Write
Write with Autoprecharge
Precharge All Banks
Precharge Selected Bank
Self Refresh
X
Precharge
Power Down
Exit
L
H
Entry
H
L
Clock Suspend
Exit
L
H
X
X
ADDR
A10/
AP
CKEn-1
RA
BA
NOTE
V
L
H
L
H
V
V
H
X
L
V
X
1
X
X
X
X
X
X
Note : 1. Existing Self Refresh occurs by asynchronously bringing CKE from low to high.
2. X = Don’t care, H = Logic High, L = logic Low, BA = Bank Address, CA = Column Address, OP code = Operand code,
NOP = No operation
Rev. 1.2/Dec. 01
13
PC100 SDRAM SO DIMM
HYM7V65401B Q-Series
PACKAGE DIMENSIONS
Rev. 1.2/Dec. 01
14