HYS 72Vx2x0GR Registered SDRAM-Modules 3.3 V 168-pin Registered SDRAM Modules 64 MB, 128 MB, 256 MB, 512 MB & 1 GB Densities • 168-pin JEDEC Standard, Registered 8 Byte Dual-In-Line SDRAM Module for PC and Server main memory applications • Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) • One bank 8M × 72, 16M × 72, 32M × 72 and 64M × 72 organization two bank 32M × 72 & 128M × 72 organization • Auto Refresh (CBR) and Self Refresh • All inputs and outputs are LVTTL compatible • Serial Presence Detect with E2PROM • Optimized for ECC applications with very low input capacitances • Utilizes 64M & 256M SDRAMs in TSOPII-54 packages with registers and PLL. The two bank module uses stacked TSOP54 packages. • Programmed Latencies: Product Speed CL tRCD tRP -8 PC100 2 2 2 -8A PC100 3 2 2 -8B PC100 3 2 3 • Card Size: 133.35 mm × 38.1 mm/ 43.18 mm × 4,00/6.50 mm with Gold contact pads • This specification follows INTEL’s “PC SDRAM Registered DIMM Specification” Rev. 1.2 • Single + 3.3 V (± 0.3 V) power supply • Performance: -8 -8A -8B PC100 PC100 PC100 Unit fCK Clock Frequency (max.) 100 100 100 MHz tCK Clock Cycle Time (min.) 10 10 10 ns tAC Clock Access Time (min.) 6 6 6 ns The HYS 72Vx2x0GR family are industry standard 168-pin 8-byte Dual in-line Memory Modules (DIMMs) which are organized as 8M × 72, 16M × 72, 32M × 72, 64M × 72 & 128M × 72 high speed memory arrays designed with Synchronous DRAMs (SDRAMs) for ECC applications. All control and address signals are registered on-DIMM and the design incorporates a PLL circuit for the Clock inputs. The 256 MB module is available as one bank and two bank module version. Use of an onboard register reduces capacitive loading on the input signals but are delayed by one cycle in arriving at the SDRAM devices. Decoupling capacitors are mounted on the PC board. The DIMMs use a serial presence detects scheme implemented via a serial E2PROM using the 2-pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All Infineon 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133.35 mm long footprint. Data Book 1 11.99 HYS 72Vx2x0GR Registered SDRAM-Modules Ordering Information Type Compliance Code Description HYS 72V8200GR-8 PC100-222-622R one bank 64 MB Reg. DIMM 64 MBit HYS 72V16200GR-8 PC100-222-622R one bank 128 MB Reg. DIMM 64 MBit HYS 72V32220GR-8 PC100-222-622R two bank 256 MB Reg. DIMM 64 MBit (stacked) HYS 72V32200GR-8 HYS 72V32200GR-8A HYS 72V32200GR-8B PC100-222-622R one bank 256 MB Reg. DIMM PC100-322-622R PC100-323-622R 256 MBit HYS 72V64200GR-8 HYS 72V64200GR-8A HYS 72V64200GR-8B PC100-222-622R one bank 512 MB Reg. DIMM PC100-322-622R PC100-323-622R 256 MBit PC100-222-622R two bank 1 GByte Reg. DIMM HYS 72V128220GR-8 HYS 72V128220GR-8A PC100-322-622R HYS 72V128220GR-8B PC100-323-622R SDRAM Technology 256 MBit (stacked) Note: All part numbers end with a place code (not shown), designating the die revision. Consult factory for current revision. Example: HYS 64V8200GR-8-B, indicating Rev. B dies are used for SDRAM components. Data Book 2 11.99 HYS 72Vx2x0GR Registered SDRAM-Modules Pin Definitions and Functions A0 - A11, A12 Address Inputs DQMB0 - DQMB7 Data Mask BA0, BA1 Bank Selects CS0 - CS3 Chip Select DQ0 - DQ63 Data Input/Output REGE Register Enable CB0 - CB7 Check Bits (x72 organization only) VDD RAS Row Address Strobe VSS Ground CAS Column Address Strobe SCL Clock for Presence Detect WE Read/Write Input SDA Serial Data Out CKE0 Clock Enable N.C. No Connection CLK0 - CLK3 Clock Input – – Power (+ 3.3 V) Address Format Density Organization Memory SDRAMs Banks 1 8M × 8 9 12/2/9 4k 64 ms 15.6 µs 128 MB 16M × 72 1 16M × 4 18 12/2/10 4k 64 ms 15.6 µs 256 MB 32M × 72 2 16M × 4 36 12/2/10 4k 64 ms 15.6 µs 256 MB 32M × 72 1 32M × 8 9 13/2/10 8k 64 ms 7.8 µs 512 MB 64M × 72 1 64M × 4 18 13/2/11 8k 64 ms 7.8 µs 2 64M × 4 36 13/2/11 8k 64 ms 7.8 µs 64 MB 1 GB 8M × 72 # of # of row/bank/ Refresh Period Interval SDRAMs columns bits 128M × 72 Pin Configuration PIN# Symbol PIN# Symbol PIN# Symbol PIN# Symbol 1 VSS 43 VSS 85 VSS 127 VSS 2 DQ0 44 DU 86 DQ32 128 CKE0 3 DQ1 45 CS2 87 DQ33 129 CS3 4 DQ2 46 DQMB2 88 DQ34 130 DQMB6 5 DQ3 47 DQMB3 89 DQ35 131 DQMB7 6 VDD 48 DU 90 VDD 132 N.C. 7 DQ4 49 VDD 91 DQ36 133 VDD 8 DQ5 50 N.C. 92 DQ37 134 N.C. 9 DQ6 51 N.C. 93 DQ38 135 N.C. 10 DQ7 52 CB2 94 DQ39 136 CB6 11 DQ8 53 CB3 95 DQ40 137 CB7 12 VSS 54 VSS 96 VSS 138 VSS Data Book 3 11.99 HYS 72Vx2x0GR Registered SDRAM-Modules Pin Configuration (cont’d) PIN# Symbol PIN# Symbol PIN# Symbol PIN# Symbol 13 DQ9 55 DQ16 97 DQ41 139 DQ48 14 DQ10 56 DQ17 98 DQ42 140 DQ49 15 DQ11 57 DQ18 99 DQ43 141 DQ50 16 DQ12 58 DQ19 100 DQ44 142 DQ51 17 DQ13 59 VDD 101 DQ45 143 VDD 18 VDD 60 DQ20 102 VDD 144 DQ52 19 DQ14 61 N.C. 103 DQ46 145 N.C. 20 DQ15 62 DU 104 DQ47 146 DU 21 CB0 63 N.C. 105 CB4 147 REGE 22 CB1 64 VSS 106 CB5 148 VSS 23 VSS 65 DQ21 107 VSS 149 DQ53 24 N.C. 66 DQ22 108 N.C. 150 DQ54 25 N.C. 67 DQ23 109 N.C. 151 DQ55 26 VDD 68 VSS 110 VDD 152 VSS 27 WE 69 DQ24 111 CAS 153 DQ56 28 DQMB0 70 DQ25 112 DQMB4 154 DQ57 29 DQMB1 71 DQ26 113 DQMB5 155 DQ58 30 CS0 72 DQ27 114 CS1 156 DQ59 31 DU 73 VDD 115 RAS 157 VDD 32 VSS 74 DQ28 116 VSS 158 DQ60 33 A0 75 DQ29 117 A1 159 DQ61 34 A2 76 DQ30 118 A3 160 DQ62 35 A4 77 DQ31 119 A5 161 DQ63 36 A6 78 VSS 120 A7 162 VSS 37 A8 79 CLK2 121 A9 163 CLK3 38 A10 (AP) 80 N.C. 122 BA0 164 N.C. 39 BA1 81 WP 123 A11 165 SA0 40 VDD 82 SDA 124 VDD 166 SA1 41 VDD 83 SCL 125 CLK1 167 SA2 42 CLK0 84 VDD 126 A12 168 VDD Data Book 4 11.99 HYS 72Vx2x0GR Registered SDRAM-Modules RCS0 RDQMB0 DQ0-DQ7 CS DQM DQ0-DQ7 D0 RDQMB4 DQ32-DQ39 CS DQM DQ0-DQ7 D4 RDQMB1 DQ8-DQ15 CS DQM DQ0-DQ7 D1 RDQMB5 DQ40-DQ47 CS DQM DQ0-DQ7 D5 CS WE DQM DQ0-DQ7 D8 RCB0-RCB7 RCS2 RDQMB2 DQ16-DQ23 CS DQM DQ0-DQ7 D2 RDQMB4 DQ48-DQ55 CS DQM DQ0-DQ7 D6 RDQMB3 DQ24-DQ31 CS DQM DQ0-DQ7 D3 RDQMB7 DQ56-DQ63 CS DQM DQ0-DQ7 D7 VCC D0-D8, Reg., DLL C VSS D0-D8, Reg., DLL CLK0 PLL Register 47 k Ω SDRAMs D0-D8 12 pF CS0/CS2 DQMB0-7 BA0, BA1 A0-A11,12* ) RAS CAS CKE0 WE E2PROM (256 word x 8 Bit) SA0 SA0 SA1 SA1 SDA SA2 WP SA2 SCL SCL RCS0/RCS2 RDQMB0-7 RBA0, RBA1 RA0-11,12 RRAS RCAS RCKE0 RWE SDRAMs D0-D8 SDRAMs D0-D8 SDRAMs D0-D8 SDRAMs D0-D8 SDRAMs D0-D8 SDRAMs D0-D8 Notes: 1) DQ wirding may differ from that decribed in this drawing; however DQ/DQB relationship must be maintained as shown 2) All resistors are 10 Ω unless otherwise noted *) A12 is only for 32 M x 72 organisation CLK1, CLK2, CLK3 REGE 10 k Ω 12 pF VCC SPB04130 Block Diagram: One Bank 8M × 72 & 32M × 72 SDRAM DIMM Modules HYS 72V8200GR/HYS 72V32200GR Using x8 Organized SDRAMs Data Book 5 11.99 HYS 72Vx2x0GR Registered SDRAM-Modules RCS0 RDQMB0 RDQMB4 DQ0-DQ3 DQM CS DQ0-DQ3 D0 DQ32-DQ35 DQM CS DQ0-DQ3 D8 DQ4-DQ7 DQM CS DQ0-DQ3 D1 DQ36-DQ39 DQM CS DQ0-DQ3 D9 RDQMB1 RDQMB5 DQ8-DQ11 DQM CS DQ0-DQ3 D2 DQ40-DQ43 DQM CS DQ0-DQ3 D10 DQ12-DQ15 DQM CS DQ0-DQ3 D3 DQ44-DQ47 DQM CS DQ0-DQ3 D11 CB0-CB3 DQM CS DQ0-DQ3 D16 CB4-CB7 DQM CS DQ0-DQ3 D17 RCS2 RDQMB2 RDQMB6 DQ16-DQ19 CS DQM DQ0-DQ3 D4 DQ48-DQ51 CS DQM DQ0-DQ3 D12 DQ20-DQ23 DQM CS DQ0-DQ3 D5 DQ52-DQ55 DQM CS DQ0-DQ3 D13 RDQMB3 RDQMB7 DQ24-DQ27 DQM CS DQ0-DQ3 D6 DQ56-DQ59 DQM CS DQ0-DQ3 D14 DQ28-DQ31 CS DQM DQ0-DQ3 D7 DQ60-DQ63 CS DQM DQ0-DQ3 D15 CLK0 PLL CS0/CS2 DQMB0-7 BA0, BA1 A0-A11, A12* ) RAS CAS CKE0 WE REGE 10 k Ω V CC Register 12 pF SDRAMs D0-D17 CLK1, CLK2, CLK3 RCS0/RCS2 RDQMB0-7 RBA0, RBA1 RA0-RA11 RRAS RCAS RCKE0 RWE 12 pF SDRAMs D0-D17 SDRAMs D0-D17 SDRAMs D0-D17 SDRAMs D0-D17 SDRAMs D0-D17 SDRAMs D0-D17 *) A12 is only used for 128 M x 72 organisation SA0 SA1 SA2 SCL E 2PROM (256 word x 8 Bit) SA0 SA1 SDA SA2 WP SCL V CC 47 k Ω D0-D17, Reg., DLL C V SS D0-D17, Reg., DLL 1) DQ wirding may differ from that decribed in this drawing; however DQ/DQB relationship must be maintained as shown 2) All resistors are 10 Ω unless otherwise noted SPB04131 Block Diagram: One Bank 16M × 72 & 64M × 72 SDRAM DIMM Modules HYS 72V16200GR/HYS 72V64200GR Using x4 Organized SDRAMs Data Book 6 11.99 HYS 72Vx2x0GR Registered SDRAM-Modules RCS0 RCS1 RDQMB0 RDQMB4 DQ0-DQ3 DQM CS DQ0-DQ3 D0 DQM CS DQ0-DQ3 D0 DQ32-DQ35 DQM CS DQ0-DQ3 D8 DQM CS DQ0-DQ3 D8 DQ4-DQ7 CS DQM DQ0-DQ3 D1 CS DQM DQ0-DQ3 D1 DQ36-DQ39 CS DQM DQ0-DQ3 D9 CS DQM DQ0-DQ3 D9 DQ8-DQ11 CS DQM DQ0-DQ3 D2 CS DQM DQ0-DQ3 D2 DQ40-DQ43 CS DQM DQ0-DQ3 D10 CS DQM DQ0-DQ3 D10 DQ12-DQ15 DQM CS DQ0-DQ3 D3 DQM CS DQ0-DQ3 D3 DQ44-DQ47 DQM CS DQ0-DQ3 D11 DQM CS DQ0-DQ3 D11 CB0-CB3 CS DQM DQ0-DQ3 D16 CS DQM DQ0-DQ3 D16 CB4-CB7 CS DQM DQ0-DQ3 D17 CS DQM DQ0-DQ3 D17 DQ16-DQ19 DQM CS DQ0-DQ3 D4 DQM CS DQ0-DQ3 D4 DQ48-DQ51 DQM CS DQ0-DQ3 D12 DQM CS DQ0-DQ3 D12 DQ20-DQ23 DQM CS DQ0-DQ3 D5 DQM CS DQ0-DQ3 D5 DQ52-DQ55 DQM CS DQ0-DQ3 D13 DQM CS DQ0-DQ3 D13 DQ24-DQ27 DQM CS DQ0-DQ3 D6 DQM CS DQ0-DQ3 D6 DQ56-DQ59 DQM CS DQ0-DQ3 D14 DQM CS DQ0-DQ3 D14 DQ28-DQ31 DQM CS DQ0-DQ3 D7 DQM CS DQ0-DQ3 D7 DQ61-DQ63 DQM CS DQ0-DQ3 D15 DQM CS DQ0-DQ3 D15 RDQMB1 RDQMB5 RCS2 RCS3 RDQMB2 RDQMB6 RDQMB3 CLK0 RDQMB7 PLL Stacked SDRAMs D0-D17 CLK1, CLK2, CLK3 CS0-CS3 DQMB0-7 BA0, BA1 A0-A11, A12* ) RAS CAS CKE0 WE REGE 10 k Ω V CC Register 12 pF RCS0-RCS3 RDQMB0-7 RBA0, RBA1 RA0-RA11 RRAS RCAS RCKE0 RWE *) 12 pF Stacked SDRAMs D0-D17 Stacked SDRAMs D0-D17 Stacked SDRAMs D0-D17 Stacked SDRAMs D0-D17 Stacked SDRAMs D0-D17 Stacked SDRAMs D0-D17 E 2PROM (256 word x 8 Bit) SA0 SA0 SA1 SA1 SDA SA2 SA2 WP SCL SCL V CC 47 k Ω D0-D17, Reg. DLL C V SS D0-D17, Reg. DLL 1.) DQ wirding may differ from that decribed in this drawing; however DQ/DQB relationship must be maintained as shown 2.) All resistors are 10 Ω unless otherwise noted A12 is only used for 128 M x 72 organisation SPB04132 Block Diagram: Two Bank 32M × 72 & 128M × 72 SDRAM DIMM Modules HYS 72V32220GR/HYS 72V128220GR Using Stacked x4 Organized SDRAMs Data Book 7 11.99 HYS 72Vx2x0GR Registered SDRAM-Modules DC Characteristics TA = 0 to 70 °C 1); VSS = 0 V; VDD,VDDQ = 3.3 V ± 0.3 V Parameter Symbol Limit Values min. max. Unit Input High Voltage VIH 2.0 VDD + 0.3 V Input Low Voltage VIL – 0.5 0.8 V Output High Voltage (IOUT = – 4.0 mA) VOH 2.4 – V Output Low Voltage (IOUT = 4.0 mA) VOL – 0.4 V Input Leakage Current, any input (0 V < VIN < 3.6 V, all other inputs = 0 V) II(L) – 10 10 µA Output Leakage Current (DQ is disabled, 0 V < VOUT < VDD) IO(L) – 10 10 µA Capacitance TA = 0 to 70 °C 1); VDD = 3.3 V ± 0.3 V, f = 1 MHz Parameter Symbol Limit Values One Bank Modules Two Bank Modules Unit Input Capacitance (all inputs except CLK and CKE) CIN 10 20 pF Input Capacitance (CLK) CCLK 30 30 pF Input Capacitance (CKE) CCKE 17 30 pF Input/Output Capacitance (DQ0 - DQ63, CB0 - CB7) CIO 10 17 pF Input Capacitance (SCL, SA0 - 2) CSC 8 8 pF Input/Output Capacitance (SDA) CSD 8 8 pF Data Book 8 11.99 HYS 72Vx2x0GR Registered SDRAM-Modules 64 MBit SDRAM Operating Currents TA = 0 to 70 °C 1), VDD = 3.3 V ± 0.3 V (Recommended Operating Conditions unless otherwise noted) Parameter Test Condition Symbol -8 Unit Note max. Operating current 2) ICC1 – tRC = tRC(MIN.), tCK = tCK(MIN.) Outputs open, Burst Length = 4, CL = 3 All banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access x4 100 x8 110 mA mA tCK = min. ICC2P 2 mA 2) tCK = infinity ICC2PS 1 mA 2) tCK = min. ICC2N 35 mA 2) tCK = infinity ICC2NS 5 mA 2) CKE ≥ VIH(MIN.) ICC3N 45 mA 2) CKE ≤ VIL(MAX.) ICC3P 8 mA 2) Burst operating current tCK = min., Read command cycling – ICC4 Auto refresh current tCK = min., Auto Refresh command cycling – ICC5 130 mA 2) Self refresh current Self Refresh Mode, CKE = 0.2 V – ICC6 1 mA 2) Precharge stand-by current in Power Down Mode CS = VIH(MIN.), CKE ≤ VIL(MAX.) Precharge Stand-by Current in Non-Power Down Mode CS = VIH (MIN.), CKE ≥ VIH(MIN.) No operating current tCK = min., CS = VIH(MIN.), active state (max. 4 banks) Data Book 2), 3) x4 60 x8 70 9 mA mA 11.99 HYS 72Vx2x0GR Registered SDRAM-Modules 256 MBit Operating Currents TA = 0 to 70 °C 1), VDD = 3.3 V ± 0.3 V (Recommended Operating Conditions unless otherwise noted) Parameter Test Condition Symbol -8/-8A/-8B Unit Note max. – ICC1 210 mA 2) tCK = min. ICC2P 2 mA 2) tCK = min. ICC2N 19 mA 2) CKE ≥ VIH(MIN.) ICC3N 45 mA 2) CKE ≤ VIL(MAX.) ICC3P 10 mA 2) Burst operating current tCK = min., Read command cycling – ICC4 100 mA 2), 3) Auto refresh current tCK = min., Auto Refresh command cycling – ICC5 240 mA 2) Self refresh current Self Refresh Mode, CKE = 0.2 V Standard version ICC6 2.5 mA 2) Operating current tRC = tRC(MIN.), tCK = tCK(MIN.) Outputs open, Burst Length = 4, CL = 3 All banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access. Precharge stand-by current in Power Down Mode CS = VIH(MIN.), CKE ≤ VIL(MAX.) Precharge Stand-by Current in Non-Power Down Mode CS = VIH (MIN.), CKE ≥ VIH(MIN.) No operating current tCK = min., CS = VIH(MIN.), active state (max. 4 banks) Data Book 10 11.99 HYS 72Vx2x0GR Registered SDRAM-Modules AC Characteristics (SDRAM Device Specification) 4), 5) TA = 0 to 70 °C 1); VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns Parameter Symbol Limit Values -8 PC100-222 -8A PC100322 Unit Note -8B PC100323 min. max. min. max. min. max. Clock and Access times Clock Cycle Time CAS Latency = 3 CAS Latency = 2 tCK Clock Frequency CAS Latency = 3 CAS Latency = 2 fCK Access Time from Clock CAS Latency = 3 CAS Latency = 2 tAC Clock High Pulse Width 10 10 – – 10 15 – – 10 15 – – ns ns – – – 100 100 – – 100 66 – – 100 66 MHz MHz – – – 6 6 – – 6 6 – – 6 7 ns ns – tCH 3 – 3 – 3 – ns – Clock Low Pulse Width tCL 3 – 3 – 3 – ns – Transition Time tT 0.5 10 0.5 10 0.5 10 ns – Input Setup Time tIS 2 – 2 – 2 – ns – Input Hold Time tIH 1 – 1 – 1 – ns – Power Down Mode Entry Time tSB – 1 – 1 – 1 CLK – Power Down Mode Exit Setup Time tPDE 1 – 1 – 1 – CLK – Mode Register Set-up Time tRSC 2 – 2 – 2 – CLK – Transition Time tT 0.5 10 0.5 10 0.5 10 ns – Row to Column Delay Time tRCD 20 – 20 – 20 – ns – Row Precharge Time tRP 20 – 20 – 30 – ns – Row Active Time tRAS 45 100k 60 100k 60 100k ns – Row Cycle Time tRC 70 – 70 – 80 – ns – Activate (a) to Activate (b) Command Period tRRD 16 – 16 – 20 – ns – Setup and Hold Parameters Common Parameters Data Book 11 11.99 HYS 72Vx2x0GR Registered SDRAM-Modules AC Characteristics (SDRAM Device Specification) (cont’d) TA = 0 to 70 °C 1); VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns Parameter Symbol 4), 5) Limit Values -8 PC100-222 -8A PC100322 Unit Note -8B PC100323 min. max. min. max. min. max. tCCD 1 – 1 – 1 – CLK – Refresh Period tREF – 64 – 64 – 64 ms – Self Refresh Exit Time tSREX 1 – 1 – 1 – CLK 6) Data Out Hold Time tOH 3 – 3 – 3 – ns – Data Out to Low Impedance tLZ 0 – 0 – 0 – ns 7) Data Out to High Impedance tHZ 3 8 3 8 3 10 ns 7) – 2 – 2 – 2 CLK – CAS(a) to CAS(b) Command Period Refresh Cycle Read Cycle DQM Data Out Disable Latency tDQZ Write Cycle Data Input to Precharge (write recovery) tWR 2 – 2 – 2 – CLK – DQM Write Mask Latency tDQW 0 – 0 – 0 – CLK – Data Book 12 11.99 HYS 72Vx2x0GR Registered SDRAM-Modules Clock Frequency and Latency (Registered DIMM Module Specification) Parameter 8) Symbol -8 -8A -8B Unit Notes Clock Frequency max. tCK 100 100 100 MHz – Clock Cycle Time min. tCK 10 10 10 ns – CAS Latency min. tAA 3 4 4 CLK 9) RAS to CAS Delay min. tRCD 2 2 2 CLK – RAS Latency min. tRL 6 7 7 CLK 9) Precharge Time min. tRP 2 2 3 CLK – Data In to Precharge min. tDPL 2 2 2 CLK – Data In to Active/Refresh min. tDAL 5 5 5 CLK – Bank to Bank Delay Time min. tRRD 2 2 2 CLK – CAS to CAS Delay Time min. tCCD 1 1 1 CLK – Write Latency fixed tWL 1 1 1 CLK 9) DQM Write Mask Latency fixed tDQW 1 1 1 CLK – DQM Data Disable Latency fixed tDQZ 1 1 1 CLK – Clock Suspend Latency fixed tCSL 1 1 1 CLK 9) Data Book 13 11.99 HYS 72Vx2x0GR Registered SDRAM-Modules Notes 1. The registered DIMM modules are designed to operate under system operating conditions between 0-55 deg C ambient, 500 MB/sec sustained bandwidth and 0 LFM airflow. 2. These parameters depend on the cycle rate. All values are measured at 100 MHz operation frequency. Input signals are changed once during tck excepts for Icc6 and for standby currents when tck = infinity. 3. These parameters are measured with continous data stream during read access and all DQ toggling. CL=3 and BL=4 is assumed and the Vcc current is excluded. 4. An initial pause of 100 µs is required after power-up. Then a Precharge All Banks command must be given followed by eight Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. Also the on-DIMM PLL must be given enough clock cycles to stabilize before any operation can be guaranteed. 5. AC timing tests have VIL = 0.8 V and VIH = 2.0 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown. Specified tAC and tOH parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1 V/ns edge rate between 0.8 V and 2.0 V. 6. Self Refresh Exit is a synchronous operation and begins on the second positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied after the Self Refresh Exit command is registered. 7. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. 8. Due to the usage of a register device on all input and address signals, all external command cycle are delayed by one clock (Reg-DIMM Latency = 1) on the module board. 9. Delayed by one clock cycle due to the use of the register device. t CH 2.4 V 0.4 V CLOCK t CL t SETUP tT t HOLD INPUT 1.4 V t AC t LZ t AC I/O t OH 50 pF OUTPUT 1.4 V Measurement conditions for tAC and tOH t HZ SPT03404 A serial presence detect storage device - E 2PROM 34C02 - is assembled onto the module. Information about the module configuration, speed, etc. is written into the E2PROM device during module production using a serial presence detect protocol (I 2C synchronous 2-wire bus) Data Book 14 11.99 HYS 72Vx2x0GR Registered SDRAM-Modules SPD-Table for -8 Registered DIMM Modules with PLL Description SPD Entry Value 0 1 2 3 Number of SPD Bytes Total Bytes in Serial PD Memory Type Number of Row Addresses (without BS bits) Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont’d) Module Interface Levels Cycle Time at CL = 3 Access Time from Clock at CL = 3 DIMM Config (Error Det/ Corr.) Refresh Rate/Type 128 256 SDRAM 12/13 80 08 04 0C 80 08 04 0C 80 08 04 0C 80 08 04 0D 80 08 04 0D 80 08 04 0D 9/10/11 09 0A 0A 0A 0B 0B 1 72 0 01 48 00 01 48 00 02 48 00 01 48 00 01 48 00 02 48 00 LVTTL 10.0 ns 6.0 ns 01 A0 60 01 A0 60 01 A0 60 01 A0 60 01 A0 60 01 A0 60 ECC 02 02 02 02 02 02 Self-Refresh, 80 15.6/7.8 µs x4, x8 08 n/a/x4 08 80 80 82 82 82 04 04 04 04 08 08 04 04 04 04 1 CLK 1, 2, 4, 8 & (full page) 4 01 8F 01 8F 01 8F 01 0F 01 0F 01 0F 04 04 04 04 04 04 2&3 06 06 06 06 06 06 0 0 with PLL 01 01 16 01 01 16 01 01 16 01 01 16 01 01 16 01 01 16 VDD tol +/– 0E 0E 0E 0E 0E 0E 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 SDRAM Width, Primary Error Checking SDRAM Data Width Minimum tCCD Burst Length Supported Number of SDRAM Banks SDRAM Supported CAS Latencies SDRAM CS Latencies SDRAM WE Latencies SDRAM DIMM Module Attributes SDRAM Device Attributes Data Book Hex 64 MB with PLL 1 Bank -8 128 MB with PLL 1 Bank -8 256 MB with PLL 2 Banks -8 256 MB with PLL 1 Bank-8 512 MB with PLL 1 Bank -8 1 GB with PLL 2 Banks -8 Byte# 10% 15 11.99 HYS 72Vx2x0GR Registered SDRAM-Modules SPD-Table for -8 Registered DIMM Modules with PLL (cont’d) Description 23 Min. Clock Cycle Time at CL = 2 24 Max. Data Access Time from Clock for CL = 2 25 Min. Clock Cycle Time at CL = 1 26 Max. Data Access Time from Clock at CL = 1 27 SDRAM Minimum tRP 28 SDRAM Minimum tRRD 29 SDRAM Minimum tRCD 30 SDRAM Minimum tRAS 31 Module Bank Density (per bank) 32 SDRAM Input Setup Time 33 SDRAM Input Hold Time 34 SDRAM Data Input Setup Time 35 SDRAM Data Input Hold Time 36-61 Superset Information (may be used in future) 62 SPD Revision 63 Checksum for Bytes 0 - 62 64-125 Manufacturer’s Information 126 Frequency Specification 127 Details of Clocks 128+ Unused Storage Locations Data Book SPD Entry Value Hex 64 MB with PLL 1 Bank -8 128 MB with PLL 1 Bank -8 256 MB with PLL 2 Banks -8 256 MB with PLL 1 Bank-8 512 MB with PLL 1 Bank -8 1 GB with PLL 2 Banks -8 Byte# 10 ns A0 A0 A0 A0 A0 A0 6 ns 60 60 60 60 60 60 not supp. FF FF FF FF FF FF not supp. FF FF FF FF FF FF 20 ns 16 ns 20 ns 45 ns 64/128/256/ 512 MByte 2 ns 14 10 14 2D 10 14 10 14 2D 20 14 10 14 2D 20 14 10 14 2D 40 14 10 14 2D 80 14 10 14 2D 80 20 20 20 20 20 20 1 ns 2 ns 10 20 10 20 10 20 10 20 10 20 10 20 1 ns 10 10 10 10 10 10 – FF FF FF FF FF FF 1.2 – 12 08 12 11 12 12 12 BC 12 F5 12 F6 – XX XX XX XX XX XX 100 MHz – – 64 8F FF 64 8F FF 64 8F FF 64 8F FF 64 8F FF 64 8F FF 16 11.99 HYS 72Vx2x0GR Registered SDRAM-Modules SPD-Table for -8A/-8B Registered DIMM Modules with PLL Description SPD Entry Value 0 1 Number of SPD Bytes Total Bytes in Serial PD Memory Type Number of Row Addresses (without BS bits) Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont’d) Module Interface Levels Cycle Time at CL = 3 Access Time from Clock at CL = 3 DIMM Config (Error Det/Corr.) Refresh Rate/Type 128 256 80 08 80 08 80 08 80 08 80 08 80 08 SDRAM 13 04 0D 04 0D 04 0D 04 0D 04 0D 04 0D 10/11 0A 0B 0B 0A 0B 0B 1 01 01 02 01 01 02 72 0 48 00 48 00 48 00 48 00 48 00 48 00 LVTTL 01 01 01 01 01 01 10.0 ns 6.0 ns A0 60 A0 60 A0 60 A0 60 A0 60 A0 60 ECC 02 02 02 02 02 02 Self82 Refresh, 15.6/7.8 µs x4, x8 08 82 82 82 82 82 04 04 08 04 04 n/a/x4 08 04 04 08 04 04 1 CLK 01 1, 2, 4, 8 & 0F (full page) 4 04 01 0F 01 0F 01 0F 01 0F 01 0F 04 04 04 04 04 2&3 06 06 06 06 06 06 0 01 01 01 01 01 01 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SDRAM Width, Primary Error Checking SDRAM Data Width Minimum tCCD Burst Length Supported Number of SDRAM Banks SDRAM Supported CAS Latencies SDRAM CS Latencies Data Book Hex 256 MB with PLL 1 Bank -8A 512 MB with PLL 1 Bank -8A 1 GB with PLL 2 Banks -8A 256 MB with PLL 1 Bank -8B 512 MB with PLL 1 Bank -8B 1 GB with PLL 2 Banks -8B Byte# 17 11.99 HYS 72Vx2x0GR Registered SDRAM-Modules SPD-Table for -8A/-8B Registered DIMM Modules with PLL (cont’d) Description SPD Entry Value 20 21 SDRAM WE Latencies SDRAM DIMM Module Attributes SDRAM Device Attributes Min. Clock Cycle Time at CL = 2 Max. Data Access Time from Clock for CL = 2 Min. Clock Cycle Time at CL = 1 Max. Data Access Time from Clock at CL = 1 SDRAM Minimum tRP SDRAM Minimum tRRD SDRAM Minimum tRCD SDRAM Minimum tRAS Module Bank Density (per bank) 0 with PLL 22 23 24 25 26 27 28 29 30 31 32 33 34 SDRAM Input Setup Time SDRAM Input Hold Time SDRAM Data Input Setup Time Data Book Hex 256 MB with PLL 1 Bank -8A 512 MB with PLL 1 Bank -8A 1 GB with PLL 2 Banks -8A 256 MB with PLL 1 Bank -8B 512 MB with PLL 1 Bank -8B 1 GB with PLL 2 Banks -8B Byte# 01 16 01 16 01 16 01 16 01 16 01 16 VDD tol +/– 0E 0E 0E 0E 0E 0E 10% 15 ns F0 F0 F0 F0 F0 F0 6/7 ns 60 60 60 70 70 70 not supp. FF FF FF FF FF FF not supp. FF FF FF FF FF FF 20 / 30 ns 20 ns 20 ns 60 ns 64/128/ 256/512 MByte 2 ns 14 14 14 3C 40 14 14 14 3C 80 14 14 14 3C 80 1E 14 14 3C 40 1E 14 14 3C 80 1E 14 14 3C 80 20 20 20 20 20 20 1 ns 10 10 10 10 10 10 2 ns 20 20 20 20 20 20 18 11.99 HYS 72Vx2x0GR Registered SDRAM-Modules SPD-Table for -8A/-8B Registered DIMM Modules with PLL (cont’d) Description 35 SDRAM Data Input Hold Time 36-61 Superset Information (may be used in future) 62 SPD Revision 63 Checksum for Bytes 0 - 62 64-125 Manufacturer’s Information 126 Frequency Specification 127 Details of Clocks 128+ Unused Storage Locations Data Book SPD Entry Value Hex 256 MB with PLL 1 Bank -8A 512 MB with PLL 1 Bank -8A 1 GB with PLL 2 Banks -8A 256 MB with PLL 1 Bank -8B 512 MB with PLL 1 Bank -8B 1 GB with PLL 2 Banks -8B Byte# 1 ns 10 10 10 10 10 10 – FF FF FF FF FF FF 1.2 – 12 1F 12 58 12 59 12 09 12 72 12 73 – XX XX XX XX XX XX 100 MHz 64 64 64 64 64 64 – – 8F FF 8F FF 8F FF 8F FF 8F FF 8F FF 19 11.99 HYS 72Vx2x0GR Registered SDRAM-Modules Package Outlines Module Package JEDEC MO-161 64 & 256 MByte Registered Module 133.35 127.35 38.1 4 Register 3 Register 1 10 11 6.35 3 1.27 40 41 6.35 84 1.27± 0.1 42.18 66.68 3.125 2 94 95 124 125 17.78 85 168 4 ± 0.1 PLL 2.54 min. 0.25 max. Detail of Contacts 1 +0.5 1.27 Data Book GLD09186 20 11.99 HYS 72Vx2x0GR Registered SDRAM-Modules Module Package JEDEC MO-161 128 & 512 MByte Registered Module 133.35 127.35 43.18 4 3 PLL 1 10 11 6.35 3 1.27 40 41 6.35 84 1.27± 0.1 42.18 66.68 3.125 2 94 95 124 17.78 85 125 Register 4 ± 0.1 Register 168 2.54 min. 0.25 max. Detail of Contacts 1+0.5 1.27 Data Book GLD09185 21 11.99 HYS 72Vx2x0GR Registered SDRAM-Modules Module Package JEDEC MO-161 256 MByte & 1 GByte Registered DIMM Module with Stacked SDRAMs 133.35 127.35 43.18 8 max. 4 3 PLL 1 10 11 6.35 3 1.27 40 41 6.35 84 1.27± 0.1 42.18 66.68 3.125 2 94 95 124 17.78 85 125 Register 4 ± 0.1 Register 168 2.54 min. 0.25 max. Detail of Contacts GLD09190 1+0.5 1.27 Data Book 22 11.99 HYS 72Vx2x0GR Registered SDRAM-Modules Functional Description All 168-pin Registered DIMMs conform to a compatible set of timing and operation characteristics intended to comply with the 100 MHz standards. The Registered DIMMs achieve high speed data transfer rate up to 100 MHz. All control and address signals are synchronized with the positive edge of externally supplied clocks and are registered on-DIMM and hence delayed by one clock cycle in arriving at the SDRAM devices. The use of the on-board register reduces the capacitive loading of the DIMM on input control and address signals. The SDRAM device data lines (DQ) are connected directly to the DIMM tabs through 10 Ohm series resistors. All the following timing diagrams and explanations show DIMM operation at the tabs, not SDRAM operation. The picture below depicts an overview of the effect of the Registered Mode on the data outputs (DQs) for a Read operation. Without the registers, the data is delayed according to the device CAS latency, in the case two clocks. With the register, the data is delayed according to the device CAS latency plus an additional clock cycle. This is know as the DIMM CAS latency, and in this example is four three. The data path can be thought of as a pipeline in which the register effectively lengthens the pipe by one clock cycle. Registered DIMM Burst Read Operation (BL = 4) T0 T1 T2 T3 T4 T5 T6 Read A NOP NOP NOP NOP NOP NOP CLK Command Device CAS latency = 2 t CK2 , DQ’s DIMM CAS latency = 3 t CK3 , DQ’s DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 Added for on-DIMM pipeline register One Clock Reg-DIMM Latency = 1 SPT03968 In case of a Burst Write Command the data-in is delayed one clock due the op-DIMM pipeline register also. Therefore, data for the first Burst Write cycle must be applied on the DQ pins on the next clock cycle after the Write command is issued. the remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored. Data Book 23 11.99 HYS 72Vx2x0GR Registered SDRAM-Modules T0 T1 T2 T3 T4 T5 T6 T7 T8 NOP Write A NOP NOP NOP NOP NOP NOP NOP DIN A0 DIN A1 DIN A2 DIN A3 don’t care CLK Command DQ’s The first data element and the Write are registered on the next clock edge Reg-DIMM Latency = 1 CLK Extra data is ignored after termination of a Burst. SPT03969 Registered DIMM Burst Write Operation (BL = 4) Data Book 24 11.99 HYS 72Vx2x0GR Registered SDRAM-Modules Rev. Changes 12.98 12.98 2.98 2.98 18.4.1999 12.5.99 16.6.99 13.8.99 2.9.99 3.9.99 28.9.99 19.10.99 30.11.99 Data Book Byte 12 changed from 80h (15.6 µs) to 82h (7.8 µs), CheckSum Byte 63 ajusted, comment added to page 2 “will change to Rev 1.2 in future” Byte 16 changed from 8Fh to 0Fh (no full page support for 256M based modules). Spec reference changed to INTEL Rev. 1.2 Values for discrete capacitors on CLK0 inputs changed to 12pF according to INTEL Rev.1.2 specification, Ioh & Iol changed to 4mA Compliance Code changed from 620R to 622R accroding to INTELs Rev. 1.2 specification -8A speed sort added for 256M based modules -8B speed sort removed for 64M based modules Infineon logo added SPD updated according to new speedsort for 256M devices Some ICC currents changed due to new inputs and measurements Input capacitance changed according to new measurements Input capacitance changed according to new measurements with flexframe stacked components Typoo on page 2, 64Mx72 to 128Mx72 corrected Changed to data book version from R&L 1 GByte module thickness 4 to 8 mm changes, (masked) CL 2 frequency changed to 66 MHz for -8A parts Typoo in input capacitance corrected (input stacked from 10 to 20 pF) Notes renumbered, Note 1) added, explaining maximum operation temperature for registered DIMM modules 25 11.99