INTEGRATED CIRCUITS PZ5032 32 macrocell CPLD Product specification IC27 Data Handbook 1997 Feb 20 Philips Semiconductors Product specification 32 macrocell CPLD PZ5032 FEATURES DESCRIPTION • Industry’s first TotalCMOS PLD – both CMOS design and The PZ5032 CPLD (Complex Programmable Logic Device) is the first in a family of Fast Zero Power (FZP) CPLDs from Philips Semiconductors. These devices combine high speed and zero power in a 32 macrocell CPLD. With the FZP design technique, the PZ5032 offers true pin-to-pin speeds of 6ns, while simultaneously delivering power that is less than 75µA at standby without the need for ‘turbo bits’ or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any competing CPLD – 70% lower at 50MHz. These devices are the first TotalCMOS PLDs, as they use both a CMOS process technology and the patented full CMOS FZP design technique. For 3V applications, Philips also offers the high speed PZ3032 CPLD that offers these features in a full 3V implementation. process technologies • Fast Zero Power (FZP) design technique provides ultra-low power and very high speed • High speed pin-to-pin delays of 6ns • Ultra-low static power of less than 75µA • Dynamic power that is 70% lower at 50MHz than competing devices • 100% routable with 100% utilization while all pins and all macrocells are fixed • Deterministic timing model that is extremely simple to use • 2 clocks with programmable polarity at every macrocell • Support for complex asynchronous clocking • Innovative XPLA architecture combines high speed with The Philips FZP CPLDs introduce the new patent-pending XPLA (eXtended Programmable Logic Array) architecture. The XPLA architecture combines the best features of both PLA and PAL type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. The XPLA structure in each logic block provides a fast 6ns PAL path with 5 dedicated product terms per output. This PAL path is joined by an additional PLA structure that deploys a pool of 32 product terms to a fully programmable OR array that can allocate the PLA product terms to any output in the logic block. This combination allows logic to be allocated efficiently throughout the logic block and supports as many as 37 product terms on an output. The speed with which logic is allocated from the PLA array to an output is only 2ns, regardless of the number of PLA product terms used, which results in worst case tPD’s of only 8ns from any pin to any other pin. In addition, logic that is common to multiple outputs can be placed on a single PLA product term and shared across multiple outputs via the OR array, effectively increasing design density. extreme flexibility • 1000 erase/program cycles guaranteed • 20 years data retention guaranteed • Logic expandable to 37 product terms • PCI compliant • Advanced 0.5µ E2CMOS process • Security bit prevents unauthorized access • Design entry and verification using industry standard and Philips CAE tools • Reprogrammable using industry standard device programmers • Innovative Control Term structure provides either sum terms or product terms in each logic block for: – Programmable 3-State buffer – Asynchronous macrocell register preset/reset The PZ5032 CPLDs are supported by industry standard CAE tools (Cadence, Mentor, Synopsys, Synario, Viewlogic, OrCAD), using text (Abel, VHDL, Verilog) and/or schematic entry. Design verification uses industry standard simulators for functional and timing simulation. Development is supported on personal computer, Sparc, and HP platforms. Device fitting uses either Minc or Philips Semiconductors-developed tools. • Programmable global 3-State pin facilitates ‘bed of nails’ testing without using logic resources • Available in both PLCC and TQFP packages • Available in both Commercial and Industrial grades Table 1. PZ5032 Features The PZ5032 CPLD is reprogrammable using industry standard device programmers from vendors such as Data I/O, BP Microsystems, SMS, and others. PZ5032 Usable gates 1000 Maximum inputs 36 Maximum I/Os 32 Number of macrocells 32 I/O macrocells 32 Buried macrocells Propagation delay (ns) Packages 0 6.0 44-pin PLCC, 44-pin TQFP PAL is a registered trademark of Advanced Micro Devices, Inc. 1997 Feb 20 2 853–1853 17781 Philips Semiconductors Product specification 32 macrocell CPLD PZ5032 ORDERING INFORMATION DESCRIPTION DRAWING NUMBER PZ5032–6A44 ORDER CODE 44-pin PLCC, 6ns tPD DESCRIPTION Commercial temp range, 5 volt power supply, ± 5% SOT187-2 PZ5032–7A44 44-pin PLCC, 7.5ns tPD Commercial temp range, 5 volt power supply, ± 5% SOT187-2 PZ5032–10A44 44-pin PLCC, 10ns tPD Commercial temp range, 5 volt power supply, ± 5% SOT187-2 PZ5032I7A44 44-pin PLCC, 7.5ns tPD Industrial temp range, 5 volt power supply, ± 10% SOT187-2 PZ5032I10A44 44-pin PLCC, 10ns tPD Industrial temp range, 5 volt power supply, ± 10% SOT187-2 PZ5032–6BC 44-pin TQFP, 6ns tPD, Commercial temp range, 5 volt power supply, ± 5% SOT376-1 PZ5032–7BC 44-pin TQFP, 7.5ns tPD Commercial temp range, 5 volt power supply, ± 5% SOT376-1 PZ5032–10BC 44-pin TQFP, 10ns tPD Commercial temp range, 5 volt power supply, ± 5% SOT376-1 PZ5032I7BC 44-pin TQFP, 7.5ns tPD Industrial temp range, 5 volt power supply, ± 10% SOT376-1 PZ5032I10BC 44-pin TQFP, 10ns tPD Industrial temp range, 5 volt power supply, ± 10% SOT376-1 PRODUCT terms, and are used to control the preset/reset and output enables of the 16 macrocells’ flip-flops. The PAL array consists of a programmable AND array with a fixed OR array, while the PLA array consists of a programmable AND array with a programmable OR array. The PAL array provides a high speed path through the array, while the PLA array provides increased product term density. XPLA ARCHITECTURE Figure 1 shows a high level block diagram of a 64 macrocell device implementing the XPLA architecture. The XPLA architecture consists of logic blocks that are interconnected by a Zero-power Interconnect Array (ZIA). The ZIA is a virtual crosspoint switch. Each logic block is essentially a 36V16 device with 36 inputs from the ZIA and 16 macrocells. Each logic block also provides 32 ZIA feedback paths from the macrocells and I/O pins. Each macrocell has 5 dedicated product terms from the PAL array. The pin-to-pin tPD of the PZ5032 device through the PAL array is 6ns. This performance is equivalent to the fastest 5 volt CPLD available today. If a macrocell needs more than 5 product terms, it simply gets the additional product terms from the PLA array. The PLA array consists of 32 product terms, which are available for use by all 16 macrocells. The additional propagation delay incurred by a macrocell using 1 or all 32 PLA product terms is just 2ns. So the total pin-to-pin tPD for the PZ5032 using 6 to 37 product terms is 8ns (6ns for the PAL + 2ns for the PLA). From this point of view, this architecture looks like many other CPLD architectures. What makes the CoolRunner family unique is what is inside each logic block and the design technique used to implement these logic blocks. The contents of the logic block will be described next. Logic Block Architecture Figure 2 illustrates the logic block architecture. Each logic block contains control terms, a PAL array, a PLA array, and 16 macrocells. the 6 control terms can individually be configured as either SUM or MC0 MC1 I/O MC0 LOGIC BLOCK 36 36 LOGIC BLOCK MC15 MC1 I/O MC15 16 16 16 16 ZIA MC0 MC1 I/O MC0 LOGIC BLOCK 36 36 LOGIC BLOCK MC15 MC1 I/O MC15 16 16 16 16 SP00439 Figure 1. Philips XPLA CPLD Architecture 1997 Feb 20 3 Philips Semiconductors Product specification 32 macrocell CPLD PZ5032 36 ZIA INPUTS 6 CONTROL TO 16 MACROCELLS 5 PAL ARRAY PLA ARRAY (32) SP00435 Figure 2. Philips Logic Block Architecture 1997 Feb 20 4 Philips Semiconductors Product specification 32 macrocell CPLD PZ5032 to control the Output Enable of the macrocell’s output buffers. The reason there are as many control terms dedicated for the Output Enable of the macrocell is to insure that all CoolRunner devices are PCI compliant. The macrocell’s output buffers can also be always enabled or disabled. All CoolRunner devices also provide a Global Tri-State (GTS) pin, which, when pulled Low, will 3-State all the outputs of the device. This pin is provided to support “In-Circuit Testing” or “Bed-of-Nails Testing”. Macrocell Architecture Figure 3 shows the architecture of the macrocell used in the CoolRunner family. The macrocell consists of a flip-flop that can be configured as either a D or T type. A D-type flip-flop is generally more useful for implementing state machines and data buffering. A T-type flip-flop is generally more useful in implementing counters. All CoolRunner family members provide both synchronous and asynchronous clocking and provide the ability to clock off either the falling or rising edges of these clocks. These devices are designed such that the skew between the rising and falling edges of a clock are minimized for clocking integrity. There are 2 clocks (CLK0 and CLK1) available on the PZ5032 device. Clock 0 (CLK0) is designated as the “synchronous” clock and must be driven by an external source. Clock 1 (CLK1) can either be used as a synchronous clock (driven by an external source) or as an asynchronous clock (driven by a macrocell equation). There are two feedback paths to the ZIA: one from the macrocell, and one from the I/O pin. The ZIA feedback path before the output buffer is the macrocell feedback path, while the ZIA feedback path after the output buffer is the I/O pin ZIA path. When the macrocell is used as an output, the output buffer is enabled, and the macrocell feedback path can be used to feedback the logic implemented in the macrocell. When the I/O pin is used as an input, the output buffer will be 3-Stated and the input signal will be fed into the ZIA via the I/O feedback path, and the logic implemented in the buried macrocell can be fed back to the ZIA via the macrocell feedback path. It should be noted that unused inputs or I/Os should be properly terminated. Two of the control terms (CT0 and CT1) are used to control the Preset/Reset of the macrocell’s flip-flop. The Preset/Reset feature for each macrocell can also be disabled. Note that the Power-on Reset leaves all macrocells in the “zero” state when power is properly applied. The other 4 control terms (CT2–CT5) can be used TO ZIA D/T CLK0 Q INIT (P or R) GTS CLK0 GND CLK1 CT0 CLK1 CT1 GND CT2 CT3 CT4 CT5 VCC GND SP00440 Figure 3. PZ5032 Macrocell Architecture 1997 Feb 20 5 Philips Semiconductors Product specification 32 macrocell CPLD PZ5032 product terms or less, the tPD = 6ns, the tSU = 4.5ns, and the tCO = 5ns. If an output is using 6 to 37 product terms, an additional 2ns must be added to the tPD and tSU timing parameters to account for the time to propagate through the PLA array. Simple Timing Model Figure 4 shows the CoolRunner Timing Model. The CoolRunner timing model looks very much like a 22V10 timing model in that there are three main timing parameters, including tPD, tSU, and tCO. In other competing architectures, the user may be able to fit the design into the CPLD, but is not sure whether system timing requirements can be met until after the design has been fit into the device. This is because the timing models of competing architectures are very complex and include such things as timing dependencies on the number of parallel expanders borrowed, sharable expanders, varying number of X and Y routing channels used, etc. In the XPLA architecture, the user knows up front whether the design will meet system timing requirements. This is due to the simplicity of the timing model. For example, in the PZ5032 device, the user knows up front that if a given output uses 5 TotalCMOS Design Technique for Fast Zero Power Philips is the first to offer a TotalCMOS CPLD, both in process technology and design technique. Philips employs a cascade of CMOS gates to implement its Sum of Products instead of the traditional sense amp approach. This CMOS gate implementation allows Philips to offer CPLDs which are both high performance and low power, breaking the paradigm that to have low power, you must have low performance. Refer to Figure 5 and Table 2 showing the IDD vs. Frequency of our PZ5032 TotalCMOS CPLD. tPD_PAL = COMBINATORIAL PAL ONLY tPD_PLA = COMBINATORIAL PAL + PLA INPUT PIN REGISTERED tSU_PAL = PAL ONLY tSU_PLA = PAL + PLA INPUT PIN D Q OUTPUT PIN REGISTERED tCO OUTPUT PIN CLOCK SP00441 Figure 4. CoolRunner Timing Model TYPICAL IDD (mA) FREQUENCY (MHz) SP00442 Figure 5. IDD vs. Frequency @ VDD = 5.0V, 25°C Table 2. IDD vs Frequency VDD = 5.00V FREQ (MHz) 0 20 40 60 80 100 120 140 160 180 Typical IDD( mA) 0.05 9.62 17.5 25.6 32.5 40.8 49.0 55.9 64.2 75.2 1997 Feb 20 6 Philips Semiconductors Product specification 32 macrocell CPLD PZ5032 ABSOLUTE MAXIMUM RATINGS1 MIN. MAX. UNIT VDD Supply voltage PARAMETER –0.5 7.0 V VI Input voltage –1.2 VDD+0.5 V VOUT Output voltage –0.5 VDD+0.5 V IIN Input current –30 30 mA IOUT Output current –100 100 mA TJ Maximum junction temperature –40 150 °C Tstr Storage temperature –65 150 °C SYMBOL NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification is not implied. OPERATING RANGE 1997 Feb 20 PRODUCT GRADE TEMPERATURE VOLTAGE Commercial 0 to +70°C 5.0 ±5% V Industrial –40 to +85°C 5.0 ±10% V 7 Philips Semiconductors Product specification 32 macrocell CPLD PZ5032 DC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES Commercial: 0°C ≤ Tamb ≤ +70°C; 4.75V ≤ VDD ≤ 5.25V SYMBOL PARAMETER TEST CONDITIONS MIN. MAX. UNIT 0.8 V VIL Input voltage low VDD = 4.75V VIH Input voltage high VDD = 5.25V VI Input clamp voltage VDD = 4.75V, IIN = –18mA –1.2 V VOL Output voltage low VDD = 4.75V, IOL = 12mA 0.5 V VOH Output voltage high VDD = 4.75V, IOH = –12mA 2.4 IIL Input leakage current low VDD = 5.25V (except CKO), VIN = 0.4V –10 10 µA IIH Input leakage current high VDD = 5.25V, VIN = 3.0V –10 10 µA IIL Clock input leakage current VDD = 5.25V, VIN = 0.4V –10 10 µA IOZL 3-Stated output leakage current low VDD = 5.25V, VIN = 0.4V –10 10 µA IOZH 3-Stated output leakage current high VDD = 5.25V, VIN = 3.0V –10 10 µA IDDQ Standby current 2.0 V V VDD = 5.25V, Tamb = 0°C 75 µA VDD = 5.25V, Tamb = 0°C @ 1MHz 3 mA IDDD1 Dynamic current IOS Short circuit output current CIN Input pin capacitance Tamb = 25°C, f = 1MHz CCLK Clock input capacitance Tamb = 25°C, f = 1MHz VDD = 5.25V, Tamb = 0°C @ 50MHz 1 pin at a time for no longer than 1 second –50 5 30 mA –200 mA 8 pF 12 pF CI/O I/O pin capacitance Tamb = 25°C, f = 1MHz 10 pF NOTE: 1. This parameter measured with a 16–bit, loadable up/down counter loaded into every logic block, with all outputs enabled and unloaded. Inputs are tied to VDD or ground. This parameter guaranteed by design and characterization, not testing. AC ELECTRICAL CHARACTERISTICS1 FOR COMMERCIAL GRADE DEVICES Commercial: 0°C ≤ Tamb ≤ +70°C; 4.75V ≤ VDD ≤ 5.25V SYMBOL –6 PARAMETER –7 –10 MIN. MAX. MIN. MAX. MIN. MAX. UNIT tPD_PAL Propagation delay time, input (or feedback node) to output through PAL 2 6 2 7.5 2 10 ns tPD_PLA Propagation delay time, input (or feedback node) to output through PAL & PLA 3 8 3 10 3 12.5 ns tCO Clock to out delay time 2 5.5 2 7 2 9 ns tSU_PAL Setup time (from input or feedback node) through PAL 4 tSU_PLA Setup time (from input or feedback node) through PAL + PLA 6 tH Hold time tCH Clock High time 3 4 5 tCL Clock Low time 3 4 5 tR Input rise time 20 20 20 tF Input fall time 20 20 20 fMAX1 Maximum FF toggle rate2 fMAX2 Maximum internal frequency2 fMAX3 Maximum external frequency2 tBUF Output buffer delay time 1.5 1.5 1.5 ns tPDF_PAL Input (or feedback node) to internal feedback node delay time through PAL 4.5 6 8.5 ns tPDF_PLA Input (or feedback node) to internal feedback node delay time through PAL + PLA 6.5 8.5 11 ns tCF Clock to internal feedback node delay time 4 5.5 7.5 ns tINIT Delay from valid VDD to valid reset 50 50 50 µs tER Input to output disable3 11 12.5 15 ns tEA Input to output valid 11 12.5 15 ns tRP Input to register preset 11 12.5 15 ns tRR Input to register reset 14 15.5 18 ns (1/tCH + tCL) 8 8 0 ns 10.5 0 ns 0 ns ns ns ns ns 167 125 100 MHz (1/tSUPAL + tCF) 125 91 64 MHz (1/tSUPAL + tCO) 105 NOTES: 1. Specifications measured with one output switching. See Figure 6 and Table 3 for derating. 2. This parameter guaranteed by design and characterization, not by test. 3. Output CL = 5pF. 1997 Feb 20 5.5 8 80 59 MHz Philips Semiconductors Product specification 32 macrocell CPLD PZ5032 DC ELECTRICAL CHARACTERISTICS FOR INDUSTRIAL GRADE DEVICES Industrial: –40°C ≤ Tamb ≤ +85°C; 4.5V ≤ VDD ≤ 5.5V SYMBOL PARAMETER TEST CONDITIONS MIN. MAX. UNIT 0.8 V VIL Input voltage low VDD = 4.5V VIH Input voltage high VDD = 5.5V VI Input clamp voltage VDD = 4.5V, IIN = –18mA –1.2 V VOL Output voltage low VDD = 4.5V, IOL = 12mA 0.5 V VOH Output voltage high VDD = 4.5V, IOH = –12mA 2.4 IIL Input leakage current low VDD = 5.5V (except CKO), VIN = 0.4V –10 10 µA IIH Input leakage current high VDD = 5.5V, VIN = 3.0V –10 10 µA IIL Clock input leakage current VDD = 5.5V, VIN = 0.4V –10 10 µA IOZL 3-Stated output leakage current low VDD = 5.5V, VIN = 0.4V –10 10 µA IOZH 3-Stated output leakage current high VDD = 5.5V, VIN = 3.0V –10 10 µA IDDQ Standby current 2.0 V V VDD = 5.5V, Tamb = –40°C 95 µA VDD = 5.5V, Tamb = –40°C @ 1MHz 4 mA IDDD1 Dynamic current IOS Short circuit output current CIN Input pin capacitance Tamb = 25°C, f = 1MHz CCLK Clock input capacitance Tamb = 25°C, f = 1MHz CI/O I/O pin capacitance Tamb = 25°C, f = 1MHz VDD = 5.5V, Tamb = –40°C @ 50MHz 1 pin at a time for no longer than 1 second –50 5 35 mA –230 mA 8 pF 12 pF 10 pF NOTE: 1. This parameter measured with a 16–bit, loadable up/down counter loaded into every logic block, with all outputs enabled and unloaded. Inputs are tied to VDD or ground. This parameter guaranteed by design and characterization, not testing. AC ELECTRICAL CHARACTERISTICS1 FOR INDUSTRIAL GRADE DEVICES Industrial: –40°C ≤ Tamb ≤ +85°C; 4.5V ≤ VDD ≤ 5.5V SYMBOL I7 PARAMETER I10 MIN. MAX. MIN. MAX. UNIT tPD_PAL Propagation delay time, input (or feedback node) to output through PAL 2 7.5 2 10 ns tPD_PLA Propagation delay time, input (or feedback node) to output through PAL & PLA 3 9.5 3 12.5 ns tCO Clock to out delay time 2 6 2 9 ns tSU_PAL Setup time (from input or feedback node) through PAL 5 8 tSU_PLA Setup time (from input or feedback node) through PAL + PLA 7 10.5 tH Hold time tCH Clock High time 4 5 tCL Clock Low time 4 5 tR Input rise time 20 20 tF Input fall time 20 20 fMAX1 Maximum FF toggle rate2 fMAX2 Maximum internal frequency2 fMAX3 Maximum external frequency2 tBUF Output buffer delay time tPDF_PAL Input (or feedback node) to internal feedback node delay time through PAL tPDF_PLA Input (or feedback node) to internal feedback node delay time through PAL + PLA tCF Clock to internal feedback node delay time tINIT Delay from valid VDD to valid reset tER 0 (1/tCH + tCL) ns ns 0 ns ns ns ns ns 125 100 MHz (1/tSUPAL + tCF) 105 64 MHz (1/tSUPAL + tCO) 91 59 MHz 1.5 1.5 ns 6 8.5 ns 8 11 ns 4.5 7.5 ns 50 50 µs Input to output disable3 12 15 ns tEA Input to output valid 12 15 ns tRP Input to register preset 12 15 ns tRR Input to register reset 14 18 ns NOTES: 1. Specifications measured with one output switching. See Figure 6 and Table 3 for derating. 2. This parameter guaranteed by design and characterization, not by test. 3. Output CL = 5pF. 1997 Feb 20 9 Philips Semiconductors Product specification 32 macrocell CPLD PZ5032 SWITCHING CHARACTERISTICS The test load circuit and load values for the AC Electrical Characteristics are illustrated below. VDD S1 COMPONENT VALUES R1 470Ω R2 250Ω C1 35pF MEASUREMENT S1 S2 tPZH Open Closed tPZL Closed Closed tP Closed Closed R1 VIN VOUT R2 C1 S2 NOTE: For tPHZ and tPLZ C = 5pF, and 3-State levels are measured 0.5V from steady state active level. SP00476 ns 6.60 VOLTAGE WAVEFORM VDD = 5V, 25°C +3.0V 90% 6.20 10% 0V tR TYPICAL tF 1.5ns 5.80 1.5ns MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. 5.40 Input Pulses 5.00 4.60 1 2 4 8 16 12 SP00448A Figure 6. tPD_PAL vs Outputs switching Table 3. tPD_PAL vs # of Outputs switching VDD = 5.00V # of Outputs 1 2 4 8 12 16 Typical (ns) 5.1 5.2 5.5 5.9 6.1 6.3 1997 Feb 20 10 SP00368 Philips Semiconductors Product specification 32 macrocell CPLD PZ5032 PIN DESCRIPTIONS Package Thermal Characteristics Philips Semiconductors uses the Temperature Sensitive Parameter (TSP) method to test thermal resistance. This method meets Mil-Std-883C Method 1012.1 and is described in Philips 1995 IC Package Databook. Thermal resistance varies slightly as a function of input power. As input power increases, thermal resistance changes approximately 5% for a 100% change in power. PZ5032 – 44-Pin Plastic Leaded Chip Carrier 6 1 40 7 39 Figure 7 is a derating curve for the change in ΘJA with airflow based on wind tunnel measurements. It should be noted that the wind flow dynamics are more complex and turbulent in actual applications than in a wind tunnel. Also, the test boards used in the wind tunnel contribute significantly to forced convection heat transfer, and may not be similar to the actual circuit board, especially in size. PLCC 17 29 28 18 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Function IN1 IN3 VDD I/O–A0–CK1 I/O–A1 I/O–A2 I/O–A3 I/O–A4 I/O–A5 GND I/O–A6 I/O–A7 I/O–A8 I/O–A9 VDD Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function I/O–A10 I/O–A11 I/O–A12 I/O–A13 I/O–A14 I/O–A15 GND VDD I/O–B15 I/O–B14 I/O–B13 I/O–B12 I/O–B11 I/O–B10 GND Function I/O–B9 I/O–B8 I/O–B7 I/O–B6 VDD I/O–B5 I/O–B4 I/O–B3 I/O–B2 I/O–B1 I/O–B0 GND IN0–CK0 IN2–gtsn ΘJA Package 44-pin PLCC 49.8°C/W 44-pin TQFP 66.3°C/W PERCENTAGE REDUCTION IN ΘJA (%) 0 10 SP00420 20 PZ5032 – 44-Pin Thin Quad Flat Package 44 30 34 1 40 33 PLCC/ QFP TQFP 50 0 1 2 3 4 5 AIR FLOW (m/s) 11 23 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function I/O–A3 I/O–A4 I/O–A5 GND I/O–A6 I/O–A7 I/O–A8 I/O–A9 VDD I/O–A10 I/O–A11 I/O–A12 I/O–A13 I/O–A14 I/O–A15 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 SP00419A 22 12 Function GND VDD I/O–B15 I/O–B14 I/O–B13 I/O–B12 I/O–B11 I/O–B10 GND I/O–B9 I/O–B8 I/O–B7 I/O–B6 VDD I/O–B5 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Figure 7. Average Effect of Airflow on ΘJA Function I/O–B4 I/O–B3 I/O–B2 I/O–B1 I/O–B0 GND IN0/CK0 IN2–gtsn IN1 IN3 VDD I/O–A0–CK1 I/O–A1 I/O–A2 SP00433 1997 Feb 20 11 Philips Semiconductors Product specification 32 macrocell CPLD PZ5032 PLCC44: plastic leaded chip carrier; 44 leads 1997 Feb 20 SOT187-2 12 Philips Semiconductors Product specification 32 macrocell CPLD PZ5032 TQFP44: plastic thin quad flat package; 44 leads; body 10 x 10 x 1.0 mm 1997 Feb 20 13 SOT376-1 Philips Semiconductors Product specification 32 macrocell CPLD PZ5032 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 1997 Feb 20 14