QS5820T GUARANTEED LOW SKEW CMOS 20 OUTPUT CLOCK DRIVER/BUFFER COMMERCIAL TEMPERATURE RANGE GUARANTEED LOW SKEW CMOS 20 OUTPUT CLOCK DRIVER/BUFFER QS5820T FEATURES: DESCRIPTION: • • • • • • The QS5820T clock driver/buffer circuits can be used for clock distribution schemes where low skew, high speed, and small footprint are primary concerns. The QS5820T offers four banks of five non-inverting outputs. Designed in IDT's proprietary QCMOS process, this device provides low propagation delay buffering with on-chip skew of 0.5ns for same-transition, same-bank signals. The QS5820T provides major skew advantages over octal type devices where total part-to-part skew (tSK(t)) of >1ns is unacceptable. Furthermore, board area consumed by the QVSOP package is almost one-third that of the typical SOIC package offered for octal devices. This clock buffer product is designed for use in high performance workstation, multi-board computing and telecommunications systems. The QS5820T is available in the 40-pin QVSOP package which offers the world’s smallest logic footprint. • 20 output, low skew clock signal buffer High drive FCT-type outputs Reduced swing TTL outputs for low noise Input hysteresis for better noise margin Monitor output Guaranteed low skew – 0.5ns output skew – 0.7ns pulse skew – 1ns part-to-part skew Available in 40-pin QVSOP FUNCTIONAL BLOCK DIAGRAM OE A 5 IN A OA 1 -O A 5 OE B 5 IN B OB 1 -O B 5 MONB OEC 5 INC OC 1 -OC 5 OED 5 IND OD 1 -OD 5 MO ND COMMERCIAL TEMPERATURE RANGE DECEMBER 2000 1 c 2000 Integrated Device Technology, Inc. DSC-5822/- QS5820T GUARANTEED LOW SKEW CMOS 20 OUTPUT CLOCK DRIVER/BUFFER PIN CONFIGURATION COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS Symbol (1) VTERM(2) Rating Supply Voltage to Ground Max. –0.5 to +7 Unit V VDD 1 40 VDD VTERM(3) DC Switch Voltage VS –0.5 to +7 V OA 1 2 39 OB 1 VTERM(3) DC Input Voltage VIN –0.5 to +7 V VAC AC Input Voltage (pulse width ≤20ns) –3 V DC Input Diode Current with VIN < 0 –20 mA OA 2 3 38 OB 2 OA 3 4 37 OB 3 IOUT DC Output Current Max Sink Current/Pin 120 mA GND 5 36 GN D PMAX Maximum Power Dissipation 1.2 W OA 4 6 35 OB 4 TSTG Storage Temperature Range –65 to +150 °C OA 5 7 34 OB 5 GND 8 33 MO N B OEA 9 32 OEB 31 IN B SO 40-1 IN A 10 VDD 11 30 VDD OC 1 12 29 OD 1 OC 2 13 28 OD 2 OC 3 14 27 OD 3 GND 15 26 GN D OC 4 16 25 OD 4 OC 5 17 24 OD 5 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDD Terminals. 3. All terminals except VDD. CAPACITANCE (TA = 25° C, f = 1MHz, VIN = 0V, VOUT = 0V) Pins All Pins Typ. 5 Max. 8 Unit pF NOTE: 1. Capacitance is characterized but not tested. PIN DESCRIPTION Pin Name Type Description OEA, OEB, OEC, OED I Output Enable Inputs INA, INB, INC, IND I Clock Inputs GND 18 23 MO ND OE C 19 22 OED OAn, OBn, OCn, ODn O Clock Outputs IND MONB, MOND O Non-disable Monitor Outputs INC 20 21 RECOMMENDED OPERATING CONDITIONS QVSOP TOP VIEW 2 Symbol VDD Description Power Supply Voltage Min. 4.75 Max. 5.25 Unit V VIN Input Voltage 0 5.5 V VOUT Voltage Applied to Outputs 0 5.5 V TA Ambient Operating Temperature 0 +70 °C QS5820T GUARANTEED LOW SKEW CMOS 20 OUTPUT CLOCK DRIVER/BUFFER COMMERCIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Symbol VIH VIL Parameter Input HIGH Voltage Conditions Guaranteed Logic HIGH for Inputs Min. 2 Typ. — Max. — Unit V Input LOW Voltage Guaranteed Logic LOW for Inputs — — 0.8 V VIC Clamp Diode Voltage VDD = Min., IIN = −18mA — − 0.7 − 1.2 V VOH Output HIGH Voltage VDD = Min., IOH = −24mA 2.4 — — V VOL Output LOW Voltage VDD = Min., IOL = 64mA — — 0.55 V IIN Input Leakage Current VDD = Max., VIN = VDD or GND — — ±1 µA IOZ Output Leakage Current VDD = Max., Outputs High-Z — — ±1 µA IOS Short Circuit Current (2,3) VDD = Max., VOUT = GND − 60 — — mA (3) NOTES: 1. Typical values are at VDD = 5.0V, TA = 25°C. 2. Not more than one output should be used to test this high power condition. Duration is ≤1 second. 3. Guaranteed by design but not tested. POWER SUPPLY CHARACTERISTICS Symbol ICC Parameter Quiescent Power Supply Current ∆ICC Supply Current per Input HIGH ICCD Dynamic Power Supply Current per Output Test Conditions (1) VDD = Max., VIN = GND or VDD (2) Typ. (3) 0.4 Max. 3 Unit mA VDD = Max., VIN = 3.4V, fI = 0MHz 0.5 2.5 mA VDD = Max., VIN = GND or VDD Outputs Enabled, 50% duty cycle 0.1 0.2 mA/MHz NOTES: 1. For conditions shown as Min. or Max., use the appropriate values specified under DC specifications. 2. Guaranteed but not tested. 3. Typical values are for reference only. Conditions are VDD = 5.0V and TA = 25°C. 4. IC = ICC + (∆ICC)(DH)(NT) + ICCD (fO)(NO) where: DH = Input duty cycle N T = Number of TTL HIGH inputs at DH fO = Output frequency NO = Number of outputs at fO 3 QS5820T GUARANTEED LOW SKEW CMOS 20 OUTPUT CLOCK DRIVER/BUFFER COMMERCIAL TEMPERATURE RANGE SKEW CHARACTERISTICS OVER OPERATING RANGE QS5820AT Symbol tSK(01) Description (1) Skew between two outputs, same transition, same bank QS5820BT Min. — Max. 0.5 Min. — Max. 0.5 Unit ns — 0.6 — 0.6 ns tSK(02) Skew between two outputs, same transition, different bank tSK(p) Duty cycle distortion (pulse skew) on a single output opposite transitions (t PHL - tPLH) — 1 — 0.7 ns tSK(t) Part-to-part skew, same transition (2) — 1.5 — 1 ns NOTES: 1. Skew parameters are guaranteed across temperature range, but not production tested. Skew parameters apply to propagation delays only. 2. tSK(t) only applies to devices of the same transition, same VDD, same temperature, same speed grade, and same loading. SWITCHING CHARACTERISTICS OVER OPERATING RANGE CLOAD = 50pF, RLOAD = 500Ω unless otherwise noted. QS5820AT Description (1) QS5820BT Min. Max. Min. Max. Unit Propagation Delay (1,2) 1.5 5.8 1.5 5 ns tR Output Rise Time, 0.8V to 2V — 1.5 — 1.5 ns tF Output Fall Time, 2V to 0.8V — 1.5 — 1.5 ns Output Enable Time 1.5 8 1.5 7 ns Output Disable Time 1.5 7 1.5 6 ns Symbol tPLH tPHL tPZL tPZH tPLZ tPHZ NOTES: 1. Minimums guaranteed but not tested. 2. The propagation delay range indicated by Min. and Max. specifications results from process and environmental variables. These propagation delay limits do not imply skew. 4 QS5820T GUARANTEED LOW SKEW CMOS 20 OUTPUT CLOCK DRIVER/BUFFER COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION XXX XX Device Type Package QS Q2 Quarter Size Very Sm all Outline Package (SO40-1) 5820AT 5820BT Guaranteed Low Skew CM OS 20 Output Clock Driver/Buffer CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* *To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. The IDT logo is a registered trademark of Integrated Device Technology, Inc. Turboclock is a registered trademark of Integrated Device Technology, Inc. 5