UC1572 UC2572 UC3572 Negative Output Flyback Pulse Width Modulator FEATURES DESCRIPTION • Simple Single Inductor Flyback PWM for Negative Voltage Generation The UC3572 is a negative output flyback pulse width modulator which converts a positive input voltage to a regulated negative output voltage. The chip is optimized for use in a single inductor negative flyback switching converter employing an external PMOS switch. The block diagram consists of a precision reference, an error amplifier configured for voltage mode operation, an oscillator, a PWM comparator with latching logic, and a 0.5A peak gate driver. The UC3572 includes an undervoltage lockout circuit to insure sufficient input supply voltage is present before any switching activity can occur, and a pulse-by-pulse current limit. Output current can be sensed and limited to a user determined maximum value. The UVLO circuit turns the chip off when the input voltage is below the UVLO threshold. In addition, a sleep comparator interfaces to the UVLO circuit to turn the chip off. This reduces the supply current to only 50µA, making the UC3572 ideal for battery powered applications. • Drives External PMOS Switch • Contains UVLO Circuit • Includes Pulse-by-Pulse Current Limit • Low 50µA Sleep Mode Current BLOCK DIAGRAM UDG-94094-2 SLUS275A - MARCH 1999 - REVISED AUGUST 2001 UC1572 UC2572 UC3572 ABSOLUTE MAXIMUM RATINGS CONNECTION DIAGRAM VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35V EAINV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.6V to VCC IEAOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA RAMP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 4V CS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC Iout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.7A to 0.7A I3VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15mA Storage Temperature . . . . . . . . . . . . . . . . . . . -65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . -65°C to +150°C Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C DIL-8, SOIC-8 (TOP VIEW) D, N or J Packages Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages. ORDERING INFORMATION UC1572 UC2572 UC3572 TEMPERATURE RANGE –55°C to +125°C –40°C to +85°C 0°C to +70°C PACKAGE J D, N or J D or N ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VCC = 5V, CT = 680pF, TA = TJ. PARAMETER TEST CONDITIONS MIN TYP 2.94 MAX UNITS Reference Section 3VREF 3 3.06 V Line Regulation VCC = 4.75 to 30V 1 10 mV Load Regulation I3VREF = 0V to –5mA 1 10 mV 100 115 kHz Oscillator Section Frequency VCC = 5V to 30V 85 EAOUT = 2V –10 Error Amp Section EAINV IEANV = –1mA 0 10 mV –0.2 –0.9 V –0.2 –1.0 IEAINV EAOUT = 2V AVOL EAOUT = 0.5V to 3V 65 EAOUT High EAINV = –100mV 3.6 EAOUT Low EAINV = 100mV IEAOUT EAINV = –100mV, EAOUT = 2V –350 –500 µA EAINV = 100mV, EAOUT = 2V 7 20 mA 0.6 1 MHz 0.185 0.205 0.225 V –0.4 –1 µA Unity Gain Bandwidth TJ = 25°C, F = 10kHz 90 A dB 4 4.4 V 0.1 0.2 V Current Sense Comparator Section Threshold Input Bias Current CS = 0 CS Propogation Delay 300 2 nS UC1572 UC2572 UC3572 ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VCC = 5V, CT = 680pF, TA = TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Gate Drive Output Section OUT High Saturation IOUT = 0 0 0.3 V IOUT = –10mA 0.7 1.5 V IOUT = –100mA 1.5 2.5 V IOUT = 10mA 0.1 0.4 V IOUT = 100mA 1.5 2.2 V Rise Time TJ = 25°C, CLOAD = 1nF + 3.3 Ohms 30 80 nS Fall Time TJ = 25°C, CLOAD = 1nF + 3.3 Ohms 30 80 nS EAINV = +100mV, VCC = 5V to 30V 92 96 % 0 % 45 55 65 %/V Start Threshold 3.5 4.2 4.5 V Hysteresis 100 200 300 mV 1.8 2.2 2.6 V OUT Low Saturation Pulse Width Modulator Section Maximum Duty Cycle Minimum Duty Cycle EAINV = –100mV, VCC = 5V to 30V Modulator Gain EAOUT = 1.5V to 2.5V Undervoltage Lockout Section Sleep Mode Section Threshold Supply Current Section IVCC VCC = 5V, 30V 9 15 mA VCC = 30, CS = 3V 50 150 A UDG-94095 Figure 1. Typical waveforms. 3 UC1572 UC2572 UC3572 PIN DESCRIPTIONS 3VREF: Precision 3V reference. Bypass with 100nF capacitor to GND. OUT: Gate drive for external PMOS switch connected between VCC and the flyback inductor. OUT drives the gate of the PMOS switch between VCC and GND. CS: Current limit sense pin. Connect to a ground referenced current sense resistor in series with the flyback inductor. OUT will be held high (PMOS switch off) if CS exceeds 0.2V. RAMP: Oscillator and ramp for pulse width modulator. Frequency is set by a capacitor to GND by the equation F= EAINV: Inverting input to error amplifier. Summing junction for 3VREF and VOUT sense. The non-inverting input of the error amplifier is internally connected to GND. This pin will source a maximum of 1mA. 1 15k • CRAMP Recommended operating frequency range is 10kHz to 200kHz. VCC: Input voltage supply to chip. Range is 4.75 to 30V. Bypass with a 1µF capacitor. EAOUT: Output of error amplifier. Use EAOUT and EAINV for loop compensation components. GND: Circuit Ground. VIN RSLEEP3 1MEG SLEEP MSLEEP CVCC 10µF C3V REF 100nF CIN 10µF UC1572 4 VCC 8 3VREF 7 RAMP 1 EAINV 2 EAOUT 6 GND OUT 5 MSWITCH CRAMP 680pF RREF RSLEEP1 56k LFLYBACK RCOMP CCOMP RSLEEP2 33k CS DFLYBACK 3 RCS GND GND COUT 100µF RV SENSE 40k –12V OUT VOUT UDG-99057 Figure 2. Typical application: +5V to –12V flyback converter. 4 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. 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