CY7C007 A CY7C017 A32K/16 K x 8, 32 K x 9 Dual-Po rt Static RAM 1 CY7C006A, CY7C007A CY7C016A, CY7C017A 32K/16K x8, 32K/16K x9 Dual-Port Static RAM • Automatic power-down • Expandable data bus to 16/18 bits or more using Master/Slave chip select when using more than one device • On-chip arbitration logic • Semaphores included to permit software handshaking between ports • INT flags for port-to-port communication • Pin select for Master or Slave • Commercial temperature range • Available in 68-pin PLCC (CY7C006A, CY7C007A and CY7C017A), 64-pin TQFP (CY7C006A), and in 80-pin TQFP (CY7C007A and CY7C016A) • Pin-compatible and functionally equivalent to IDT7006 and IDT7007 Features • True dual-ported memory cells which allow simultaneous access of the same memory location • 16K x 8 organization (CY7C006A) • 32K x 8 organization (CY7C007A) • 16K x 9 organization (CY7C016A) • 32K x 9 organization (CY7C017A) • 0.35-micron CMOS for optimum speed/power • High-speed access: 12/15/20 ns • Low operating power — Active: ICC = 180 mA (typical) — Standby: ISB3 = 0.05 mA (typical) • Fully asynchronous operation Logic Block Diagram R/WL R/WR CEL CER OEL OER  8/9  8/9 I/O0L–I/O7/8L I/O0R–I/O7/8R I/O Control  A0L–A13/14L  14/15 Address Decode Address Decode True Dual-Ported RAM Array 14/15 14/15  A0R–A 13/14R 14/15 A0L–A13/14L CEL OEL R/WL SEM L I/O Control  A0R–A 13/14R CER OE R Interrupt Semaphore Arbitration   BUSYL INTL R/WR SEM R BUSYR INT R M/S Notes: 1. See page 7 for Load Conditions. 2. I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices. 3. BUSY is an output in master mode and an input in slave mode. 4. A0–A13 for 16K; A0–A14 for 32K devices. For the most recent information, visit the Cypress web site at www.cypress.com Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 January 10, 2001 CY7C006A, CY7C007A CY7C016A, CY7C017A Each port has independent control pins: Chip Enable (CE), Read or Write Enable (R/W), and Output Enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The Interrupt flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a Chip Select (CE) pin. Functional Description The CY7C006A, CY7C007A, CY7C016A, and CY7C017A are low-power CMOS 32K x 8/9 and 16K x 8/9 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 8/9-bit dual-port static RAMs or multiple devices can be combined in order to function as a 16/18-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 16/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. The CY7C006A, CY7C007A, and CY7C017A are available in 68-pin PLCC packages, the CY7C006A is also available in 64-pin TQFP, and the CY7C007A and CY7C016A are also available in 80-pin TQFP packages. 2 CY7C006A, CY7C007A CY7C016A, CY7C017A Pin Configurations I/O2L I/O3L I/O4L 10 I/O5L GND I/O6L I/O7L 13 A9L A8L A7L A6L 64 63 62 61 VCC 68 67 A11L A10L A14L A13L 2 1 65 CEL 3 A12L SEML 4 66 R/WL 5  I/O0L NC(I/O8L) OEL 7 6 I/O1L 12 I/O2R VCC 21 22 23 24 A5L A4L 58 A3L A2L A1L 56 55 CY7C006A (16K x 8) CY7C007A (32K x 8) CY7C017A (32K x 9) 16 17 18 60 59 57 14 15 GND I/O0R I/O1R 19 INTL 53 BUSYL GND M/S 51 50 49 48 47 42 43 BUSYR INTR A0R A1R A2R A3R A4R A6R A5R 41 40 A8R A7R A9R 38 39 36 37 A11R A10R A12R 35 GND A 14R A13R 32 33 34 31 CER  30 44 SEMR 26 29 46 45 OER R/WR 25 27 28 A0L 54 52 20 I/O7R I/O3R I/O4R I/O5R I/O6R 8 11 NC(I/O8R ) VCC 9 68-Pin PLCC Top View NC NC 61 A10L 67 A6L A11L 68 63 62 A12L 69 A7L VCC 70 A8L  A13L 64 A14L 72 71 A9L CE L NC 74 66 65 SEM L 75 73 R/W L 76 NC OE L 78 77 1 79 NC I/O 2L I/O 3L 80 I/O1L I/O0L 80-Pin TQFP Top View 60 NC A5L A4L 2 59 I/O 4L 3 4 58 57 I/O 5L 5 56 A3L A2L GND I/O 6L 6 55 A1L 7 54 A0L I/O 7L 8 53 V CC 9 10 52 51 50 INTL BUSYL GND M/S 49 BUSYR NC GND I/O0R I/O1R CY7C007A (32K x 8) CY7C016A (16K X 9) 11 12 Notes: 5. This pin is I/O for CY7C017A only. 6. A14 is a no connect pin for 16K devices. 3 38 39 40 NC NC A5R 37 A6R A7R 35 36 A8R 34 A9R GND  A 14R OER NC I/O7R 33 NC 32 41 A11R A10R 20 31 NC A12R A4R 29 30 43 42 A13R 18 19 28 I/O 5R I/O 6R 27 44 26 17 NC 46 45 25 15 16 I/O 3R I/O 4R CER V CC A0R A1R SEMR 47 23 24 14 R/WR INTR I/O2R 22 48 21 13 A2R A3R NC CY7C006A, CY7C007A CY7C016A, CY7C017A Pin Configurations (continued) A6L A5L 49 54 A7L A12L 56 55 A8L VCC 57 51 50 CEL A13L A9L SEML 59 52 R/WL 60 53 OEL 62 61 A11L A10L I/O0L 63 58 I/O1L 64 64-Pin TQFP Top View I/O2L 1 48 A4L I/O3L I/O4L 2 47 3 4 46 45 A3L A2L 5 44 A0L I/O6L I/O7L 6 43 7 42 INTL BUSYL GND M/S I/O5L GND CY7C006A (16K x 8) A1L 36 A0R A1R I/O3R I/O4R 14 15 35 34 A2R I/O5R 16 33 A4R 32 A6R A5R 30 31 41 A7R A8R A9R A11R A10R A12R GND CER A13R SEMR R/WR OER I/O6R I/O7R 29 13 28 VCC 27 37 25 26 12 24 INTR I/O2R 23 38 22 11 21 40 39 19 20 9 10 18 8 17 VCC GND I/O0R I/O1R BUSYR A3R C006-3 Selection Guide CY7C006A CY7C007A CY7C016A CY7C017A -12 CY7C006A CY7C007A CY7C016A CY7C017A -15 CY7C006A CY7C007A CY7C016A CY7C017A -20 Maximum Access Time (ns) 12 15 20 Typical Operating Current (mA) 195 190 180 Typical Standby Current for ISB1 (mA) (Both Ports TTL Level) Typical Standby Current for ISB3 (mA) (Both Ports CMOS Level) 4 55 50 45 0.05 0.05 0.05 CY7C006A, CY7C007A CY7C016A, CY7C017A Pin Definitions Left Port Right Port Description CEL CER Chip Enable R/WL R/WR Read/Write Enable OEL OER Output Enable A0L–A14L A0R–A14R Address I/O0L–I/O 8L I/O0R–I/O 8R Data Bus Input/Output (I/O0–I/O7 for x8 devices and I/O 0–I/O8 for x9) SEML SEMR Semaphore Enable INTL INTR Interrupt Flag BUSYL BUSYR Busy Flag M/S Master or Slave Select VCC Power GND Ground NC No Connect Output Current into Outputs (LOW)............................. 20 mA Maximum Ratings Static Discharge Voltage .......................................... >2001V (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-Up Current .................................................... >200 mA Storage Temperature .................................–65°C to +150°C Operating Range Ambient Temperature with Power Applied.............................................–55°C to +125°C Supply Voltage to Ground Potential ............... –0.3V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... –0.5V to +7.0V Range Ambient Temperature VCC Commercial 0°C to +70°C 5V ± 10% –40°C to +85°C 5V ± 10% Industrial DC Input Voltage ........................................ –0.5V to +7.0V 5 CY7C006A, CY7C007A CY7C016A, CY7C017A Electrical Characteristics Over the Operating Range CY7C006A CY7C007A CY7C016A CY7C017A -12 Parameter Min. Description VOH Output HIGH Voltage (VCC = Min., IOH = –4.0 mA) VOL Output LOW Voltage (VCC = Min., IOH = +4.0 mA) VIH Input HIGH Voltage VIL Input LOW Voltage IOZ Output Leakage Current ICC Operating Current (VCC = Max., IOUT = 0 mA) Outputs Disabled Com’l. Standby Current (Both Ports TTL Level) CEL & CER ≥ VIH, f = fMAX Com’l. Standby Current (One Port TTL Level) CEL | CER ≥ VIH, f = fMAX Com’l. Standby Current (Both Ports CMOS Level) CEL & CER ≥ VCC − 0.2V, f=0 Com’l. Standby Current (One Port CMOS Level) CEL | CER ≥ VIH, f = fMAX Com’l. ISB1 ISB2 ISB3 ISB4 Typ. -15 Max. 2.4 Min. Typ. -20 Max. 2.4 10 –10 325 75 Ind. 125 205 Ind. 0.05 0.5 Ind. 115 185 Ind. 10 190 280 215 305 50 70 65 95 120 180 135 205 0.05 0.5 0.05 0.5 110 160 125 175 Unit V V 0.8 Ind. 55 0.4 2.2 0.8 195 Max. V 0.4 2.2 –10 Typ. 2.4 0.4 2.2 Min. 0.8 –10 180 V 10 µA 275 mA mA 45 65 mA mA 110 160 mA mA 0.05 0.5 mA mA 100 140 mA mA Capacitance Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. Unit 10 pF 10 pF Notes: 7. Pulse width < 20 ns. 8. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3. 9. Tested initially and after any design or process changes that may affect these parameters. 6 CY7C006A, CY7C007A CY7C016A, CY7C017A AC Test Loads and Waveforms 5V 5V R1 = 893Ω RTH = 250Ω OUTPUT OUTPUT R1 = 893Ω OUTPUT C = 30 pF C = 30 pF R2 = 347Ω C = 5 pF R2 = 347Ω VTH = 1.4V (a) Normal Load (Load 1) (c) Three-State Delay (Load 2) (Used for tLZ, tHZ, tHZWE, & tLZWE including scope and jig) (b) Thévenin Equivalent (Load 1) AC Test Loads (Applicable to -12 only) Z 0 = 50Ω ALL INPUT PULSES R = 50Ω OU TPUT 3.0V C 10% GND 90% 10% 90% ≤ 3 ns ≤ 3 ns VTH = 1.4V (a) Load 1 (-12 only) 1 .00 0.90 ∆ (ns) for all -12 access times 0.80 0.70 0.60 0.50 0.40 0.30 0.20 0.1 0 0.00 10 15 20 25 Capacitance (pF) (b) Load Derating Curve Note: 10. Test Conditions: C = 10 pF. 7 30 35 CY7C006A, CY7C007A CY7C016A, CY7C017A Switching Characteristics Over the Operating Range CY7C006A CY7C007A CY7C016A CY7C017A –12 Parameter Description Min. –15 Max. Min. –20 Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Output Hold From Address Change tACE CE LOW to Data Valid tDOE OE LOW to Data Valid tLZOE[13, 14, 15] OE LOW to Low Z tHZOE[13, 14, 15] tLZCE[13, 14, 15] tHZCE[13, 14, 15] tPU tPD OE HIGH to High Z 12 15 12 3 3 12 3 CE HIGH to High Z 10 3 0 CE HIGH to Power-Down ns 12 ns ns 12 10 12 20 3 0 ns ns 12 0 15 ns ns 3 10 10 CE LOW to Power-Up 3 3 10 ns 20 15 8 3 CE LOW to Low Z 20 15 ns ns 20 ns WRITE CYCLE tWC Write Cycle Time 12 15 20 ns tSCE CE LOW to Write End 10 12 15 ns tAW Address Valid to Write End 10 12 15 ns tHA Address Hold From Write End 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 ns tPWE Write Pulse Width 10 12 15 ns tSD Data Set-Up to Write End 10 10 15 ns tHD tHZWE[14, 15] tLZWE[14, 15] tWDD tDDD Data Hold From Write End 0 0 0 ns R/W LOW to High Z 10 R/W HIGH to Low Z 3 10 3 12 3 ns ns Write Pulse to Data Delay 25 30 45 ns Write Data Valid to Read Data Valid 20 25 30 ns  BUSY TIMING tBLA BUSY LOW from Address Match 12 15 20 ns tBHA BUSY HIGH from Address Mismatch 12 15 20 ns tBLC BUSY LOW from CE LOW 12 15 20 ns tBHC BUSY HIGH from CE HIGH 17 ns tPS Port Set-Up for Priority 12 5 15 5 5 ns Notes: 11. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I OI/IOH and 30-pF load capacitance. 12. To access RAM, CE = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time. 13. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 14. Test conditions used are Load 3. 15. This parameter is guaranteed but not tested. 16. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 17. Test conditions used are Load 2. 18. For 15 ns industrial parts tHD Min. is 0.5 ns. 8 CY7C006A, CY7C007A CY7C016A, CY7C017A Switching Characteristics Over the Operating Range (continued) CY7C006A CY7C007A CY7C016A CY7C017A –12 Parameter Description Min. –15 Max. Min. –20 Max. Min. Max. Unit tWB R/W HIGH after BUSY (Slave) 0 0 0 ns tWH R/W HIGH after BUSY HIGH (Slave) 11 13 15 ns tBDD BUSY HIGH to Data Valid 12 15 20 ns  INTERRUPT TIMING tINS INT Set Time 12 15 20 ns tINR INT Reset Time 12 15 20 ns SEMAPHORE TIMING tSOP SEM Flag Update Pulse (OE or SEM) 10 10 10 ns tSWRD SEM Flag Write to Read Time 5 5 5 ns tSPS SEM Flag Contention Window 5 5 5 ns tSAA SEM Address Access Time 12 15 20 ns Timing Data Retention Mode Data Retention Mode The C Y7C 006A, C Y7C 007A, C Y7C 016A, and C Y7C 017A are designed w ith battery backup in m ind. D ata retention voltage and supply current are guaranteed over tem perature. The follow ing rules ensure data retention: VCC 1. C hip Enable (C E) m ust be held H IG H during data retention, w ithin V CC to V C C – 0.2V. 4.5V VCC > 2.0V 4.5V VCC to VCC – 0.2V CE tRC V IH 2. C E m ust be kept betw een V C C – 0.2V and 70% of V C C during the pow er-up and pow er-dow n transitions. Parameter 3. The R AM can begin operation >tR C after V C C reaches the m inim um operating voltage (4.5 volts). ICC DR1 Test Conditions @ VCCDR = 2V Switching Waveforms Read Cycle No. 1 (Either Port Address Access)[21, 22, 23] tRC ADDRESS tAA tOHA DATA OUT tOHA PREVIOUS DATA VALID DATA VALID Notes: 19. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual). 20. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested. 21. R/W is HIGH for read cycles. 22. Device is continuously selected CE = VIL. This waveform cannot be used for semaphore reads. 23. OE = VIL. 9 Max. Unit 1.5 mA CY7C006A, CY7C007A CY7C016A, CY7C017A Switching Waveforms (continued) Read Cycle No. 2 (Either Port CE/OE Access)[21, 24, 25] tACE CE tHZCE tDOE OE tHZOE tLZOE DATA VALID DATA OUT tLZCE tPU tPD ICC CURRENT ISB Read Cycle No. 3 (Either Port)[21, 23, 24, 25] tRC ADDRESS tAA tOHA tLZCE tABE CE tHZCE tACE tLZCE DATA OUT Notes: 24. Address valid prior to or coincident with CE transition LOW. 25. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL. 10 CY7C006A, CY7C007A CY7C016A, CY7C017A Switching Waveforms (continued) Write Cycle No. 1: R/W Controlled Timing [26, 27, 28, 29] tWC ADDRESS tHZOE  OE CE tAW  tPWE tSA tHA R/W tHZWE DATA OUT tLZWE NOTE 32 NOTE 32 tSD tHD DATA IN Write Cycle No. 2: CE Controlled Timing [26, 27, 28, 33] tWC ADDRESS tAW CE  tSA tSCE tHA R/W tSD tHD DATA IN Notes: 26. R/W or CE must be HIGH during all address transitions. 27. A write occurs during the overlap (t SCE or tPWE) of a LOW CE or SEM. 28. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle. 29. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE. 30. To access RAM, CE = VIL, SEM = VIH. 31. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested. 32. During this period, the I/O pins are in the output state, and input signals must not be applied. 33. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state. 11 CY7C006A, CY7C007A CY7C016A, CY7C017A Switching Waveforms (continued) Semaphore Read After Write Timing, Either Side tAA A 0–A 2 VALID ADRESS VALID ADRESS tAW tACE tHA SEM tOHA tSCE tSOP tSD I/O0 DATAIN VALID tSA tPWE DATAOUT VALID tHD R/W tSWRD tDOE tSOP OE WRITE CYCLE READ CYCLE Timing Diagram of Semaphore Contention[35, 36, 37] A0L –A 2L MATCH R/WL SEM L tSPS A 0R –A 2R MATCH R/WR SEM R Notes: 34. CE = HIGH for the duration of the above timing (both write and read cycle). 35. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH. 36. Semaphores are reset (available to both ports) at cycle start. 37. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable. 12 CY7C006A, CY7C007A CY7C016A, CY7C017A Switching Waveforms (continued) Timing Diagram of Read with BUSY (M/S=HIGH) tWC ADDRESSR MATCH tPWE R/WR tHD tSD DATA INR VALID tPS ADDRESSL MATCH tBLA tBHA BUSYL tBDD tDDD DATA OUTL VALID tWDD Write Timing with Busy Input (M/S=LOW) tPWE R/W BUSY tWB tWH Note: 38. CEL = CER = LOW. 13 CY7C006A, CY7C007A CY7C016A, CY7C017A Switching Waveforms (continued) Busy Timing Diagram No. 1 (CE Arbitration) CELValid First: ADDRESS L,R ADDRESS MATCH CEL tPS CER tBLC tBHC BUSYR CER Valid First: ADDRESS L,R ADDRESS MATCH CER tPS CE L tBLC tBHC BUSY L Busy Timing Diagram No. 2 (Address Arbitration) Left Address Valid First: tRC or tWC ADDRESS L ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSR tBLA tBHA BUSY R Right Address Valid First: tRC or tWC ADDRESSR ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSL tBLA tBHA BUSY L Note: 39. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted. 14 CY7C006A, CY7C007A CY7C016A, CY7C017A Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INTR: tWC ADDRESSL WRITE 7FFF tHA  CE L R/W L INT R tINS  Right Side Clears INTR: tRC READ 7FFF ADDRESSR CE R tINR  R/WR OE R INTR Right Side Sets INT L: tWC ADDRESSR WRITE 7FFE tHA CE R R/W R INT L  tINS Left Side Clears INTL: tRC ADDRESSR READ 7FFE CE L tINR R/W L OE L INT L Notes: 40. tHA depends on which enable pin (CEL or R/WL) is deasserted first. 41. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last. 15 CY7C006A, CY7C007A CY7C016A, CY7C017A address match occurs within tPS of each other, the busy logic will determine which port has access. If tPS is violated, one port will definitely gain permission to the location, but it is not predictable which port will get that permission. BUSY will be asserted tBLA after an address match or tBLC after CE is taken LOW. Architecture The CY7C006A, CY7C007A, CY7C016A and CY7C017A consist of an array of 32K/16K words of 8 bits and 32K words of 9 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. Two Interrupt (INT) pins can be utilized for port-to-port communication. Two Semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the devices can function as a master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). The devices also have an automatic power-down feature controlled by CE. Each port is provided with its own Output Enable control (OE), which allows data to be read from the device. Master/Slave A M/S pin is provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This will allow the device to interface to a master device with no external components. Writing to slave devices must be delayed until after the BUSY input has settled (tBLC or tBLA), otherwise, the slave chip may begin a write cycle during a contention situation. When tied HIGH, the M/S pin allows the device to be used as a master and, therefore, the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave. Functional Description Semaphore Operation Write Operation The CY7C006A, CY7C007A, CY7C016A and CY7C017A provide eight semaphore latches, which are separate from the dual-port memory locations. Semaphores are used to reserve resources that are shared between the two ports. The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tSOP before attempting to read the semaphore. The semaphore value will be available tSWRD + tDOE after the rising edge of the semaphore write. If the left port was successful (reads a zero), it assumes control of the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore. When the right side has relinquished control of the semaphore (by writing a one), the left side will succeed in gaining control of the semaphore. If the left side no longer requires the semaphore, a one is written to cancel its request. Data must be set up for a duration of tSD before the rising edge of R/W in order to guarantee a valid write. A write operation is controlled by either the R/W pin (see Write Cycle No. 1 waveform) or the CE pin (see Write Cycle No. 2 waveform). Required inputs for non-contention operations are summarized in Table 1. If a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is read on the output; otherwise the data read is not deterministic. Data will be valid on the port tDDD after the data is presented on the other port. Read Operation When reading the device, the user must assert both the OE and CE pins. Data will be available tACE after CE or tDOE after OE is asserted. If the user wishes to access a semaphore flag, then the SEM pin must be asserted instead of the CE pin, and OE must also be asserted. Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip select for the semaphore latches (CE must remain HIGH during SEM LOW). A0–2 represents the semaphore address. OE and R/W are used in the same manner as a normal memory access. When writing or reading a semaphore, the other address pins have no effect. Interrupts The upper two memory locations may be used for message passing. The highest memory location (7FFF) is the mailbox for the right port and the second-highest memory location (7FFE) is the mailbox for the left port. When one port writes to the other port’s mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox. The message is user defined. When writing to the semaphore, only I/O 0 is used. If a zero is written to the left port of an available semaphore, a one will appear at the same semaphore address on the right port. That semaphore can now only be modified by the side showing zero (the left port in this case). If the left port now relinquishes control by writing a one to the semaphore, the semaphore will be set to one for both sides. However, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. Table 3 shows sample semaphore operations. Each port can read the other port’s mailbox without resetting the interrupt. The active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. Also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. If an application does not require message passing, do not connect the interrupt pin to the processor’s interrupt request input pin. When reading a semaphore, all data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. If both ports attempt to access the semaphore within tSPS of each other, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore. The operation of the interrupts and their interaction with Busy are summarized in Table 2. Busy The CY7C006A, CY7C007A, CY7C016A and CY7C017A provide on-chip arbitration to resolve simultaneous memory location access (contention). If both ports’ CEs are asserted and an 16 CY7C006A, CY7C007A CY7C016A, CY7C017A Table 1. Non-Contending Read/Write Inputs Outputs I/O0–I/O8 CE R/W OE SEM H X X H High Z Deselected: Power-Down H H L L Data Out Read Data in Semaphore Flag X X H X High Z I/O Lines Disabled X L Data In Write into Semaphore Flag H Operation L H L H Data Out Read L L X H Data In Write L X X L Not Allowed Table 2. Interrupt Operation Example (assumes BUSYL=BUSYR=HIGH) Left Port Function Right Port R/WL CEL OEL A0L–14L INTL R/WR CER OER A0R–14R INTR Set Right INTR Flag L L X 7FFF X X X X X L Reset Right INTR Flag X X X X X X L L 7FFF H Set Left INTL Flag X X X X L L L X 7FFE X  X X X X X Reset Left INTL Flag X L L 7FFE H Table 3. Semaphore Operation Example I/O0–I/O8 Left I/O0–I/O8Right No action 1 1 Semaphore free Left port writes 0 to semaphore 0 1 Left Port has semaphore token Right port writes 0 to semaphore 0 1 No change. Right side has no write access to semaphore Left port writes 1 to semaphore 1 0 Right port obtains semaphore token Left port writes 0 to semaphore 1 0 No change. Left port has no write access to semaphore Right port writes 1 to semaphore 0 1 Left port obtains semaphore token Left port writes 1 to semaphore 1 1 Semaphore free Right port writes 0 to semaphore 1 0 Right port has semaphore token Right port writes 1 to semaphore 1 1 Semaphore free Left port writes 0 to semaphore 0 1 Left port has semaphore token Left port writes 1 to semaphore 1 1 Semaphore free Function Notes: 42. If BUSYR = L, then no change. 43. If BUSYL= L, then no change. 17 Status CY7C006A, CY7C007A CY7C016A, CY7C017A Ordering Information 16K x8 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 12 CY7C006A-12AC 15 CY7C006A-15AI A65 64-Pin Thin Quad Flat Pack Industrial CY7C006A-15JC J81 68-Pin Plastic Leaded Chip Carrier Commercial 20 A65 64-Pin Thin Quad Flat Pack Commercial CY7C006A-12JC J81 68-Pin Plastic Leaded Chip Carrier Commercial CY7C006A-15AC A65 64-Pin Thin Quad Flat Pack Commercial CY7C006A-15JI J81 68-Pin Plastic Leaded Chip Carrier Industrial CY7C006A-20AC A65 64-Pin Thin Quad Flat Pack Commercial CY7C006A-20JC J81 68-Pin Plastic Leaded Chip CarrieR Commercial 32K x8 Asynchronous Dual-Port SRAM Speed (ns) 12 15 20 Ordering Code Package Name Package Type Operating Range CY7C007A-12AC A80 80-Pin Thin Quad Flat Pack Commercial CY7C007A-12JC J81 68-Pin Plastic Leaded Chip Carrier Commercial CY7C007A-15AC A80 80-Pin Thin Quad Flat Pack Commercial CY7C007A-15AI A80 80-Pin Thin Quad Flat Pack Industrial CY7C007A-15JC J81 68-Pin Plastic Leaded Chip Carrier Commercial CY7C007A-15JI J81 68-Pin Plastic Leaded Chip Carrier Industrial CY7C007A-20AC A80 80-Pin Thin Quad Flat Pack Commercial CY7C007A-20JC J81 68-Pin Plastic Leaded Chip CarrieR Commercial 16K x9 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 12 CY7C016A-12AC 15 CY7C016A-15AC A80 80-Pin Plastic Leaded Chip Carrier Commercial CY7C016A-15IC A80 80-Pin Plastic Leaded Chip Carrier Industrial CY7C016A-20AC A80 80-Pin Plastic Leaded Chip Carrier Commercial 20 A80 80-Pin Plastic Leaded Chip Carrier Commercial 32K x9 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 12 CY7C017A-12JC J81 68-Pin Plastic Leaded Chip Carrier Commercial 15 CY7C017A-15JC J81 68-Pin Plastic Leaded Chip Carrier Commercial CY7C017A-15JI J81 68-Pin Plastic Leaded Chip Carrier Industrial 20 CY7C017A-20JC J81 68-Pin Plastic Leaded Chip Carrier Commercial Document #: 38-00831-*C 18 CY7C006A, CY7C007A CY7C016A, CY7C017A Package Diagrams 64-Lead Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm) A65 51-85046-B 19 CY7C006A, CY7C007A CY7C016A, CY7C017A Package Diagrams (continued) 80-Pin Thin Plastic Quad Flat Pack A80 51-85065-B 68-Lead Plastic Leaded Chip Carrier J81 51-85005-A © Cypress Semiconductor Corporation, 2001. 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