August 1992 11C90/11C91 650 MHz Prescalers General Description The 11C90 and 11C91 are high-speed prescalers designed specifically for communication and instrumentation applications. All discussions and examples in this data sheet are applicable to the 11C91 as well as the 11C90. The 11C90 will divide by 10 or 11 and the 11C91 by 5 or 6, both over a frequency range from DC to typically 650 MHz. The division ratio is controlled by the Mode Control. The divide-by-10 or -11 capability allows the use of pulse swallowing techniques to control high-speed counting modulos by lower-speed circuits. The 11C90 may be used with either ECL or TTL power supplies. In addition to the ECL outputs Q and Q, the 11C90 contains an ECL-to-TTL converter and a TTL output. The TTL output operates from the same VCC and VEE levels as the counter, but a separate pin is used for the TTL circuit VEE. This minimizes noise coupling when the TTL output switches and also allows power consumption to be reduced by leaving the separate VEE pin open if the TTL output is not used. To facilitate capacitive coupling of the clock signal, a 400X resistor (VREF) is connected internally to the VBB reference. Connecting this resistor to the Clock Pulse input (CP) automatically centers the input about the switching threshold. Maximum frequency operation is achieved with a 50% duty cycle. Each of the Mode Control inputs is connected to an internal 2 kX resistor with the other end uncommitted (RM1 and RM2). An M input can be driven from a TTL circuit operating from the same VCC by connecting the free end of the associated 2 kX resistor to VCCA. When an M input is driven from the ECL circuit, the 2 kX resistor can be left open or, if required, can be connected to VEE to act as a pull-down resistor. Logic Symbol Connection Diagram 16-Pin DIP TL/F/9892 – 2 Pin Names CE CP Mn MS Q, Q QTTL RMn VREF TL/F/9892 – 1 Description Count Enable Input (Active LOW) Clock Pulse Input Count Modulus Control Input Asynchronous Master Set Input ECL Outputs TTL Output 2 kX Resistor to Mn 400X Resistor to VBB C1995 National Semiconductor Corporation TL/F/9892 RRD-B30M115/Printed in U. S. A. 11C90/11C91 650 MHz Prescalers Not Intended For New Designs Absolute Maximum Ratings Recommended Operating Conditions Above which the useful life may be impaired If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. b 65§ C to a 150§ C Storage Temperature Maximum Junction Temperature (TJ) Supply Voltage Range Input Voltage (DC) Output Current (DC Output HIGH) Operating Range Lead Temperature (Soldering, 10 sec.) Min Ambient Temperature (TA) Commercial Military Supply Voltage (VEE) Commercial Military a 150§ C b 7.0V to GND VEE to GND b 50 mA b 5.7V to b 4.7V Typ 0§ C a 75§ C a 125§ C b 55§ C b 5.7V b 5.7V Max b 5.2V b 5.2V b 4.7V b 4.7V 300§ C TTL Input/Output Operation DC Electrical Characteristics Over Operating Temperature and Voltage Range unless otherwise noted, Pins 12 and 13 e GND Symbol Parameter Min Typ (Note 3) Max Units Conditions VIH Input HIGH Voltage M1 and M2 Inputs 4.1 V Guaranteed Input HIGH Threshold Voltage (Note 4), VCC e VCCA e 5.0V VIL Input LOW Voltage M1 and M2 Inputs 3.3 V Guaranteed Input LOW Threshold Voltage (Note 4), VCC e VCCA e 5.0V VOH Output HIGH Voltage QTTL Output 3.3 V VCC e VCCA e Min, IOH e b640 mA VOL Output LOW Voltage QTTL Output VCC e VCCA e Min, IOL e 20.0 mA IIL Input LOW Current M1 and M2 Inputs ISC Output Short Circuit Current 2.3 b 20 0.2 0.5 V b 2.3 b 5.0 mA VCC e VCCA e Max, VIN e 0.4V, Pins 6, 7 e VCC b 35 b 80 mA VCC e VCCA e Max, VOUT e 0.0V, Pin 14 e VCC AC Electrical Characteristics VCC e VCCA e 5.0V Nominal, VEE e GND, TA e a 25§ C Symbol Parameter Min Typ Max Units tPLH tPHL Propagation Delay, (50% to 50%) CP to QTTL tPLH Propagation Delay, (50% to 50%) MS to QTTL ts Mode Control Setup Time 4 2 ns th Mode Control Hold Time 0 b2 ns tTLH Output Rise Time (20% to 80%) 10 ns tTHL Output Fall Time (80% to 20%) 2 ns fMAX Count Frequency 650 650 MHz 6 550 600 2 10 14 ns 12 17 ns Conditions See Figure 1 b 55§ C to a 125§ C 0§ C to a 75§ C Clock Input AC Coupled 350 mV Peak-to-Peak Sinewave (Note 5) ECL OperationÐCommercial Version DC Electrical Characteristics VCC e VCCA e GND, VEE e b5.2V Symbol VOH VOL VIH VIL IIH IIL IEE VEE VREF Parameter Min Typ Max Output HIGH Voltage Q and Q b 1060 b 1025 b 980 b 995 b 960 b 910 b 905 b 880 b 805 mV b 1820 b 1705 b 1620 mV b 1135 b 1095 b 1035 b 840 b 810 b 720 mV a 25§ C a 75§ C b 1870 b 1850 b 1830 b 1500 b 1485 b 1460 mV a 25§ C a 75§ C Output LOW Voltage Q and Q Input HIGH Voltage Input LOW Voltage Input HIGH Current CP Input (Note 1) MS Input M1 and M2 Input Input LOW Current Power Supply Current Operating Supply Voltage Range Reference Voltage Units TA 0§ C Conditions Load e 50X to b2V a 25§ C a 75§ C 0§ C to a 75§ C 0§ C 0§ C Guaranteed Input HIGH Signal (Note 6) Guaranteed Input LOW Signal VIN e VIHA 400 400 250 0.5 b 110 b 119 b 75 b 5.7 b 5.2 mA a 25§ C a 25§ C a 25§ C mA a 25§ C VIN e VILB 0§ C to Pins 6, 7, 13 not connected mA b 1550 a 75§ C 0§ C to b 4.7 V b 1150 mV a 75§ C a 25§ C VRM1 e VRM2 e b5.2V IN e b10.0 mA AC Electrical Characteristics TA e 0§ C to a 75§ C, VCC e VCCA e GND, VEE e b5.2V Symbol Parameter 0§ C Typ a 25§ C a 75§ C Typ Units Min Typ Max 1.3 2.0 3.0 2.5 ns 4.0 6.0 4.5 ns tPLH tPHL Propagation Delay, (50% to 50%) CP to Q 1.8 tPLH Propagation Delay, (50% to 50%) MS to Q 3.7 ts Setup Time, M to CP 2.0 4.0 2.0 2.0 ns th Hold Time, M to CP b 2.0 0.0 b 2.0 b 2.0 ns tTLH Output Rise Time (20% to 80%) 1.0 1.0 2.0 1.0 ns tTHL Output Fall Time (80% to 20%) 1.0 1.0 2.0 1.0 ns fMAX Maximum Clock Frequency 625 MHz 650 600 650 3 Conditions Output: RL e 50X to b2.0V Input: tri e tfi e 2.0 g 0.1 ns (20% to 80%) See Figure 1 AC Coupled Input 350 mV Peak-to-Peak. fMAX is Guaranteed to be 575 MHz Min at 0§ C to a 75§ C. ECL OperationÐMilitary Version DC Electrical Characteristics VCC e VCCA e GND, VEE e b5.2V Symbol VOH Parameter Min Typ Max Units TA Output HIGH Voltage Q and Q b 1100 b 980 b 910 b 1030 b 910 b 820 b 900 b 820 b 670 mV b 55§ C a 25§ C a 125§ C b 1820 b 1705 b 1620 mV b 55§ C to a 125§ C b 1190 b 1095 b 975 b 905 b 810 b 690 mV b 55§ C a 25§ C a 125§ C Guaranteed Input HIGH Signal (Note 6) b 1890 b 1850 b 1800 b 1525 b 1485 b 1435 mV b 55§ C a 25§ C a 125§ C Guaranteed Input LOW Signal mA a 25§ C a 25§ C a 25§ C mA a 25§ C VIN e VILB mA a 25§ C Pins 6, 7, 13 not connected mA b 55§ C to a 125§ C b 4.7 V b 55§ C to a 125§ C b 1150 mV a 25§ C VOL Output LOW Voltage Q and Q VIH Input HIGH Voltage VIL IIH IIL IEE Input LOW Voltage Input HIGH Current CP Input (Note 1) MS Input M1 and M2 Input Input LOW Current Power Supply Current VIN e VIHA 400 400 250 0.5 b 110 b 75 b 119 VEE Operating Supply Voltage Range VREF Reference Voltage Conditions Load e 100X to b2V b 5.7 b 5.2 b 1550 VRM1 e VRM2 e b5.2V IN e b10.0 mA AC Electrical Characteristics TA e b55§ C to a 125§ C, VCC e VCCA e GND, VEE e b5.2V Symbol Parameter b 55§ C Typ a 25§ C a 125§ C Typ Units Min Typ Max 1.3 2.0 3.0 3.0 ns 4.0 6.0 5.0 ns tPLH tPHL Propagation Delay, (50% to 50%) CP to Q 1.5 tPLH Propagation Delay, (50% to 50%) MS to Q 3.5 ts Setup Time, M to CP 2.0 4.0 2.0 2.0 ns th Hold Time, M to CP b 2.0 0.0 b 2.0 b 2.0 ns tTLH Output Rise Time (20% to 80%) 1.0 1.0 2.0 1.0 ns tTHL Output Fall Time (80% to 20%) 1.0 1.0 2.0 1.0 ns fMAX Maximum Clock Frequency 700 600 650 600 MHz Conditions Output: RL e 50X to b2.0V Input: tri e tfi e 2.0 g 0.1 ns (20% to 80%) See Figure 1 AC Coupled Input 350 mV Peak-to-Peak. fMAX is Guaranteed to be 550 MHz Min at b55§ C to a 125§ C. Note 1: Conditions for testing, not shown in the Table, are chosen to guarantee operation under ‘‘worst case’’ conditions. Note 2: The specified limits represent the ‘‘worst case’’ value for the parameter. Since these ‘‘worst case’’ values normally occur at the temperature and supply voltage extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges. Note 3: Typical limits are at VCC e 5.0V and TA e a 25§ C. Note 4: The M1 and M2 threshold specifications are normally referenced to the VCC potential, as shown in the ECL operation tables. Using VEE (GND) as the reference, as in normal TTL practice, effectively makes the threshold vary directly with VCC. Threshold is typically 1.3V below VCC (e.g., a 3.7V at VCC e a 5V). A signal swing about threshold of g 0.4V is adequate, which gives the state VIH and VIL values. The internal 2 kX resistors are intended to pull TTL outputs up to the required VIH range, as discussed in the Functional Description and shown in Figure 5. Note 5: TTL Output Signal swing is guaranteed at fMAX over temperature range. Note 6: M1 or M2 can be tied to VCC for fixed divide-by-ten operation. 4 TL/F/9892 – 3 TL/F/9892 – 4 Conditions: VCC e a 2.0V VEE e b 3.2V RT e 50X (scope input impedance) CL e Jig and stray capacitance k 5.0 pF I1 e L2 e equal 50X impedance lines C e 0.1 pF Note 7: Use high impedance to test QTTL. Connect pin 13 to VEE. Note 8: For High frequency test use AC coupled input as in Figure 3 . Adjust input amplitude to 350 mV peak-to-peak. FIGURE 1. AC Test Circuit 5 Functional Description The 11C90 contains four ECL Flip-Flops, an ECL to TTL converter and a Schottky TTL output buffer with an active pull-up. Three of the Flip-Flops operate as a synchronous shift counter driving the fourth Flip-Flop operating as an asynchronous toggle. The internal feedback logic is such that the TTL output and the Q ECL output are HIGH for six clock periods and LOW for five clock periods. The Mode Control (M) inputs can modify the feedback to make the output HIGH for five clock periods and LOW for five clock periods, as indicated in the Count Sequence Table. The feedback logic is such that the instant the output goes HIGH, the circuit is already committed as to whether the output period will be 10 or 11 clock periods long. This means that subsequent changes in an M input signal, including decoding spikes, will have no effect on the current output period. The only timing restriction for an M input signal is that it be in the desired state at least a setup time before the clock that follows the HHLL state shown in the table. The allowable propagation delay through external logic to an M input is maximized by designing it to use the positive transition of the 11C90 output as its active edge. This gives an allowable delay of ten clock periods, minus the CP to Q delay of the 11C90 and the M to CP setup time. If the external logic uses the negative output transition as its active edge, the allowable delay is reduced to five clock periods minus the previously mentioned delay and setup time. Capacitively coupled triggering is simplified by the 400X resistor which connects pin 15 to the internal VBB reference. By connecting this to the CP input, as shown in Figure 3 , the clock is automatically centered about the input threshold. A clock duty cycle of 50% provides the fastest operation, since the Flip-Flops are Master-Slave types with offset clock thresholds between master and slave. This feature ensures that the circuit will operate with clock waveforms having very slow rise and fall times, and thus, there is no maximum frequency restriction. Recommended minimum and maximum clock amplitude as a function of a frequency and temperature are shown in the graph labeled Figure 2 . When the CP or any other input is driven from another ECL circuit, normal ECL termination methods are recommended. One method is indicated in Figure 4 . Other ECL termination methods are discussed in the F100K ECL Design Guide (Section 5 of Databook). TL/F/9892 – 10 FIGURE 3. Capacitively Coupled Clocking TL/F/9892 – 11 ZOX 50 75 100 R1X 80.6 121 162 R2X 130 196 261 VEE e b 5.2V, VCC e 0V, VTT e b 2.0V FIGURE 4. Clocking by ECL Source via Terminated Line When an M input is to be driven from a TTL output operating from the same VCC and ground (VEE), the internal 2 kX resistor can be used to pull the TTL output up as shown in Figure 5 . Some types of TTL outputs will only pull up to within two diode drops of VCC, which is not high enough for 11C90 inputs. The resistor will pull the signal up through the threshold region, although this final rise may be somewhat slow, depending on wiring capacitance. A resistor network that gives faster rise and also lower impedance is shown in Figure 6 . TL/F/9892 – 12 FIGURE 5. Using Internal Pull-Up with TTL Source TL/F/9892 – 13 TL/F/9892–5 FIGURE 6. Faster Low Impedance TTL to ECL Interface FIGURE 2. AC Coupled Triggering Characteristics 6 Functional Description (Continued) be connected together as close to the package as possible. Pin 12 must always be connected to the VEE side of the supply, while pin 13 is required only if the TTL output is used. Low impedance VCC and VEE distribution and RF bypass capacitors are recommended to prevent crosstalk. The ECL outputs have no pull-down resistors and can drive series or parallel terminated transmission lines. For short interconnections that do not require impedance matching, a 270X to 510X resistor to VEE can be used to establish the VOL level. Both VCC pins must always be used and should Logic Diagram 11C90 TL/F/9892 – 6 Note: This diagram is provided for understanding of logic operation only. It should not be used for evaluation of propagation delays as many internal functions are achieved more efficiently than shown. Count Sequence Table 11C90 Operating Mode Table 11C90 Inputs MS CE M1 M2 H L L L L X H L L L X X L H X X X L X H H e HIGH Voltage Level L e LOW Voltage Level X e Don’t Care TL/F/9892 – 7 Note: A HIGH on MS forces all Qs HIGH. 7 Output Response Set HIGH Hold d 11 d 10 d 10 Logic Diagram 11C91 TL/F/9892 – 8 Count Sequence Table 11C91 Operating Mode Table 11C91 Inputs MS CE M1 M2 H L L L L X H L L L X X L X H X X L H X Output Response Set HIGH Hold d6 d5 d5 H e HIGH Voltage Level L e LOW Voltage Level X e Don’t Care TL/F/9892 – 9 Note: A HIGH on MS forces all Qs HIGH. Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 11C90/91 D Device Number (basic) C QR Special Variations QR e Commercial grade device with burn-in Package Code D e Ceramic Dual In-Line Temperature Range C e Commercial (0§ C to a 85§ C) 8 9 11C90/11C91 650 MHz Prescalers Physical Dimensions inches (millimeters) 16 Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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