fax id: 3505 1I CD20 25 ICD2025 Motherboard Clock Generator Features • Three independent clock outputs: separate CPUCLK, SYSCLK and Buffered Reference Clock • Ideally suited for 386/486 motherboard applications • Phase-locked loop output range of 1.843 MHz − 100 MHz • Phase-locked loop oscillator input derived from single 14.31818 MHz crystal • Sophisticated internal loop-filter requires no external components or manufacturing tweaks as commonly required with external filters • Three-state oscillator control disables outputs for test purposes • 5V operation • Low-power, high-speed CMOS technology • Available in 16-pin SOIC package Functional Description A modern personal computer motherboard often requires many different crystal can oscillators. The System Logic family of frequency synthesis parts from Cypress/IC Designs replaces the large number of oscillators required to build such multi-function motherboards. These parts synthesize all the required frequencies in a single monolithic device, thus lowering manufacturing costs and significantly reducing the printed circuit borad space required. The ICD2025 is a low-cost approach to the generation of the 3 necessary clocks required by any PC motherboard. Logic Block Diagram SYSBUS 14.318 MHz fREF/ XTALIN XTALOUT Charge Pump Phase Detector ÷n 7 VCO CPUCLK Internal Loop Filter ÷m ROM Phase–LockedLoop Oscillator #1 7 C0 C1 C2 C3 SYSCLK PLL #2 S0 S1 S2 OE GND VDD AVDD ICD2025–2 Pin Configuration SOIC Top View SYSBUS 1 16 AVDD SYSCLK 2 15 CPUCLK OE 3 14 C3 GND 4 13 VDD fREF/XTALIN 5 12 S2 XTALOUT 6 11 C2 C0 7 10 C1 S0 8 9 S1 ICD2025–1 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 August 1994 – Revised April 1995 2025: 8/94 Revision: April 10, 1995 ICD2025 Pin Summary Name Number Description SYSBUS 1 Buffered 14.31818 MHz crystal output (z) SYSCLK 2 System clock output (see Table 2) OE 3 Output Enable three-states output when signal is LO. (pin has internal pull-up) GND 4 Ground fREF/ XTALIN[1] 5 Reference Oscillator input for all internal phase-locked loops (nominally from a parallel-resonant 14.31818 MHz crystal). Optionally PC System Bus Clock. XTALOUT[1] 6 Oscillator output to a reference crystal. C0 7 CPUCLK Select signal—Bit 0 (internal pull-up) S0 8 SYSCLK Clock Select signal—Bit 0 (internal pull-up) S1 9 SYSCLK Select signal—Bit 1 (internal pull-up) C1 10 CPUCLK Select signal—Bit 1 (internal pull-up) C2 11 CPUCLK Select signal—Bit 2 (internal pull-up) S2 12 SYSCLK Select signal—Bit 2 (internal pull-up) VDD 13 +5V to I/O Ring C3 14 CPUCLK Select signal—Bit 3 (internal pull-down) CPUCLK 15 CPU Clock Output (See CPUCLK Selection Table) AVDD 16 +5V to Analog Core Note: 1. For best accuracy, use a parallel-resonant crystal, assume CLOAD = 17 pF. Available Frequencies (MHz) SYSCLK CPUCLK 1.843 16.000 3.686 20.000 8.000 25.000 12.000 32.000 18.432 33.333 20.000 40.000 24.000 50.000 32.000 66.667 80.000 100.000 2 2025: 8/94 Revision: April 10, 1995 ICD2025 General Considerations Table 2. SYSCLK Selection CPU and System Clock Oscillator Selection The frequency value of the CPU clock output (CPUCLK) is selected by the four CPU clock select inputs: C0, C1, C2, and C3. This feature allows the ICD2025 to support different CPU speeds. The frequency value of the system clock output (SYSCLK) is selected by the three system clock selection inputs: S0, S1, and S2. The selection tables are shown in Table 1 and 2. At any time during operation, the select lines can be changed to select a different frequency. When this occurs, the internal phase-locked loop will immediately seek the newly selected frequency. During the transition period, the clock output will multiplex glitch-free to the 14.31818 MHz reference signal until the PLL settles to the new frequency. The timing for this transition is shown in AC Characteristics. Actual Freq. (MHz) Error (PPM) 0 0 0 0 0 40.000 39.812 4734 0 0 0 1 1 80.000 79.623 4734 0 0 1 0 2 33.333 33.322 320 0 0 1 1 3 66.667 66.645 335 0 1 0 0 4 25.000 25.000 0 0 1 0 1 5 50.000 50.000 0 0 1 1 0 6 16.000 15.923 4848 0 1 1 1 7 32.000 31.846 4848 1 0 0 0 8 20.000 19.906 4734 1 0 0 1 9 100.000 99.840 1600 1 0 1 0 10 40.000 39.812 4734 1 0 1 1 11 80.000 79.623 4734 1 1 0 0 12 33.333 33.322 320 1 1 0 1 13 66.667 66.645 335 1 1 1 0 14 25.000 25.000 0 1 1 1 1 15 50.000 50.000 0 S1 S0 0 0 0 0 18.432 18.431 62 0 0 1 1 20.000 20.003 167 0 1 0 2 24.000 23.998 80 0 1 1 3 1.843 1.843 144 1 0 0 4 12.000 11.999 80 1 0 1 5 8.000 8.001 167 1 1 0 6 3.686 3.687 144 1 1 1 7 32.000 32.005 167 Error (PPM) Output Frequency Accuracy The accuracy of the ICD2025 output frequencies depends on the target output frequencies. The tables within this document contain target frequencies that differ from the actual frequencies produced by the clock synthesizer. Table 1. CPUCLK Selection Desired Freq. C3 C2 C1 C0 Word (MHz) S2 Actual Desired Freq. Word Freq. (MHz) (MHz) The output frequencies of the ICD2025 are an integral fraction of the input (reference) frequency: f(OUT) = (2 × f(REF) × P/Q) Only certain output frequencies are possible for a particular reference frequency. However, the ICD2025 always produces an output frequency within 0.1% of the target frequencies listed, which is more than sufficient to meet standard system logic requirements. (Actual values are given in the tables.) Three-State Output Operation The OE signal, when pulled LOW, will three-state the SYSCLK, CPUCLK, and SYSBUF output lines. This supports procedures such as automated testing, where the clock must be disabled. The OE signal contains an internal pull-up but should be tied to VDD if not used. Short-term stability (also called bit-jitter) is a manifestation of the frequency synthesis process. The Cypress/IC Designs frequency synthesis parts have been designed with an emphasis on reduction of bit-jitter. The primary cause of this phenomenon is the dance of the VCO as it strives to maintain lock. Low-gain VCOs and sufficient loop filtering are design elements specifically included to minimize bit-jitter. The IC Designs families of frequency synthesis components are all guaranteed to operate at a jitter rate low enough for system logic applications. 3 2025: 8/94 Revision: April 10, 1995 ICD2025 Maximum Ratings Junction temperature.................................................... 125°C (Above which the useful life may be impaired. For user guidelines, not tested.) Operating Range Supply Voltage to Ground Potential .................−0.5V to +7.0V Ambient Temperature DC Input Voltage ..........................................−0.5V to VDD +0.5V Storage Temperature ....................................... −65°C to +150°C VDD & AVDD 0°C ≤ TAMBIENT ≤ 70°C 5V ± 5% Max soldering temperature (10 sec) ............................ 260°C Electrical Characteristics Over the Operating Range ICD2025 Parameter Description Test Conditions Min. Max. Unit VOH Output HIGH Voltage IOH = −4.0mA VOL Output LOW Voltage IOL = 4.0 mA VIH Input HIGH Voltage Except crystal inputs VIL Input LOW Voltage Wxcept crystal inputs IIH Input HIGH Current IIL Input LOW Current IOZ Output Leakage Current (Three-state) 10 µA IDD Power Supply Current Inputs @ VDD or GND 60 mA IADD Analog Power Supply Current 6 mA 2.4 V 0.4 2.0 V V 0.8 V VIH = VDD−0.5V 150 µA VIL = 0.5V −250 µA 4 2025: 8/94 Revision: April 10, 1995 ICD2025 Switching Characteristics Over the Operating Range[2] Parameter Name Drscription Min. Typ. Max. Unit f(REF) Reference Frequency Reference Oscillator nominal value 4 14.318 26 MHz t(REF) Ref Clock Period 1 ÷ f(REF) 38.5 69.8 2500 ns t1 Input Duty Cycle Duty cycle for the inputs defined as t1÷t(REF) 25% 50% 75% t2 Output Period CPUCLK output value t3 Output Duty Cycle Duty cycle for the outputs defined as t3÷t2 (measured at 2.5V) t4 Rise Time Rise time for the outputs into a 25 pF load t5 Fall Time t6 Three-State t7 10 100 MHz 544 1.84 MHz 40% 60% ns 4 ns Fall time for the outputs into a 25 pF load 4 ns Time for the outputs to go into three-state mode after OE signal assertion 12 ns Clk Valid Time for the outputs to recover from three-state mode after OE signal goes HIGH 12 ns tMUXREF Clk Stable Time required for the outputs to become valid after C0−C3 or S0−S2 select signals change value 6.9 msec tfreq1 freq1 Output Old frequency output tfreq2 freq2 Output New frequency output t8 f(REF) Mux Time Time clock output remains HIGH while output muxes to reference frequency 3.4 ns t ( REF ) --------------2 t9 tfreq2 Mux Time 5 t ( R EF ) 3 --------------2 Time clock output remains HIGH while output muxes to new frequency value ns tf req2 ------------2 Note: 2. Input capacitance is typically 10 pF, except for the crystal pads. 5 t freq2 3 ------------2 2025: 8/94 Revision: April 10, 1995 ICD2025 Switching Waveforms Rise and Fall Times t(REF) t1 f(REF) t2 CPUCLK SYSCLK SYSBUS t3 t4 t5 90% 90% 10% 10% ICD2025–3 Three-State Timing OE t6 t7 THREE–STATEOUTPUT CPUCLK SYSCLK ICD2025–4 Selection Timing Original Frequency VCO Settle Time New Frequency S0 S1 tMUXREF (Internal Timeout) VCLKOUT tfreq1 t(REF) t8 t9 tfreq2 ICD2025–5 6 2025: 8/94 Revision: April 10, 1995 ICD2025 Test Circuit VDD 22Ω 16 .01 µF 4 22 µF VDD 13 .01 µF OUTPUTS CLOAD ICD2025–6 Note: All capacitors should be placed as close to each pin as possible. © Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 2025: 8/94 Revision: April 10, 1995 ICD2025 Ordering Information[3] Ordering Code ICD2025− Package Name S1 Operating Range Package Type 16-Pin SOIC Commercial[4] Notes: 3. Contact your local Cypress representative. 4. 0°C to +70°C Example: order ICD2025SC for the ICD2025, 16-pin plastic SOIC, commercial temperature range device. Document #: 38−00398 Package Diagram 16-Lead Molded SOIC S1 ICD2025–7 8