TPS3306-15, TPS3306-18, TPS3306-20, TPS3306-25, TPS3306-33 DUAL PROCESSOR SUPERVISORY CIRCUITS WITH POWER-FAIL SLVS290 – APRIL 2000 D D D D D D D D D D D Dual Supervisory Circuits With Power-Fail for DSP and Processor-Based Systems Voltage Monitor for Power-Fail or Low-Battery Warning Watchdog Timer With 0.8 Second Time-Out Power-On Reset Generator With Integrated 100 ms Delay Time Open-Drain Reset and Power-Fail Output Supply Current of 15 µA (TYP.) Supply Voltage Range . . . 2.7 V to 6 V Defined RESET Output From VDD ≥ 1.1 V MSOP-8 and SO-8 Packages Temperature Range . . . – 40°C to 85°C Applications Include – Multivoltage DSPs and Processors – Portable Battery-Powered Equipment – Embedded Control Systems – Intelligent Instruments – Automotive Systems D OR DGK PACKAGE (TOP VIEW) SENSE1 SENSE2 PFI GND 1 8 2 7 3 6 4 5 VDD WDI PFO RESET description The TPS3306 family is a series of supervisory circuits designed for circuit initialization which require two supply voltages, primarily in DSP and processor-based systems. The product spectrum of the TPS3306-xx is designed for monitoring two independent supply voltages of 3.3 V/1.5 V, 3.3 V/1.8 V, 3.3 V/2 V, 3.3 V/2.5 V, or 3.3 V/5 V. TYPICAL OPERATING CIRCUIT 3.3 V 1.5 V AVDD TPS3306–15 R1 1% R2 1% R3 R4 CVDD SENSE1 VDD DVDD SENSE2 WDI B_XF PFI PFO A_XF GND TMS320 VC5441 RESET RESET VSS VSSA Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • DALLAS, TEXAS 75265 1 TPS3306-15, TPS3306-18, TPS3306-20, TPS3306-25, TPS3306-33 DUAL PROCESSOR SUPERVISORY CIRCUITS WITH POWER-FAIL SLVS290 – APRIL 2000 description (continued) The various supervisory circuits are designed to monitor the nominal supply voltage, as shown in the following supply voltage monitoring table. SUPPLY VOLTAGE MONITORING DEVICE NOMINAL SUPERVISED VOLTAGE THRESHOLD VOLTAGE (TYP) SENSE1 SENSE2 SENSE1 SENSE2 TPS3306-15 3.3 V 1.5 V 2.93 V 1.4 V TPS3306-18 3.3 V 1.8 V 2.93 V 1.68 V TPS3306-20 3.3 V 2V 2.93 V 1.85 V TPS3306-25 3.3 V 2.5 V 2.93 V 2.25 V TPS3306-33 5V 3.3 V 4.55 V 2.93 V During power-on, RESET is asserted when the supply voltage VDD becomes higher than 1.1 V. Thereafter, the supervisory circuits monitor the SENSEn inputs and keep RESET active as long as SENSEn remains below the threshold voltage VIT. An internal timer delays the return of the RESET output to the inactive state (high) to ensure proper system reset. The delay time, td(typ) = 100 ms, starts after SENSE1 and SENSE2 inputs have risen above the threshold voltage VIT. When the voltage at SENSE1 or SENSE2 input drops below the threshold voltage VIT, the output becomes active (low) again. The integrated power-fail (PFI) comparator with separate open-drain (PFO) output can be used for low-battery detection, power-fail warning, or for monitoring a power supply other than the main supply. The TPS3306-xx devices integrate a watchdog timer that is periodically triggered by a positive or negative transition of WDI. When the supervising system fails to retrigger the watchdog circuit within the time-out interval, tt(out) = 0.50 s, RESET becomes active for the time period td . This event also reinitializes the watchdog timer. Leaving WDI unconnected disables the watchdog. The TPS3306-xx devices are available in either 8-pin MSOP or standard 8-pin SO packages. The TPS3306-xx family is characterized for operation over a temperature range of – 40°C to 85°C. AVAILABLE OPTIONS PACKAGED DEVICES TA –40_C to 85_C MARKING DGK PACKAGE SMALL OUTLINE (D) µ-SMALL OUTLINE (DGK) TPS3305-15D TPS3306-15DGK TIAIC TPS3305-18D TPS3306-18DGK TIAID TPS3305-20D TPS3306-20DGK TIAIE TPS3305-25D TPS3306-25DGK TIAIF TPS3305-33D TPS3306-33DGK TIAIG 2 POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • DALLAS, TEXAS 75265 TPS3306-15, TPS3306-18, TPS3306-20, TPS3306-25, TPS3306-33 DUAL PROCESSOR SUPERVISORY CIRCUITS WITH POWER-FAIL SLVS290 – APRIL 2000 description (continued) FUNCTION/TRUTH TABLES SENSE1>VIT1 0 SENSE2>VIT2 0 RESET 0 1 L 1 0 L 1 1 H L FUNCTION/TRUTH TABLES PFI>VIT 0→1 PFO TYPICAL DELAY L→H 0.5 µs 1→0 H→L 0.5 µs functional block diagram TPS3306 SENSE 1 R1 VDD + _ SENSE 2 R3 R2 R4 RESET RESET Logic + Timer + _ GND Reference Voltage of 1.25 V Oscillator PFO _ + PFI WDI Transition Detection Watchdog Logic + Timer 40 kΩ POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • DALLAS, TEXAS 75265 3 TPS3306-15, TPS3306-18, TPS3306-20, TPS3306-25, TPS3306-33 DUAL PROCESSOR SUPERVISORY CIRCUITS WITH POWER-FAIL SLVS290 – APRIL 2000 timing diagram SENSEn V(nom) VIT 1.1 V t WDI 1 tt(out) 0 t RESET 1 Undefined Behavior Undefined Behavior 0 t td td td RESET Because of Power-Down RESET Because of WDI RESET Because of a Power Drop Below VIT– RESET Because of Power-Up Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION GND 4 I Ground PFI 3 I Power-fail comparator input PFO 6 O Power-fail comparator output, open-drain RESET 5 O Active-low reset output, open-drain SENSE1 1 I Sense voltage input 1 SENSE2 2 I Sense voltage input 2 WDI 7 I Watchdog timer input VDD 8 I Supply voltage detailed description watchdog In a microprocessor- or DSP-based system, it is not only important to supervise the supply voltage, it is also important to ensure correct program execution. The task of a watchdog is to ensure that the program is not stalled in an indefinite loop. The microprocessor, microcontroller, or DSP has to typically toggle the watchdog input within 0.8 s to avoid a time out occurring. Either a low-to-high or a high-to-low transition resets the internal watchdog timer. If the input is unconnected or tied with a high impedance driver, the watchdog is disabled and will be retriggered internally. 4 POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • DALLAS, TEXAS 75265 TPS3306-15, TPS3306-18, TPS3306-20, TPS3306-25, TPS3306-33 DUAL PROCESSOR SUPERVISORY CIRCUITS WITH POWER-FAIL SLVS290 – APRIL 2000 detailed description (continued) saving current while using the watchdog The watchdog input is internally driven low during the first 7/8 of the watchdog time-out period, then momentarily pulses high, resetting the watchdog counter. For minimum watchdog input current (minimum overall power consumption), leave WDI low for the majority of the watchdog time-out period, pulsing it low-high-low once within 7/8 of the watchdog time-out period to reset the watchdog timer. If instead WDI is externally driven high for the majority of the time-out period, a current of 5 V/40 kΩ ≈ 125 µA can flow into WDI. VDD VIT t WDI t(tout) t RESET td td t Figure 1. Watchdog Timing power-fail comparator (PFI & PFO) An additional comparator is provided to monitor voltages other than the nominal supply voltage. The power-fail-input (PFI) will be compared with an internal voltage reference of 1.25 V. If the input voltage falls below the power-fail threshold (VPFI) of typ. 1.25 V, the power-fail output (PFO) goes low. If it goes above 1.25 V plus about 10 mV hysteresis, the output returns to high. By connecting 2 external resistors, it is possible to supervise any voltages above 1.25 V. The sum of both resistors should be about 1 MΩ, to minimize power consumption and also to assure that the current in the PFI pin can be neglected compared with the current through the resistor network. The tolerance of the external resistors should be not more than 1% to ensure minimal variation of sensed voltage. If the power-fail comparator is unused, connect PFI to ground and leave PFO unconnected. VPFI,trip = 1.25 V × R1 + R2 R2 V(SENSE) R1 1% VCC PFI R2 1% POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003 PFO TPS3306 GND • DALLAS, TEXAS 75265 5 TPS3306-15, TPS3306-18, TPS3306-20, TPS3306-25, TPS3306-33 DUAL PROCESSOR SUPERVISORY CIRCUITS WITH POWER-FAIL SLVS290 – APRIL 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VDD (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V All other pins (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Maximum low output current, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA Maximum high output current, IOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 5 mA Input clamp current, IIK (VI < 0 or VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Soldering temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260_C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GND. For reliable operation, the device must not be operated at 7 V for more than t = 1000 h continuously. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING DGK 424 mW 3.4 mW/°C 271 mW 220 mW D 725 mW 5.8 mW/°C 464 mW 377 mW recommended operating conditions at specified temperature range MIN Supply voltage, VDD 2.7 Input voltage at WDI and PFI, VI 0 Input voltage at SENSE1 and SENSE2, VI 0 High-level input voltage at WDI, VIH UNIT 6 V VDD+0.3 (VDD+0.3)VIT/1.25 V V 0.7xVDD Low-level input voltage at WDI, VIL Operating free-air temperature range, TA 6 POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003 MAX –40 • DALLAS, TEXAS 75265 V V 0.3×VDD 85 V °C TPS3306-15, TPS3306-18, TPS3306-20, TPS3306-25, TPS3306-33 DUAL PROCESSOR SUPERVISORY CIRCUITS WITH POWER-FAIL SLVS290 – APRIL 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOL Low-level output voltage TEST CONDITIONS RESET, PFO Power-up reset voltage (see Note 2) VSENSE1, VSENSE2 VIT Negative-going g g g input threshold voltage g (see Note 3) Vhys y IH(AV) Hysteresis VSENSEn Average high-level input current MAX 0.2 VDD = 3.3 V, IOL = 2 mA 0.4 VDD = 6 V, IOL = 3 mA 0.4 VDD ≥ 1.1 V, IOL = 20 µA VDD = 2 2.7 7 V to 6 V V, TA = 0°C to 85°C VDD = 2 2.7 7 V to 6 V V, TA = –40°C to 85°C PFI PFI TYP VDD = 2.7 V to 6 V, IOL = 20 µA PFI VSENSE1, VSENSE2 MIN 0.4 1.37 1.40 1.43 1.64 1.68 1.72 1.81 1.85 1.89 2.20 2.25 2.30 2.86 2.93 3 4.46 4.55 4.64 1.22 1.25 1.28 1.37 1.40 1.44 1.64 1.68 1.73 1.81 1.85 1.90 2.20 2.25 2.32 2.86 2.93 3.02 4.46 4.55 4.67 1.22 1.25 1.29 VIT = 1.25 V VIT = 1.40 V 10 VIT = 1.68 V VIT = 1.86 V 15 VIT = 2.25 V VIT = 2.93 V 20 VIT = 4.55 V WDI = VDD = 6 V Time average (dc = 88%) 40 –15 –20 WDI WDI = VDD = 6 V, 120 170 SENSE1 5 8 IH High-level input current SENSE2 VSENSE1 = VDD = 6 V VSENSE2 = VDD = 6 V IL II Low-level input current WDI WDI = 0 V, Input current PFI IDD Ci Supply current VDD, = 6 V VDD = 6 V, 0 V ≤ VI ≤ VDD V V 30 WDI = 0 V, VDD = 6 V, Time average (dc = 12%) Average low-level input current V mV 20 150 IL(AV) V 15 100 WDI UNIT µA 6 9 –120 –170 –25 15 µA µA 25 nA 40 µA Input capacitance VI = 0 V to VDD 10 pF NOTES: 2. The lowest supply voltage at which RESET becomes active. tr, VDD ≥ 15 µs/V. 3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic 0.1 µF) should be placed close to the supply terminals. POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • DALLAS, TEXAS 75265 7 TPS3306-15, TPS3306-18, TPS3306-20, TPS3306-25, TPS3306-33 DUAL PROCESSOR SUPERVISORY CIRCUITS WITH POWER-FAIL SLVS290 – APRIL 2000 timing requirements at VDD = 2.7 V to 6 V, RL = 1 MΩ, CL = 50 pF, TA = 25°C PARAMETER tw Pulse width TEST CONDITIONS SENSEn WDI VSENSEnL = VIT –0.2 V, VIH = 0.7 × VDD, MIN VSENSEnH = VIT +0.2 V VIL = 0.3 × VDD TYP MAX UNIT 6 µs 100 ns switching characteristics at VDD = 2.7 V to 6 V, RL = 1 MΩ, CL = 50 pF, TA = 25°C PARAMETER TEST CONDITIONS tt(out) Watchdog time out VI(SENSEn) ≥ VIT + 0.2 V, See timing diagram td Delay time VI(SENSEn) ≥ VIT + 0.2 V, See timing diagram tPHL Propagation (delay) time, high-to-low level output tPHL Propagation (delay) time, high-to-low level output tPLH Propagation (delay) time, low-to-high level output SENSEn to RESET MIN TYP MAX 0.5 0.8 1.2 s 70 100 140 ms 1 5 µs 05 0.5 1 µs VIH = VIT +0.2 V, VIL = VIT –0.2 V PFI to PFO UNIT NORMALIZED SENSE THRESHOLD VOLTAGE vs FREE-AIR TEMPERATURE AT VDD SUPPLY CURRENT vs SUPPLY VOLTAGE 1.005 18 VDD = 6 V 1.004 16 14 1.003 12 I DD – Supply Current – µ A Normalized Input Threshold Voltage – VIT(TA), VIT(25 °C) TYPICAL CHARACTERISTICS 1.002 1.001 1 0.999 0.998 0.997 10 8 6 4 2 0 –2 –4 SENSEn = VDD TA = 25°C –6 0.996 0.995 –40 TPS3306–33 60 –15 10 35 TA – Free-Air Temperature – °C 85 –8 –10 –0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 VDD – Supply Voltage – V Figure 2 8 POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Figure 3 • DALLAS, TEXAS 75265 TPS3306-15, TPS3306-18, TPS3306-20, TPS3306-25, TPS3306-33 DUAL PROCESSOR SUPERVISORY CIRCUITS WITH POWER-FAIL SLVS290 – APRIL 2000 TYPICAL CHARACTERISTICS LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 2.8 6.5 2 1.6 1.2 VDD = 6 V 6 2.4 VOL – Low-Level Output Voltage – V VOL – Low-Level Output Voltage – V VDD = 2.7 V 85°C 0.8 –40°C 0.4 5.5 5 4.5 4 3.5 3 85°C 2.5 2 1.5 –40°C 1 0.5 0 0 1 0 2 3 4 5 6 7 8 9 10 11 12 13 IOL – Low-Level Output Current – mA 0 5 10 15 20 25 30 35 40 45 50 55 60 IOL – Low-Level Output Current – mA Figure 4 Figure 5 MINIMUM PULSE DURATION AT SENSE vs THRESHOLD OVERDRIVE tw – Minimum Pulse Duration at Vsense – µ s 10 VDD = 6 V 9 8 7 6 5 4 3 2 1 0 0 100 200 300 400 500 600 700 800 900 1000 SENSE – Threshold Overdrive – mV Figure 6 POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • DALLAS, TEXAS 75265 9 TPS3306-15, TPS3306-18, TPS3306-20, TPS3306-25, TPS3306-33 DUAL PROCESSOR SUPERVISORY CIRCUITS WITH POWER-FAIL SLVS290 – APRIL 2000 MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 0.010 (0,25) M 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 0.010 (0,25) 1 7 0°– 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047 / D 10/96 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 10 POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • DALLAS, TEXAS 75265 TPS3306-15, TPS3306-18, TPS3306-20, TPS3306-25, TPS3306-33 DUAL PROCESSOR SUPERVISORY CIRCUITS WITH POWER-FAIL SLVS290 – APRIL 2000 MECHANICAL DATA DGK (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE 0,38 0,25 0,65 8 0,25 M 5 0,15 NOM 3,05 2,95 4,98 4,78 Gage Plane 0,25 1 0°– 6° 4 3,05 2,95 0,69 0,41 Seating Plane 1,07 MAX 0,15 0,05 0,10 4073329/B 04/98 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-187 POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • DALLAS, TEXAS 75265 11 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated Powered by ICminer.com Electronic-Library Service CopyRight 2003