DATA SHEET DATA SHEET MOS INTEGRATED CIRCUIT µPD30550A VR5500A 64-/32-BIT MICROPROCESSOR DESCRIPTION The µPD30550A (VR5500A) is a member of the VRTM Series of RISC (Reduced Instruction Set Computer) microprocessors. It is a high-performance 64-/32-bit microprocessor that employs the RISC architecture developed by MIPSTM. The VR5500A allows selection of a 64-bit or 32-bit bus width for the system interface, and can operate using protocols compatible with the VR5000 Series and VR5432. Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing. • VR5500A User’s Manual (U16677E) FEATURES • MIPS 64-bit RISC architecture • High-speed operation processing • Two-way superscalar super pipeline • 300 MHz product: 603 MIPS 400 MHz product: 804 MIPS • High-speed translation lookaside buffer (TLB) • 64-/32-bit address/data multiplexed bus • Bus width selectable during reset • Bus protocol compatibility with existing products retained • Maximum operating frequency • 300 MHz product: Internal 300 MHz, external 133 MHz (48 entries) • Address space • Physical: 36 bits (64-bit bus selected) • Virtual: 40 bits (in 64-bit mode) 32 bits (32-bit bus selected) 31 bits (in 32-bit mode) • On-chip floating-point unit (FPU) • Supports sum-of-products instructions • On-chip primary cache memory 400 MHz product: Internal 400 MHz, external 133 MHz • External/internal multiplication factor selectable from ×2 to ×5.5 by increments of 0.5 • Conforms to MIPS I, II, III, and IV instruction sets. Also supports product-sum operation instruction, rotate instruction, register scan instruction, and instruction for low power mode. (instruction/data: 32 KB each) • Supports hardware debug function (N-Wire) • 2-way set associative • Supply voltage • Supports line lock feature Core block: 1.5 V ±5% (300 MHz product) 1.6 to 1.7 V (400 MHz product) I/O block: 3.3 V ±5%, 2.5 V ±5% The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. U16678EJ1V0DS00 (1st edition) Date Published April 2003 NS CP(K) Printed in Japan 2003 2001 µPD30550A APPLICATIONS • Set-top boxes • RAID • High-end embedded devices, etc. ORDERING INFORMATION Part Number Package µPD30550AF2-300-NN1 µPD30550AF2-400-NN1 Maximum Operating Frequency 272-pin plastic BGA (C/D advanced type) (29 × 29) 300 MHz 272-pin plastic BGA (C/D advanced type) (29 × 29) 400 MHz PIN CONFIGURATION • 272-pin plastic BGA (C/D advanced type) (29 × 29) µPD30550AF2-300-NN1 µPD30550AF2-400-NN1 Bottom View Top View 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AA Y W V U T R P N M L K J H G F E D C B A A B C D E F G H J K L M N P R T U V W Y AA Index mark 2 Data Sheet U16678EJ1V0DS µPD30550A (1/2) No. Pin Name No. Pin Name No. Pin Name No. Pin Name A1 VSS B17 SysAD27 D12 VSS H4 VDD A2 VSS B18 VDDIO D13 SysAD31 H18 VSS A3 VDDIO B19 VDDIO D14 VDD H19 VSS A4 VDDIO B20 VSS D15 SysAD60 H20 VSS A5 Reset# B21 VSS D16 VSS H21 SysAD21 A6 PReq# C1 VDDIO D17 SysAD26 J1 SysCmd7 A7 ValidIn# C2 VDDIO D18 VSS J2 SysCmd8 A8 ValidOut# C3 VSS D19 VSS J3 TIntSel A9 VSS C4 VSS D20 VDDIO J4 Int0# A10 SysADC7 C5 VSS D21 VDDIO J18 SysAD52 A11 SysADC3 C6 VDD E1 SysCmd0 J19 SysAD20 A12 SysADC1 C7 WrRdy# E2 DisDValidO# J20 SysAD51 A13 SysADC4 C8 VSS E3 DWBTrans# J21 SysAD19 A14 SysAD62 C9 SysID1 E4 O3Return# K1 Int1# A15 SysAD30 C10 VDD E18 SysAD57 K2 VSS A16 SysAD28 C11 SysADC2 E19 SysAD25 K3 VSS A17 SysAD59 C12 VSS E20 SysAD56 K4 VSS A18 VDDIO C13 SysAD63 E21 SysAD24 K18 VDD A19 VDDIO C14 VDD F1 SysCmd1 K19 VDD A20 VSS C15 SysAD29 F2 VSS K20 VDD A21 VSS C16 VSS F3 VSS K21 VDD B1 VSS C17 SysAD58 F4 VSS L1 Int2# B2 VSS C18 VDDIO F18 VDD L2 Int3# B3 VDDIO C19 VSS F19 VDD L3 Int4# B4 VDDIO C20 VDDIO F20 VDD L4 Int5# B5 ColdReset# C21 VDDIO F21 SysAD55 L18 SysAD17 B6 Release# D1 VDDIO G1 SysCmd2 L19 SysAD49 B7 ExtRqst# D2 VDDIO G2 SysCmd3 L20 SysAD18 B8 BusMode D3 VSS G3 SysCmd4 L21 SysAD50 B9 SysID2 D4 VSS G4 SysCmd5 M1 RMode#/BKTGIO# B10 VDD D5 IC G18 SysAD23 M2 VDD B11 SysADC6 D6 VDD G19 SysAD54 M3 VDD B12 VSS D7 RdRdy# G20 SysAD22 M4 VDD B13 SysADC0 D8 VSS G21 SysAD53 M18 VSS B14 VDD D9 SysID0 H1 SysCmd6 M19 VSS B15 SysAD61 D10 VDD H2 VDD M20 VSS B16 VSS D11 SysADC5 H3 VDD M21 VSS Caution Leave the IC pin open. Remark # indicates active low. Data Sheet U16678EJ1V0DS 3 µPD30550A (2/2) No. 4 Pin Name No. Pin Name No. Pin Name No. Pin Name N1 VDDIO T21 SysAD12 W2 VDDIO Y12 VDD N2 NMI# U1 NTrcClk W3 VSS Y13 SysAD3 N3 VDDIO U2 NTrcData0 W4 VSS Y14 VSS N4 BigEndian U3 NTrcData1 W5 VDDPA2 Y15 SysAD37 N18 SysAD15 U4 NTrcData3 W6 VSS Y16 SysAD39 N19 SysAD47 U18 SysAD10 W7 VDDIO Y17 SysAD40 N20 SysAD16 U19 SysAD42 W8 VDD Y18 VDDIO N21 SysAD48 U20 SysAD11 W9 JTDI Y19 VDDIO P1 VSS U21 SysAD43 W10 VSS Y20 VSS P2 VSS V1 NTrcData2 W11 SysAD1 Y21 VSS P3 VSS V2 NTrcEnd W12 VDD AA1 VSS P4 VSS V3 VSS W13 SysAD35 AA2 VSS P18 VDD V4 VSS W14 VSS AA3 VDDIO P19 VDD V5 VSSPA2 W15 SysAD38 AA4 VDDIO P20 VDD V6 VSS W16 VDD AA5 VDDPA1 P21 SysAD46 V7 VDDIO W17 SysAD9 AA6 VDDIO R1 DivMode0 V8 VDD W18 VSS AA7 IC R2 DivMode1 V9 JTMS W19 VSS AA8 JTDO R3 DivMode2 V10 VSS W20 VDDIO AA9 DrvCon R4 VDDIO V11 SysAD33 W21 VDDIO AA10 VSS R18 SysAD44 V12 VDD Y1 VSS AA11 SysAD0 R19 SysAD13 V13 SysAD4 Y2 VSS AA12 SysAD2 R20 SysAD45 V14 VSS Y3 VDDIO AA13 SysAD34 R21 SysAD14 V15 SysAD7 Y4 VDDIO AA14 SysAD36 T1 VDD V16 VDD Y5 VSSPA1 AA15 SysAD5 T2 VDD V17 SysAD41 Y6 SysClock AA16 SysAD6 T3 VDD V18 VSS Y7 JTRST# AA17 SysAD8 T4 VDD V19 VSS Y8 VDD AA18 VDDIO T18 VSS V20 VDDIO Y9 JTCK AA19 VDDIO T19 VSS V21 VDDIO Y10 VSS AA20 VSS T20 VSS W1 VDDIO Y11 SysAD32 AA21 VSS Caution Leave the IC pin open. Remark # indicates active low. Data Sheet U16678EJ1V0DS µPD30550A PIN NAMES BigEndian: Big endian PReq#: Processor request BKTGIO#: Break/trigger input/output RdRdy#: Read ready BusMode: Bus mode Release#: Release ColdReset#: Cold reset Reset#: Reset DisDValidO#: Disable delay ValidOut# RMode#: Reset mode DivMode(2:0): Divide mode SysAD(63:0): System address/data bus DrvCon: Driver control SysADC(7:0): System address/data check DWBTrans#: Doubleword block transfer ExtRqst#: External request SysClock: System clock IC Internally connected SysCmd(8:0): System command/data Int(5:0)#: Interrupt JTCK: JTAG clock SysID(2:0): System bus identifier JTDI: JTAG data input TIntSel: Timer interrupt selection JTDO: JTAG data output ValidIn#: Valid input JTMS: JTAG mode select ValidOut#: Valid output JTRST#: JTAG reset VDD: Power supply for CPU core NMI#: Non-maskable interrupt VDDIO: Power supply for I/O NTrcClk: N-Trace clock VDDPA1, VDDPA2: Quiet VDD for PLL bus identifier bus NTrcData(3:0) : N-Trace data output VSS: Ground NTrcEnd: N-Trace end VSSPA1, VSSPA2: Quiet VSS for PLL O3Return#: Out-of-Order Return mode WrRdy#: Write ready Remark # indicates active low. Data Sheet U16678EJ1V0DS 5 µPD30550A INTERNAL BLOCK DIAGRAM VR5500A IFU BHT Instruction cache RAS IMQ Control signal SysAD bus (64/32 bits) SIU WTB RCU RF ICU RNRF RS EXU CP0 Test interface SysClock ALU0 ALU1 BRU FPU/ MACU FPU LSU TLB Clock generator DCU Data cache SB RB 6 Data Sheet U16678EJ1V0DS µPD30550A CONTENTS 1. PIN FUNCTIONS ......................................................................................................................................8 1.1 List of Pin Functions .................................................................................................................................... 8 1.2 Recommended Connection of Unused Pins............................................................................................. 12 2. ELECTRICAL SPECIFICATIONS ..........................................................................................................14 3. PACKAGE DRAWING............................................................................................................................24 4. RECOMMENDED SOLDERING CONDITIONS .....................................................................................25 Data Sheet U16678EJ1V0DS 7 µPD30550A 1. PIN FUNCTIONS Remark # indicates active low. 1.1 List of Pin Functions (1) System interface signals Pin Name SysAD(63:0) I/O I/O Function System address/data bus A 64-bit bus for communication between the processor and external agent. The lower 32 bits (SysAD(31:0)) are used in 32-bit bus mode. SysADC(7:0) I/O System address/data check bus A bus for SysAD bus parity. Valid only during a data cycle. The lower 4 bits (SysADC(3:0)) are used in 32-bit bus mode. SysCmd(8:0) I/O System command/data ID bus A 9-bit bus that transfers command and data identifiers between the processor and external agent SysID(2:0) I/O System bus protocol ID These signals transfer request identifiers in the out-of-order return mode. The processor drives a valid identifier in synchronization with the activation of the ValidOut# signal. The external agent must drive valid identifiers in synchronization with the activation of the ValidIn# signal. ValidIn# Input Valid In A signal indicating that the external agent is driving a valid address or data onto the SysAD bus, a valid command or data identifier onto the SysCmd bus, or a valid request identifier onto the SysID bus in the out-of-order return mode. ValidOut# Output Valid out A signal indicating that the processor is driving a valid address or data onto the SysAD bus, a valid command or data identifier onto the SysCmd bus, or a valid request identifier onto the SysID bus in the out-of-order return mode. RdRdy# Input Read ready A signal indicating that the external agent is ready to accept a processor read request WrRdy# Input Write ready A signal indicating that the external agent is ready to accept a processor write request ExtRqst# Input External request A signal indicating that the external agent is requesting the right to use the system interface Release# Output Releases interface A signal indicating that the processor is releasing the system interface to a slave state PReq# Output Processor request A signal indicating that the processor has a request that is pending 8 Data Sheet U16678EJ1V0DS µPD30550A (2) Initialization interface signals Pin Name DivMode(2:0) (1/2) I/O Input Function Division mode These signals set the division ratio of PClock and SysClock as follows: 111: 5.5 110: 5 101: 4.5 100: 4 011: 3.5 010: 3 001: 2.5 000: 2 Set the input levels of these signals before a power-on reset. Make sure that the levels of these signals do not change while the VR5500A is operating. BigEndian Input Endian mode This signal sets the byte ordering for addressing. 1: Big endian 0: Little endian Set the input level of this signal before a power-on reset. Make sure that the level of this signal does not change while the VR5500A is operating. BusMode Input Bus mode This signal sets the bus width of the system interface. 1: 64 bits 0: 32 bits Set the input level of this signal before a power-on reset. Make sure that the level of this signal does not change while the VR5500A is operating. TIntSel Input Interrupt source select This signal sets the interrupt source to be assigned to the IP7 bit of the Cause register. 1: Timer interrupt 0: Int5# input and external write request (SysAD5) Set the input level of this signal before a power-on reset. Make sure that the level of this signal does not change while the VR5500A is operating. DisDValidO# Input ValidOut# delay enable 1: ValidOut# is active even while the address cycle is stalled 0: ValidOut# is active during the address issuance cycle only Set the input level of this signal before a power-on reset. Make sure that the level of this signal does not change while the VR5500A is operating. DWBTrans# Input Doubleword block transfer enable (valid in 32-bit bus mode only) 1: Disabled 0: Enabled Set the input level of this signal before a power-on reset. Make sure that the level of this signal does not change while the VR5500A is operating. Remark 1: High level, 0: Low level Data Sheet U16678EJ1V0DS 9 µPD30550A (2/2) Pin Name O3Return# I/O Input Function Out-of-Order Return mode This signal sets the protocol of the system interface. 1: Normal mode 0: Out-of-order return mode Set the input level of this signal before a power-on reset. Make sure that the level of this signal does not change while the VR5500A is operating. ColdReset# Input Cold reset This signal completely initializes the internal status of the processor. Deassert it in synchronization with SysClock. Reset# Input Reset This signal logically initializes the internal status of the processor. Deassert it in synchronization with SysClock. DrvCon Input Drive control This signal sets the impedance of the external output driver. 1: Low 0: Normal (recommended) Set the input level of this signal before a power-on reset. Make sure that the level of this signal does not change while the VR5500A is operating. Remark 1: High level, 0: Low level The O3Return#, DWBTrans#, DisDValidO#, and BusMode signals are used for determining the protocol of the system interface. The protocol is selected as follows in accordance with the setting of these signals. Protocol O3Return# DWBTrans# DisDValidO# BusMode VR5000 compatible 1 1 1 1 RM523x compatible 1 1 1 0 VR5432 native mode compatible 1 0 0 0 Out-of-order return mode 0 Arbitrary Arbitrary Arbitrary Remark 1: High level, 0:Low level RM523x is a product of PMC-Sierra, Inc. (3) Interrupt interface signals Pin Name Int(5:0)# I/O Input Function Interrupt These are general-purpose processor interrupt requests. The input states can be checked by the Cause register. Whether Int5# is acknowledged or not depends on the status of the TIntSel signal during reset. NMI# Input Non-maskable interrupt This is the non-maskable interrupt request. 10 Data Sheet U16678EJ1V0DS µPD30550A (4) Clock interface signals Pin Name SysClock I/O Input Function System clock Clock input to the processor VDDPA1 − VDD for PLL − VSS for PLL VDDPA2 Power supply for the internal PLL VSSPA1 VSSPA2 Ground for the internal PLL (5) Power supply Pin Name I/O Function VDD − Power supply pin for core VDDIO − Power supply pin for I/O VSS − Ground potential pin Caution The VR5500A uses two power supply pins. These power supply pins can be applied in any sequence. However, power must not be applied to one pin for 100 ms or longer while it is not applied to the other. (6) Test interface signals Pin Name I/O Function NTrcData(3:0) Output Trace data NTrcEnd Output Trace end Trace data output A signal that indicates the end of a trace data packet. NTrcClk Output Trace clock Clock for the test interface. The same clock as SysClock is output. RMode#/ I/O BKTGIO# Reset mode/break trigger I/O A debug reset mode input signal while the JTRST# signal is active. It serves as a break or trigger I/O signal during normal operation. JTDI Input JTAG data input JTDO Output JTAG data output Serial data input for JTAG Serial data output for JTAG. Output is performed in synchronization with the fall of JTCK. JTMS Input JTAG mode select This signal selects the JTAG test mode. JTCK Input JTAG clock input Serial clock input for JTAG. The maximum frequency is 33 MHz. There is no need for it to be synchronized with SysClock. JTRST# Input JTAG reset input A signal for initializing the JTAG test module. Data Sheet U16678EJ1V0DS 11 µPD30550A 1.2 Recommended Connection of Unused Pins (1) System interface pins (a) 32-bit bus mode The VR5500A allows selection of a SysAD bus width from 64 bits or 32 bits. When the 32-bit bus mode is selected, the VR5500A operates using only the required system interface pins. Therefore, set the unused pins as follows when operating the VR5500A in the 32-bit bus mode. Pin Name Recommended Connection of Unused Pins SysAD(63:32) Leave open SysADC(7:4) Leave open (b) Normal mode The VR5500A can process read/write transactions regardless of the order in which requests are issued in the out-of-order return mode. The SysID(2:0) signals are used to identify each request during this processing. Set these signals, which are not used in the normal mode, as follows. Pin Name Recommended Connection of Unused Pins SysID(2:0) Leave open (c) Parity bus The VR5500A allows selection of whether the data is protected using parity. When parity is used, the parity data is output from the processor or external agent to the SysADC bus. However, whether the parity is used or not is selected by software, so unless the program is started, the VR5500A cannot determine the operation of the SysADC bus. Therefore, care must be taken to prevent the SysADC bus from being left open or in a high-impedance state. When parity is not used, it is recommended to connect each pin of the SysADC bus to VDDIO via a resistor with a high resistance value. 12 Data Sheet U16678EJ1V0DS µPD30550A (2) Test interface pins The VR5500A can be used to perform testing and debugging with the device mounted on the board. The test interface pins are used for connection with the external debug tool during such debugging. Therefore set the test interface pins as follows when the debug function is not used and in the normal operation mode. Pin Name Recommended Connection of Unused Pins JTCK Pull up JTDI Pull up JTMS Pull up JTRST# Pull down JTDO Leave open NTrcClk Leave open NTrcData(3:0) Leave open NTrcEnd Leave open RMode#/BKTGIO# Pull up Data Sheet U16678EJ1V0DS 13 µPD30550A 2. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Parameter Supply voltage Note Input voltage Symbol Conditions Ratings Unit VDDIO −0.5 to +4.0 V VDD −0.5 to +2.0 V VDDP −0.5 to +2.0 V −0.5 to VDDIO + 0.3 V −1.5 to VDDIO + 0.3 V VI Pulse of less than 7 ns Operating case temperature TC −10 to +85 °C Storage temperature Tstg −40 to +125 °C Note The upper limit of the input voltage (VDDIO + 0.3) is +4.0 V. Cautions 1. Do not short-circuit two or more outputs at the same time. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The specifications and conditions shown in the following DC Characteristics and AC Characteristics sections are the ranges within which the product can normally operate and the quality can be guaranteed. Operating Conditions (1) 300 MHz product Parameter Supply voltage MIN. MAX. Unit 2.375 2.625 V 3.135 3.465 V VDD 1.425 1.575 V VDDP 1.425 1.575 V Symbol Conditions VDDIO Caution VDD can also be used with the voltage range of the 400 MHz product (1.6 to 1.7 V). In this case, internal operation at 300 MHz is guaranteed. The supply current of the core block in this case is the specified value of the 400 MHz product (MAX. 1.68 A). (2) 400 MHz product Parameter Supply voltage Caution MIN. MAX. Unit 2.375 2.625 V 3.135 3.465 V VDD 1.6 1.7 V VDDP 1.6 1.7 V Symbol Conditions VDDIO VDD can also be used with the voltage range of the 300 MHz product (1.425 to 1.575 V). In this case, internal operation at 300 MHz is guaranteed. The supply current of the core block in this case is the specified value of the 300 MHz product (MAX. 1.25 A). 14 Data Sheet U16678EJ1V0DS µPD30550A Supply Current Parameter Supply current of core block Symbol IDD MIN. Conditions 300 MHz product, during normal MAX. Unit 1.25 A 1.68 A 0.25 A 0.31 A operation, VDD = VDDP = 1.575 V 400 MHz product, during normal operation, VDD = VDDP = 1.7 V IDD_sb 300 MHz product, in standby mode, VDD = VDDP = 1.575 V 400 MHz product, in standby mode, VDD = VDDP = 1.7 V Remark The supply current in the I/O block varies depending on the application used. It is normally 20% IDD or lower. DC Characteristics (1) When VDDIO = 2.5 V ±5% (300 MHz product: TC = −10 to +85°C, VDDIO = 2.5 V ±5%, VDD = VDDP = 1.5 V ±5%) (400 MHz product: TC = −10 to +85°C, VDDIO = 2.5 V ±5%, VDD = VDDP = 1.6 to 1.7 V) Parameter Symbol Conditions Output voltage, high VOH VDDIO = MIN., IOH = −4 mA Output voltage, low VOL VDDIO = MIN., IOL = 4 mA Input voltage, high Note 1 Note 1 Input voltage, low Input voltage, high Input voltage, lowNote 2 MAX. 0.8 × VDDIO Unit V 0.4 V VIH 2.0 VDDIO + 0.3 V VIL −0.5 0.2 × VDDIO V −1.5 0.2 × VDDIO V VIHC 0.8 × VDDIO VDDIO + 0.3 V VILC −0.5 0.2 × VDDIO V −1.5 0.2 × VDDIO V Pulse of less than 7 ns Note 2 MIN. Pulse of less than 7 ns Input current leakage, high ILIH VI = VDDIO 5.0 µA Input current leakage, low ILIL VI = 0 V −5.0 µA Output current leakage, high ILOH VO = VDDIO 5.0 µA Output current leakage, low ILOL VO = 0 V −5.0 µA Notes 1. Does not apply to the SysClock pin. 2. Only applies to the SysClock pin. Data Sheet U16678EJ1V0DS 15 µPD30550A (2) When VDDIO = 3.3 V ±5% (300 MHz product: TC = −10 to +85°C, VDDIO = 3.3 V ±5%, VDD = VDDP = 1.5 V ±5%) (400 MHz product: TC = −10 to +85°C, VDDIO = 3.3 V ±5%, VDD = VDDP = 1.6 to 1.7 V) Parameter Symbol Conditions Output voltage, high VOH VDDIO = MIN., IOH = −4 mA Output voltage, low VOL VDDIO = MIN., IOL = 4 mA Input voltage, high Note 1 Note 1 Input voltage, low Input voltage, high Note 2 Input voltage, low MAX. 2.4 Unit V 0.4 V VIH 2.0 VDDIO + 0.3 V VIL −0.5 0.8 V −1.5 0.8 V VIHC 0.8 × VDDIO VDDIO + 0.3 V VILC −0.5 0.2 × VDDIO V −1.5 0.2 × VDDIO V Pulse of less than 7 ns Note 2 MIN. Pulse of less than 7 ns Input current leakage, high ILIH VI = VDDIO 5.0 µA Input current leakage, low ILIL VI = 0 V −5.0 µA Output current leakage, high ILOH VO = VDDIO 5.0 µA Output current leakage, low ILOL VO = 0 V −5.0 µA Notes 1. Does not apply to the SysClock pin. 2. Only applies to the SysClock pin. 16 Data Sheet U16678EJ1V0DS µPD30550A Power-on Sequence The VR5500A uses two power supply pins. These power supply pins can be applied in any sequence. However, power must not be applied to one pin for 100 ms or longer while it is not applied to the other. Parameter Power-on delay Symbol Conditions MIN. MAX. Unit 0 100 ms MIN. MAX. Unit tDF Capacitance (TA = 25°C, VDDIO = VDD = VDDP = 0 V) Parameter Symbol Conditions Input capacitance CIN fC = 1 MHz 5.0 pF Output capacitance COUT Unmeasured pins returned to 0 V 7.0 pF MAX. Unit AC Characteristics (300 MHz product: TC = −10 to +85, VDDIO = 2.5 V ±5%, 3.3 V ±5%, VDD = VDDP = 1.5 V ±5%) (400 MHz product: TC = −10 to +85, VDDIO = 2.5 V ±5%, 3.3 V ±5%, VDD = VDDP = 1.6 to 1.7 V) Clock parameters (1/2) Parameter Symbol Conditions MIN. System clock high-level width tCH 1.8 ns System clock low-level width tCL 1.8 ns Pipeline clock frequency Note System clock frequency 300 MHz product 200 300 MHz 400 MHz product 200 400 MHz 300 MHz DivMode = 2:1 100 133 MHz product DivMode = 2.5:1 80 120 MHz DivMode = 3:1 66.7 100 MHz DivMode = 3.5:1 57.2 85.7 MHz 50 75 MHz 44.5 66.6 MHz 40 60 MHz DivMode = 5.5:1 36.4 54.5 MHz 400 MHz DivMode = 2:1 100 133 MHz product DivMode = 2.5:1 80 133 MHz DivMode = 4:1 DivMode = 4.5:1 DivMode = 5:1 DivMode = 3:1 66.7 133 MHz DivMode = 3.5:1 57.2 114 MHz 50 100 MHz 44.5 88.8 MHz 40 80 MHz 36.4 72.7 MHz DivMode = 4:1 DivMode = 4.5:1 DivMode = 5:1 DivMode = 5.5:1 Note This is the frequency at which the operation of the internal PLL is guaranteed. Data Sheet U16678EJ1V0DS 17 µPD30550A Clock parameters (2/2) Parameter System clock cycle Symbol tCP Conditions MIN. MAX. Unit 300 MHz DivMode = 2:1 7.5 10 ns product DivMode = 2.5:1 8.3 12.5 ns DivMode = 3:1 10 15 ns DivMode = 3.5:1 11.7 17.5 ns DivMode = 4:1 13.3 20 ns 15 22.5 ns DivMode = 5:1 16.7 25 ns DivMode = 5.5:1 18.3 27.5 ns 400 MHz DivMode = 2:1 7.5 10 ns product DivMode = 2.5:1 7.5 12.5 ns DivMode = 3:1 7.5 15 ns DivMode = 3.5:1 8.8 17.5 ns DivMode = 4.5:1 DivMode = 4:1 10 20 ns DivMode = 4.5:1 11.3 22.5 ns DivMode = 5:1 12.5 25 ns DivMode = 5.5:1 13.8 27.5 ns System clock jitter tJ ±5 % System clock rise time tCR 1.2 ns System clock fall time tCF 1.2 ns 33 MHz MAX. Unit JTAG clock frequency Remarks 1. The system clock jitter is a cycle-to-cycle jitter. 2. The JTAG clock runs asynchronously to the system clock. System interface parameters Parameter Data output hold time Note 1 Data output delay time Data input setup time Data input hold time Note 1 Note 2 Note 2 Symbol Conditions tDM MIN. 1.0 tDO 5.0 tDS tDH ns ns 1.5 ns 300 MHz product 1.0 ns 400 MHz product 0.5 ns Notes 1. Applies to the Release#, ValidOut#, PReq#, SysAD(63:0), SysADC(7:0), SysCmd(8:0), and SysID(2:0) pins. 2. Applies to the ColdReset#, Reset#, Int(5:0)#, NMI#, ExtRqst#, RdRdy#, WrRdy#, ValidIn#, SysAD(63:0), SysADC(7:0), SysCmd(8:0), and SysID(2:0) pins. Load coefficient Parameter Load coefficient 18 Symbol Conditions CLD Data Sheet U16678EJ1V0DS MIN. MAX. Unit 1.0 ns/25 pF µPD30550A Measurement Conditions Measurement points SysClock 50% tDO tDM All output pins 50% Load conditions All output pins DUT CL = 50 pF Timing Charts Clock timing tCP tCH 80% SysClock 50% 20% tCL tCR Data Sheet U16678EJ1V0DS tCF 19 µPD30550A Clock jitter tJ tJ SysClock 50% System interface edge timing SysClock tDO tDH tDM SysAD(63:0), SysADC(7:0), SysCmd(8:0), SysID(2:0) tDS Output Output tDO tDM ValidOut#, Release#, PReq# Output Output tDS tDH ValidIn#, ExtRqst#, RdRdy#, WrRdy#, Int(5:0)#, NMI# ColdReset#, Reset# 20 Input Data Sheet U16678EJ1V0DS Input µPD30550A Clock relationships (DivMode = 2:1) Cycle 1 2 3 4 SysClock (input) PClock (internal) tDO tDM Note (output) Data Note (input) Data Data Data Data Data Data Data tDS tDH Note SysAD(63:0), SysADC(7:0), SysCmd(8:0), SysID(2:0) Power-on sequence tDF VDD VDDIO tDF 50% 50% Data Sheet U16678EJ1V0DS 21 µPD30550A Reset timing Power-on reset timing VDD Note 1 VDDIO Note 2 SysClock (input) ≥100 ms ≥64 K SysClock tDS ColdReset# (input) tDS ≥16 SysClock Reset# (input) Notes 1. 2. 1.425 V (300 MHz product), 1.6 V (400 MHz product) 2.375 V at 2.5 V operation or 3.135 V at 3.3 V operation Cold reset timing VDD H VDDIO H SysClock (input) ≥64 K SysClock tDS tDS ColdReset# (input) ≥16 SysClock tDS tDS Reset# (input) 22 Data Sheet U16678EJ1V0DS µPD30550A Warm reset timing VDD H VDDIO H SysClock (input) ≥16 SysClock ColdReset# (input) H tDS tDS Reset# (input) Data Sheet U16678EJ1V0DS 23 µPD30550A 3. PACKAGE DRAWING 272-PIN PLASTIC BGA (CAVITY DOWN ADVANCED TYPE) (29x29) D B A ZE ZD 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 E AA Y W V U T R P N M L K J H G F E D C B A INDEX AREA 4-C1.4 A A2 A1 detail of A part S A φb e y S φ x1 φ x2 M S A B M S A4 ITEM D E e A A1 A2 MILLIMETERS 29.00±0.20 29.00±0.20 1.27 1.75±0.30 0.60±0.10 1.15 A4 0.25MIN. b x1 x2 φ 0.75±0.15 y 0.20 ZD 1.80 ZE 0.30 0.15 1.80 P272F2-127-BA1 24 Data Sheet U16678EJ1V0DS µPD30550A 4. RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mounting Technology Manual (http://www.necel.com/pkg/en/mount/index.html) Table 4-1. Surface mounting Type Soldering Conditions µPD30550AF2-300-NN1: 272-pin plastic BGA (C/D advanced type) (29 × 29) µPD30550AF2-400-NN1: 272-pin plastic BGA (C/D advanced type) (29 × 29) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or Note higher), Count: Three times or less, Exposure limit: 3 days IR35-203-3 (after that, prebake at 125°C for 20 to 72 hours) Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. Data Sheet U16678EJ1V0DS 25 µPD30550A NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Note Reference document Electrical Characteristics for Microcomputer (U15170J) Note This document number is that of Japanese version. The related documents indicated in the publication may include preliminary versions. However, preliminary versions are not marked as such. 26 Data Sheet U16678EJ1V0DS µPD30550A Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics America, Inc. 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China Tel: 021-6841-1138 Fax: 021-6841-1137 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC Electronics Singapore Pte. Ltd. Novena Square, Singapore Tel: 6253-8311 Fax: 6250-3583 J02.11 Data Sheet U16678EJ1V0DS 27 µPD30550A VR is a trademark of NEC Electronics Corporation. MIPS is a registered trademark of MIPS Technologies, Inc. in the United States. Exporting this product or equipment that includes this product may require a governmental license from the U.S.A. for some countries because this product utilizes technologies limited by the export control regulations of the U.S.A. • The information in this document is current as of April, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. 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