0.35 µm CMOS Embedded Array EA-9HD Family .35 0 d e t a egr t n i y l igh t h n o i t a or r p e p n u e s g o dSecon arious macr reduction Multif derable cost Consi rray a d e d bed m e S O M C m µ New s t c u d o r P WHAT IS AN EMBEDDED ARRAY? An embedded array is a high-performance semi-custom LSI that uses in its internal area the basic cell of a gate array, and can integrate a large variety of macros, including the same type of RAM as a cell-based IC. With an embedded array, a highly functional, high-performance LSI of the cell-based IC class can be realized. Because it is possible to manufacture wafers and perform simulation in parallel, the end of simulation leaves only the wiring process to be completed, thus enabling the TAT up until sample completion to be reduced to the same level as for gate arrays. By using an embedded array as the initial mass-produced product of cell-based ICs, it is possible to construct a system in express time. Moreover, if the macro structure and gate scale levels are the same, the embedded array can be put to common use as a master wafer. Because of this, the cost of embedded arrays is lower than cell-based ICs, and it is possible to develop a variety of derivative products. Furthermore, because the circuitry is easier to modify, embedded arrays aid in risk reduction. FEATURES Highly Integrated, Super High-Speed, Low Power Consumption-Type Embedded Array Using 0.35 µm Process • Realizes the high-level function, high performance LSI • Easy derivative-product development or reworking of the cell-based IC class • Macro common to cell-based IC (CB-9/9VX) provided • TAT reduced to gate array level Family Name EA-9HD 3.3 V ±0.3 V Supply voltage Delay time Internal gatesNote 1 131 ps Input buffersNote 2 229 ps Output buffersNote 3 1396 ps 0.524 µW/MHz/cell (internal gates) Power consumption Notes 1. 2NAND power gate, fanout = 1, standard wiring length value 2. The value when fanout = 1, standard wiring length value 3. The value when load capacitance 15 pF 3-metal layer Part Number µPD65443 µPD65444 µPD65445 µPD65446 µPD65448 µPD65449 µPD65451 µPD65454 µPD65456 µPD65458 Number of I/O pads 172 196 216 268 327 380 436 516 588 708 Number of raw gates 76720 103032 128872 207000 314104 440832 592020 840768 1104432 1626628 Number of usable gates 42196 56667 70879 113850 172757 220416 296010 420384 552216 731982 4-metal layer Part Number µPD65461 µPD65464 µPD65466 µPD65468 µPD65469 µPD65470 µPD65471 Number of I/O pads 436 516 588 708 764 820 876 Number of raw gates 592020 840768 1104432 1626628 1906800 2203360 2521344 Number of usable gates 355212 504460 662659 894645 1048740 1211848 1386739 Remark The actual number of usable signal lines depends on the package and the number of power supply and GND pins used. 2 Pamphlet A13163EJ4V0PF Support of Variety of Pin Count Packages • 100- to 304-pin plastic QFP (fine-pitch) • 225- to 352-pin plastic BGA • 48- to 120-pin plastic TQFP • 256- to 696-pin tape BGA • 144-pin plastic LQFP Abundance of Macro Libraries Memory Macro Cell-based IC type • Single-port high-speed synchronous compiled RAM • Dual-port high-speed synchronous compiled RAM • Single-port high-density synchronous compiled RAM • Dual-port high-density synchronous compiled RAM • High-speed synchronous ROM Gate array type • Single-port asynchronous soft macro RAM • Dual-port asynchronous soft macro RAM • Single-port asynchronous compiled RAM • Dual-port asynchronous compiled RAM • Dual-port synchronous compiled RAM • FIFONote User Logic • Logic gates • Decoder • Adder • Multiplexer • Shift register PLL • PLL for skew adjustment • PLL for multiplication I/O Buffers CPU Peripheral Core • Serial interface • Timer/counter • Interrupt controller • UART + FIFO • Low noise buffer • High drive capacity buffer • PCI • GTL+ • HSTLNote Note Macros that are under development or under investigation. Pamphlet A13163EJ4V0PF 3 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Parameter Supply voltage Symbol Conditions VDD Ratings Unit –0.5 to +4.6 V Input voltage LVTTL interface buffer VI VI < VDD +0.5 V –0.5 to +4.6 V LVTTL interface buffer with fail safe VI VI < VDD +0.5 V –0.5 to +4.6 V VI VI < VDD +3.0 V –0.5 to +6.6 V LVTTL output buffer VO VO < VDD +0.5 V –0.5 to +4.6 V TTL 5-V output buffer VO VO < VDD +3.0 V –0.5 to +6.6 V 5-V output buffer for CMOS VO VO < VDD +3.0 V –0.5 to +6.6 V IO IOL = 1 mA (FV0A) 3 mA IOL = 2 mA (FV0B) 7 mA IOL = 3 mA (FO09) 10 mA IOL = 6 mA (FO04) 20 mA IOL = 9 mA (FO01) 30 mA IOL = 12 mA (FO02) 40 mA IOL = 18 mA (FO03) 60 mA IOL = 24 mA (FO06) 75 mA function TTL 5-V tolerant voltage interface buffer Output voltage Output current Note Operating ambient temperature TA –40 to +85 °C Storage temperature Tstg –65 to +150 °C Note Output current: Indicates the maximum value of the direct current that is allowed to flow through this output pin. Remark With the exception of the buffer with fail safe function, be sure to apply voltage to the I/O pins only after the supply voltage has been fixed. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. 4 Pamphlet A13163EJ4V0PF Recommended Operating Range Parameter Symbol Conditions MIN. TYP. MAX. Unit 3.30 3.60 V Supply voltage VDD LVTTL interface 3.00 High-level input voltage VIH (LVTTL input buffer with 2.0 VDD V Low-level input voltage VIL fail-safe function) 0 0.8 V Positive trigger voltage VP 1.4 2.4 V Negative trigger voltage VN 0.8 1.6 V Hysteresis voltage VH 0.3 1.5 V High-level input voltage VIH TTL 5-V tolerant voltage 2.0 5.5 V Low-level input voltage VIL interface 0 0.8 V Positive trigger voltage VP 1.4 2.4 V Negative trigger voltage VN 0.8 1.6 V Hysteresis voltage VH 0.3 1.5 V Input rise time tri 0 200 ns Input fall time tfi 0 200 ns Input rise time tri 0 10 ms Input fall time tfi 0 10 ms Schmitt input Schmitt input Normal input Schmitt input Remark When inputting a slow signal with a long rise/fall time, noise on a signal line may affect the operation. Therefore, use a Schmitt trigger input buffer. Because fluctuation on the power supply line due to simultaneous operation of output buffers reduces the capability of the Schmitt trigger input buffer, carefully determine pin placement. Pamphlet A13163EJ4V0PF 5 DC Characteristics (VDD = 3.3 V ±0.3 V) (1/3) Parameter Symbol Conditions MIN. TYP. MAX. Unit Note1 Static current consumption µPD65443, µPD65444, IDDS VI = VDD or GND 2.0 300 µA IDDS VI = VDD or GND 3.0 400 µA IDDS VI = VDD or GND 4.0 800 µA LVTTL output IOZ VO = VDD or GND ±10 µA TTL 5-V tolerant voltage output IOZ VO = VDD or GND ±10 µA 5-V tolerant voltage for CMOS IOZ VO = VDD or GND ±10 µA IR VPU = 5.5 V, RPU = 2 kΩ, 0.1 µA VO = GND –250 mA ±1.0 µA µPD65445, µPD65446, µPD65448, µPD65449, µPD65451, µPD65454, µPD65456 µPD65458 Note2 Off-state output current Note3 Output flow current 5-V tolerant output for CMOS Note4 Output short-circuit current VO = 3.0 V IOS Input leakage current Normal input II VI = VDD or GND With pull-up resistor (50 kΩ) II VI = GND –28 –83 –190 µA With pull-up resistor (5 kΩ) II VI = GND –280 –700 –1900 µA With pull-down resistor (50 kΩ) II VI = VDD 28 83 190 µA RPU VI = GND 18.9 39.8 107.1 kΩ RPU VI = GND 1.9 4.7 10.7 kΩ RPD VI = VDD 18.9 39.8 107.1 kΩ Note5 Pull-up resistor 50 kΩ Note5 Pull-up resistor 5 kΩ Pull-down resistor 50 kΩ 6 Note5 Pamphlet A13163EJ4V0PF DC Characteristics (VDD = 3.3 V ±0.3 V) (2/3) Parameter Symbol Conditions MIN. TYP. MAX. Unit Note6 Low-level output current 3.00Note7 mA 6.00 mA IOL 9.00 mA 12 mA buffer (FO02) IOL 12.00 mA 18 mA buffer (FO03) IOL 18.00 mA 24 mA buffer (FO06) IOL 24.00 mA 1 mA buffer (FV0A) IOL TTL 5-V tolerant voltage 1.00 mA 2 mA buffer (FV0B) IOL output type 2.00 mA 3 mA buffer (FV09) IOL VOL = 0.4 V 3.00 mA 6 mA buffer (FV04) IOL 6.00 mA 9 mA buffer (FV01) IOL 9.00 mA 12 mA buffer (FV02) IOL 12.00 mA 18 mA buffer (FV03) IOL 18.00 mA 24 mA buffer (FV06) IOL 24.00 mA 3 mA buffer (FY09) IOL 5-V tolerant voltage output 3.00 mA 6 mA buffer (FY04) IOL type for CMOS 6.00 mA 9 mA buffer (FY01) IOL VOL = 0.4 V 9.00 mA 12 mA buffer (FY02) IOL 12.00 mA 18 mA buffer (FY03) IOL 18.00 mA 24 mA buffer (FY06) IOL 24.00 mA 3 mA buffer (FO09) IOL LVTTL output type 6 mA buffer (FO04) IOL VOL = 0.4 V 9 mA buffer (FO01) Pamphlet A13163EJ4V0PF 7 DC Characteristics (VDD = 3.3 V ±0.3 V) (3/3) Parameter High-level output current Symbol Conditions MIN. TYP. MAX. Unit Note6 3 mA buffer (FO09) IOH LVTTL output type –3.00 mA 6 mA buffer (FO04) IOH VOH = 2.4 V –6.00 mA 9 mA buffer (FO01) IOH –9.00 mA 12 mA buffer (FO02) IOH –12.00 mA 18 mA buffer (FO03) IOH –18.00 mA 24 mA buffer (FO06) IOH –24.00 mA 1 mA buffer (FV0A) IOH TTL 5-V tolerant voltage –1.00 mA 2 mA buffer (FV0B) IOH output type –1.00 mA 3 mA buffer (FV09) IOH VOH = 2.4 V –3.00 mA 6 mA buffer (FV04) IOH –3.00 mA 9 mA buffer (FV01) IOH –3.00 mA 12 mA buffer (FV02) IOH –3.00 mA 18 mA buffer (FV03) IOH –6.00 mA 24 mA buffer (FV06) IOH –6.00 mA Low-level output voltage LVTTL output type VOL IOL = 0 mA 0.1 V LVTTL output type (with 5 kΩ pull-up resistor) VOL IOL = 0 mA 0.2 V TTL 5-V tolerant voltage output type VOL IOL = 0 mA 0.1 V 5-V tolerant voltage output type for CMOS VOL IOL = 0 mA 0.1 V LVTTL output type VOH IOH = 0 mA VDD – 0.1 V TTL 5-V tolerant voltage output type VOH IOH = 0 mA VDD – 0.2 V High-level output voltage Notes 1. When using I/O blocks (etc.) with pull-up/pull-down resistors incorporated, the static current consumption increases. 2. Because there is a bias toward the 5-V protection circuit in the TTL 5-V tolerant voltage and 5-V tolerant voltage for CMOS 3-state or I/O buffers, the output off-state current increases slightly. 3. When the LSI supply current is pulled up to a higher voltage in the CMOS I/O buffers, a flow current from the output pin to inside the LSI is generated. 4. The output short-circuit time is less than 1 second and for 1 LSI pin only. 5. The pull-up and pull-down resistances vary depending on the input and output voltages. 6. All the buffers with the same output drive capability have the same specifications. 7. 2.00 mA for a buffer with a 5 kΩ pull-up resistor. Remarks 1. The + and – symbols attached to the current values in the table indicate the direction of the current. The symbol is + when the current is flowing into the device, and – when flowing out of the device. 2. Blanks in the table indicate that the values are undergoing evaluation. 8 Pamphlet A13163EJ4V0PF AC Characteristics The values in the table below refer to when the supply voltage of the internal gate array block is 3.3 V. Parameter Symbol Conditions Toggle frequency ftog Internal toggle F/F (fanout = 2) Transfer delay time tPD Internal gates Fanout = 1, wiring length 0 mm MIN. TYP. 670 MAX. Unit MHz 94 ps Fanout = 1, standard wiring length 131 ps Standard load Internal gates, Fanout = 1, standard wiring length power gates, Standard load 2NAND Input buffers Fanout = 1, standard wiring length 108 ps 107 ps 94 ps 229 ps Standard load 222 ps Output buffer (FO01) CL = 15 pF 1396 ps Output rise time tr Output buffer (FO01) CL = 15 pF 2391 ps Output fall time tf Output buffer (FO01) CL = 15 pF 1872 ps Remark Standard load: Fanout = 2, wiring length 0 mm Standard wiring length: 145 µm/1 pin pair Pamphlet A13163EJ4V0PF 9 DEVELOPMENT TOOLS Easy interface with your EWS or PC Users can choose the following tools to their environment. Caution Some functions may not be supported. Make it sure before use. OPENCADTM V5.5 Configuration Tool Function NEC Tool Function simulator Interface Data Commercially Available Tool Interface ModelSimTM/Verilog-XLTM/ – NC-VerilogTM/VCSTM VdrawTM Schmatic editor Logic synthesis – Gate-level simulator Note 1 PWC/EDIF (2.0.0)/ TM V. sim Formal verifier – • Net list VerilogTM HDL Design Compiler ModelSim/Verilog-XL/NC-Verilog/VCS Formality/TuxedoTM-LEC/ – • Test pattern STANote 1 Tiara Fault simulationNote 2 C. FGRADETM Design for test TESTACT/NEC_SCAN/ ALBA ConformalTM-LEC PrimeTime – • Delay data file DFT Compiler/TetraMAXTM NEC_BSCAN/NEC_BIST/ TESTBUS Note 3 Floor planner • Timing limit CBIC : ace_floorplan – G/A : Galet Note 3 Layout and wiring Notes 1. 2. 3. Silicon EnsembleTM (Only CBIC) Galet Sign-off tool Tool not supported in the HPTM version Individually supported tool Remark Platform : SUNTM (SolarisTM)/HP (HP-UXTM) GUI : X11R5/MotifTM 1.2 OPENCAD, C. FGRADE, Vdraw, and V.sim are trademarks of NEC Corporation. Design Compiler is a registered trademark of Synopsys, Inc. in Japan. PrimeTime and Formality are registered trademarks of Synopsys, Inc. in the USA. Silicon Ensemble, Verilog, NC-Verilog, and Verilog-XL are trademarks of Cadence Design Systems, Inc. SUN and Solaris are trademarks of Sun Microsystems, Inc. VCS and TetraMAX are trademarks of Synopsys, Inc. HP and HP-UX are trademarks of Hewlett-Packard Co. Motif is a trademark of The Open Group(TOG)/(OSF). ModelSim is a trademark of Model Technology Inc. Tuxedo and Conformal are trademarks of Verplex Systems, Inc. 10 Pamphlet A13163EJ4V0PF The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. • The information in this document is current as of September, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. • NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4 Pamphlet A13163EJ4V0PF 11 For further information, please contact: NEC Corporation NEC Building 7-1, Shiba 5-chome, Minato-ku Tokyo 108-8001, Japan Tel: 03-3454-1111 http://www.ic.nec.co.jp/ [North & South America] [Europe] NEC Electronics Inc. 2880 Scott Blvd. Santa Clara, CA 95050-2554, U.S.A. Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 http://www.necel.com/ NEC Electronics (Europe) GmbH Oberrather Str. 4 40472 Düsseldorf, Germany Tel: 0211-6503-01 Fax: 0211-6503-327 http://www.ee.nec.de/ NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 011-6462-6810 Fax: 011-6462-6829 Sucursal en España Juan Esplandiu, 15 28007 Madrid, Spain Tel: 091-504-2787 Fax: 091-504-2860 Succursale Française 9, rue Paul Dautier, B.P. 52 78142 Velizy-Villacoublay Cédex France Tel: 01-3067-5800 Fax: 01-3067-5899 Filiale Italiana Via Fabio Filzi, 25/A 20124 Milano, Italy Tel: 02-667541 Fax: 02-66754299 Branch The Netherlands Boschdijk 187a 5612 HB Eindhoven The Netherlands Tel: 040-2445845 Fax: 040-2444580 [Asia & Oceania] NEC Electronics Hong Kong Limited 12/F., Cityplaza 4, 12 Taikoo Wan Road, Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 Seoul Branch 10F, ILSONG Bldg., 157-37, Samsung-Dong, Kangnam-Ku Seoul, the Republic of Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics Shanghai, Ltd. 7th Floor, HSBC Tower, 101Yin Cheng Road, Pudong New Area, Shanghai P.R. China Tel: 021-6841-1138 Fax: 021-6841-1137 NEC Electronics Taiwan Ltd. 7F, No. 363 Fu Shing North Road Taipei, Taiwan, R. O. C. Tel: 02-2719-2377 Fax: 02-2719-5951 NEC Electronics Singapore Pte. Ltd. 238A Thomson Road #12-01/10 Novena Square Singapore 307684 Tel: 253-8311 Fax: 250-3583 Branch Sweden P.O. Box 134 18322 Taeby, Sweden Tel: 08-6380820 Fax: 08-6380388 United Kingdom Branch Cygnus House, Sunrise Parkway Linford Wood, Milton Keynes MK14 6NP, U.K. Tel: 01908-691-133 Fax: 01908-670-290 G02.4 Document No. A13163EJ4V0PF00(4th edition) Date Published September 2002 N CP(K) © NEC Corporation 1997 Printed on recycled paper Printed in Japan