ETC 6MBP75TEA-060

SPECIFICATION
Device Name
:
IGBT - IPM
Type Name
:
6MBP75TEA060
Spec. No.
:
MS6M 0701
Fuji Electric Co.,Ltd.
Matsumoto Factory
Nov . 26 ‘02 K.Sekigawa
Nov . 26 ‘02 Nishiura
Nov .-26 -‘02 K.Yamada
T.Fujihira
MS6M 0701
a
1
22
H04-004-07
Revised Records
Date
Classification
Nov.-26-’02
enactment
Mar.-12-’03
Revision
Ind.
Content
Applied
date
Issued
date
a
Revision, Package outline
addition, caution for design
Drawn
K.Sekigawa
N.Matsuda
MS6M 0701
Checked
Nishiura
K.Yamada
Nishiura
K.Yamada
Approved
T.Fujihira
T.Fujihira
a
2
22
H04-004-06
a
1. Package Outline Drawings
Package type : P622
Dimensions in mm
MS6M 0701
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3
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H04-004-03
2.Pin Descriptions
Main circuit
Symbol
Description
P
Positive input supply voltage.
U
Output (U).
V
Output (V).
W
Output (W).
N
Negative input supply voltage.
B
No contact.
Control circuit
№
Symbol
①
GNDU High side ground (U).
②
ALMU
Alarm signal output (U).
③
VinU
Logic input for IGBT gate drive (U).
④
VccU
High side supply voltage (U).
⑤
GNDV High side ground (V).
⑥
ALMV
Alarm signal output (V).
⑦
VinV
Logic input for IGBT gate drive (V).
⑧
VccV
High side supply voltage (V).
⑨
GNDW High side ground (W).
⑩
ALMW Alarm signal output (W).
⑪
VinW
Logic input for IGBT gate drive (W).
⑫
VccW
High side supply voltage (W).
⑬
GND
Low side ground.
⑭
Vcc
Low side supply voltage.
⑮
Description
VinDB No contact.
⑯
VinX
Logic input for IGBT gate drive (X).
⑰
VinY
Logic input for IGBT gate drive (Y).
⑱
VinZ
Logic input for IGBT gate drive (Z).
⑲
ALM
Low side alarm signal output.
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3. Block Diagram
VccU
④
VinU
③
ALMU
②
a
Pre-Driver
RALM 1.5k
GNDU
①
VccV
⑧
VinV
⑦
ALMV
⑥
P
Vz
U
Pre-Driver
GNDV
⑤
VccW
⑫
VinW
⑪
ALMW
⑩
RALM 1.5k
Vz
V
Pre-Driver
GNDW
⑨
Vcc
⑭
VinX
⑯
RALM 1.5k
Vz
W
Pre-Driver
Vz
GND
VinY
⑬
⑰
Pre-Driver
Vz
VinZ
⑱
Pre-Driver
Vz
B
VinDB
⑮
ALM
⑲
RALM 1.5k
N
Pre-drivers include following functions
1.Amplifier for driver
2.Short circuit protection
3.Under voltage lockout circuit
4.Over current protection
5.IGBT chip over heating protection
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4.Absolute Maximum Ratings
Tc=25℃ unless otherwise specified.
Items
Symbol
Min.
Max.
Units
VDC
0
450
V
VDC(surge)
0
500
V
Vsc
200
400
V
Vces
0
600
V
DC
Ic
-
75
A
1ms
Icp
-
150
A
Duty=75.0% *2
-Ic
-
75
A
Pc
-
198
W
Supply Voltage of Pre-Driver *4
Vcc
-0.5
20
V
Input Signal Voltage *5
Vin
-0.5
Vcc+0.5
V
Input Signal Current
Iin
-
3
mA
Alarm Signal Voltage *6
VALM
-0.5
Vcc
V
Alarm Signal Current *7
IALM
-
20
mA
Tj
-
150
℃
Operating Case Temperature
Topr
-20
100
℃
Storage Temperature
Tstg
-40
125
℃
Solder Temperature *8
Tsol
-
260
Viso
-
AC2500
V
-
-
3.5
Nm
Bus Voltage
DC
(between terminal P and N)
Surge
Shortoperating
Inverter
Collector-Emitter Voltage *1
Collector Current
Collector Power Dissipation One transistor *3
Junction Temperature
Isolating Voltage
(Terminal to base, 50/60Hz sine wave 1min.)
Screw Torque
Mounting (M5)
Note
*1 :Vces shall be applied to the input voltage between terminal P and U or V or W,
N and U or V or W
*2 : 125℃/FWD Rth(j-c)/(Ic×VF MAX)=125/0.855/(75×2.6)×100=75.0%
*3 : Pc=125℃/IGBT Rth(j-c)=125/0.63=198W [Inverter]
*4 : VCC shall be applied to the input voltage between terminal No.4 and 1, 8 and 5,
12 and 9, 14 and 13
*5 : Vin shall be applied to the input voltage between terminal No.3 and 1, 7 and 5, 11 and 9,
16,17,18 and 13.
*6 : VALM shall be applied to the voltage between terminal No.2 and 1, No6 and 5,
No10 and 9, No.19 and 13.
*7 : IALM shall be applied to the input current to terminal No.2,6,10 and 19.
*8 :Immersion time 10±1sec.
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5. Electrical Characteristics
Tj=25℃,Vcc=15V unless otherwise specified.
5.1 Main circuit
Item
Collector Current
Inverter
at off signal input
Collector-Emitter
saturation voltage
Forward voltage of FWD
Conditions
Symbol
ICES
VCE(sat)
VF
Min.
Typ.
Max.
Units
-
-
1.0
mA
Terminal
-
-
2.4
V
Chip
-
2.0
-
V
-
-
2.6
V
-
1.6
-
V
VCE=600V
Vin terminal open.
Ic=75A
-Ic=75A Terminal
Chip
Turn-on time
ton
VDC=300V、Tj=125℃
1.2
-
-
Turn-off time
toff
Ic=75A Fig.1,Fig.6
-
-
3.6
trr
VDC=300V
-
-
0.3
40
-
-
mJ
Min.
Typ.
Max.
Units
-
-
18
mA
-
-
65
mA
ON
1
1.35
1.7
OFF
1.25
1.6
1.95
-
8.0
-
Tc=-20℃ Fig.2
1.1
-
-
Tc=25℃ Fig.2
-
2.0
-
Tc=125℃ Fig.2
-
-
4.0
1425
1500
1575
Reverse recovery time
IF=75A Fig.1,Fig.6
PAV
Maximum AvalancheEnergy
internal wiring
inductance=50nH
(A non-repetition)
us
Main circuit wiring
inductance=54nH
5.2 Control circuit
Item
Supply current
of P-side pre-driver (one unit)
Supply current
Conditions
Symbol
Iccp
Iccn
Switching Frequency
: 0~15kHz
Tc=-20~125℃ Fig.7
of N-side pre-driver
Input signal threshold voltage
Input Zener Voltage
Alarm Signal Hold Time
Current Limit Resistor
Vin(th)
Vz
tALM
Rin=20kΩ
RALM Alarm terminal
MS6M 0701
V
V
ms
Ω
7
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H04-004-03
5.3 Protection Section (Vcc=15V)
Item
Symbol
Over Current Protection Level
Conditions
Min.
Typ.
Max.
Units
Ioc
Tj=125℃
113
-
-
A
tdoc
Tj=125℃
-
5
-
us
Tj=125℃ Fig.4
-
-
8
us
150
-
-
℃
of Inverter circuit
Over Current Protection Delay time
SC Protection Delay time
tsc
IGBT Chips Over Heating
TjOH
Protection Temperature Level
Surface
of IGBT Chips
Over Heating Protection Hysteresis
TjH
-
20
-
℃
Under Voltage Protection Level
VUV
11
-
12.5
V
VH
0.2
0.5
-
Symbol
Min.
Typ.
Max.
Units
IGBT
Rth(j-c)
-
-
0.63
℃/W
FWD
Rth(j-c)
-
-
0.855
Case to Fin Thermal Resistance with Compound
Rth(c-f)
-
0.05
-
Under Voltage Protection Hysteresis
6. Thermal Characteristics (Tc=25℃)
Item
Junction to Case
Inverter
Thermal Resistance *9
7. Noise Immunity
(Vdc=300V、Vcc=15V、Test Circuit Fig 5.)
Item
Conditions
Min.
Typ.
Max.
Units
Common mode
Pulse width 1us,polarity ±,10 minuets
±2.0
-
-
kV
±5.0
-
-
kV
Symbol
Min.
Typ.
Max.
Units
DC Bus Voltage
VDC
-
-
400
V
Power Supply Voltage of Pre-Driver
Vcc
13.5
15
16.5
V
-
2.5
-
3
Nm
Symbol
Min.
Typ.
Max.
Units
Wt
-
270
-
g
rectangular noise
Common mode
lightning surge
Judge:no over-current, no miss operating
Rise time 1.2us,Fall time 50usInterval 20s,10 times
Judge:no over-current, no miss operating
8. Recommended Operating Conditions
Item
Screw Torque (M5)
9. Weight
Item
Weight
*9:( For 1device ,Case is under the device )
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Vin
Vin(th)
On
Vin(th)
trr
90%
50%
Ic
90%
10%
toff
ton
Figure 1. Switching Time Waveform Definitions
Vge (Inside IPM)
Fault (Inside IPM)
off
off
/Vin
on
on
Gate On
Gate Off
normal
alarm
/ALM
tALM>Max.
tALM>Max.
①
②
tALM 2ms(typ.)
③
Fault:Over-current,Over-heat or Under-voltage
Figure 2. Input/Output Timing Diagram
Necessary conditions for alarm reset (refer to ① to ③ in figure2.)
① This represents the case when a failure-causing Fault lasts for a period more than tALM.
The alarm resets when the input Vin is OFF and the Fault has disappeared.
② This represents the case when the ON condition of the input Vin lasts for a period more
than tALM. The alarm resets when the Vin turns OFF under no Fault conditions.
③ This represents the case when the Fault disappears and the Vin turns OFF within tALM.
The alarm resets after lasting for a period of the specified time tALM.
off
/Vin
on
on
Ioc
Ic
/ALM
①
②
<tdoc
alarm
tdoc
Figure 3. Over-current Protection Timing Diagram
Period ①:
When a collector current over the OC level flows and the OFF command is input within
a period less than the trip delay time tdoc, the current is hard-interrupted and no alarm
is output.
Period ②:
When a collector current over the OC level flows for a period more than the trip delay
time tdoc, the current is soft-interrupted. If this is detected at the lower arm IGBTs,
an alarm is output.
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t SC
Ic
Ic
IALM
Ic
IALM
IALM
Figure.4 Definition of tsc
20k
DC
15V
VinU
CT
P
VccU
IPM
U
SW1
AC200V
GNDU
Vcc
V
VinX
W
+
20k
DC
15V
4700p
SW2
Noise
N
GND
Earth
Cooling
Fin
Figure 5. Noise Test Circuit
Vcc
20k
DC
15V
P
L
IPM
+
Vin
DC
300V
HCPL4504
GND
N
Ic
Figure 6. Switching Characteristics Test Circuit
Icc
DC
15V
A
Vcc
P
IPM
P.G
+8V
fsw
Vin
U
V
W
GND
N
Figure 7. Icc Test Circuit
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10. Truth table
10.1 IGBT Control
The following table shows the IGBT ON/OFF status with respect to the input signal Vin.
The IGBT turn-on when Vin is at “Low” level under no alarm condition.
Input
(Vin)
Output
(IGBT)
Low
ON
High
OFF
10.2 Fault Detection
(1) When a fault is detected at the high side, only the detected arm stops its output.
At that time the IPM dosen’t any alarm.
(2) When a fault is detected at the low side, all the lower arms stop their outputs and the IPM
outputs an alarm of the low side.
Fault
High side
U-phase
High side
V-phase
High side
W-phase
Low side
IGBT
Alarm Output
U-phase V-phase W-phase Low side
ALM-U
ALM-V
ALM-W
ALM
OC
OFF
*
*
*
L
H
H
H
UV
OFF
*
*
*
L
H
H
H
TjOH
OFF
*
*
*
L
H
H
H
OC
*
OFF
*
*
H
L
H
H
UV
*
OFF
*
*
H
L
H
H
TjOH
*
OFF
*
*
H
L
H
H
OC
*
*
OFF
*
H
H
L
H
UV
*
*
OFF
*
H
H
L
H
TjOH
*
*
OFF
*
H
H
L
H
OC
*
*
*
OFF
H
H
H
L
UV
*
*
*
OFF
H
H
H
L
TjOH
*
*
*
OFF
H
H
H
L
*:Depend on input logic.
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11. Cautions for design and application
1. Trace routing layout should be designed with particular attention to least stray capacity
between the primary and secondary sides of optical isolators by minimizing the wiring
length between the optical isolators and the IPM input terminals as possible.
フォトカプラとIPMの入力端子間の配線は極力短くし、フォトカプラの一次側と二次側の浮遊容量を小さくした
パターンレイアウトにして下さい。
2. Mount a capacitor between Vcc and GND of each high-speed optical isolator as close to
as possible.
高速フォトカプラのVcc-GND間に、コンデンサを出来るだけ近接して取り付けて下さい。
3. For the high-speed optical isolator, use high-CMR type one with tpHL, tpLH ≦ 0.8µs.
高速フォトカプラは、tpHL,tpLH≦0.8us、高CMRタイプをご使用ください。
4. For the alarm output circuit, use low-speed type optical isolators with CTR ≧ 100%.
アラーム出力回路は、低速フォトカプラCTR≧100%のタイプをご使用ください。
5. For the control power Vcc, use four power supplies isolated each. And they should be
designed to reduce the voltage variations.
制御電源Vccは、絶縁された4電源を使用してください。また、電圧変動を抑えた設計として下さい。
6. Suppress surge voltages as possible by reducing the inductance between the DC bus P
and N, and connecting some capacitors between the P and N terminals.
P-N間の直流母線は出来るだけ低インダクタンス化し、P-N端子間にコンデンサを接続するなどしてサージ
電圧を低減して下さい。
7. To prevent noise intrusion from the AC lines, connect a capacitor of some 4700pF between
the three-phase lines each and the ground.
ACラインからのノイズ侵入を防ぐために、3相各線-アース間に4700pF程のコンデンサを接続して下さい。
8. At the external circuit, never connect the control terminal ①GNDU to the main terminal
U-phase, ⑤GNDV to V-phase, ⑨GNDW to W-phase, and ⑬GND to N-phase. Otherwise,
malfunctions may be caused.
制御端子①GNDUと主端子U相、制御端子⑤GNDVと主端子V相、制御端子⑨GNDWと主端子W相、
制御端子⑬GNDと主端子Nを外部回路で接続しないで下さい。誤動作の原因になります。
9. Take note that an optical isolator’s response to the primary input signal becomes slow
if a capacitor is connected between the input terminal and GND.
入力端子-GND間にコンデンサを接続すると、フォトカプラ一次側入力信号に対する応答時間が長くなります
のでご注意ください。
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10. Taking the used isolator’s CTR into account, design with a sufficient allowance to decide
the primary forward current of the optical isolator.
フォトカプラの一次側電流は、お使いのフォトカプラのCTRを考慮し十分に余裕をもった設計にして下さい。
11. Apply thermal compound to the surfaces between the IPM and its heat sink to reduce
the thermal contact resistance.
接触熱抵抗を小さくするために、IPMとヒートシンクの間にサーマルコンパウンドを塗布して下さい。
12. Finish the heat sink surface within roughness of 10µm and flatness (camber) between screw
positions of 0 to +100µm. If the flatness is minus, the heat radiation becomes worse due to
a gap between the heat sink and the IPM. And, if the flatness is over +100µm, there is a danger
that the IPM copper base may be deformed and this may cause a dielectric breakdown.
ヒートシンク表面の仕上げは、粗さ10um以下、ネジ位置間
+100μm
0
での平坦度(反り)は、0~100umとして下さい。平坦度がマ
Heat sink
イナスの場合、ヒートシンクとIPMの間に隙間ができ放熱が
悪化します。また、平坦度が+100um以上の場合IPMの銅
ベースが変形し絶縁破壊を起こす危険性があります。
Mounting holes
13. This product is designed on the assumption that it applies to an inverter use. Sufficient
examination is required when applying to a converter use. Please contact Fuji Electric Co.,Ltd
if you would like to applying to converter use.
本製品は、インバータ用途への適用を前提に設計されております。コンバータ用途へ適用される場合は、
十分な検討が必要です。もし、コンバータへ適用される場合は御連絡ください。
14. Please see the 『Fuji IGBT-IPM R SERIES APPLICATION MANUAL』 and 『Fuji IGBT
MODULES N SERIES APPLICATION MANUAL』.
『富士IGBT-IPM Rシリーズ アプリケーションマニュアル』及び『IGBTモジュール Nシリーズ アプリケーション
マニュアル』を御参照ください。
15. There is thermal interference between nearby power devices, because the Econo IPM
is a compact package. Therefore you measure the case temperature just under the IGBT chips
that showed in report MT6M04545, and estimate the chip temperature.
Econo IPM はパッケージ小型化のため、パワー素子の熱干渉が考えられます。
その為、チップ温度推定は必ず MT6M04545 に示すチップ直下のケース温度を測定して行って下さい。
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12. Example of applied circuit 応用回路例
VccU
+5V
VccU
HCPL4504
20kΩ
0.1uF
“H“で
U相IGBTオン
+5V
P
④
+10uF
20kΩ
0.1uF
③
GNDU
①
②
W
⑧
+10uF
B
⑦
N
①
AC200V
U
V
V
M
②
W
⑧
+10uF
B
⑦
N
“H“で
V相IGBTオン
GNDV
20kΩ
0.1uF
“H“で
V相IGBTオン
GNDV
⑤
⑤
⑥
⑥
VccW
VccW
20kΩ
20kΩ
⑫
+10uF
0.1uF
“H“で
W相IGBTオン
GNDW
⑫
+10uF
0.1uF
“H“で
W相IGBTオン
⑪
⑪
GNDW
⑨
⑨
⑩
Vcc
20kΩ
0.1uF
“H“で
X相IGBTオン
⑭
⑩
IPM
Vcc
+10uF
⑯
GND
20kΩ
0.1uF
⑭
⑯
GND
0.1uF
⑰
“H“で
Y相IGBTオン
⑱
“H“で
Z相IGBTオン
⑬
20kΩ
⑰
20kΩ
0.1uF
20kΩ
⑱
⑮
⑮
⑲
⑲
TLP521
(a)In case of use of High side alarm
上アームアラーム使用の場合
IPM
+10uF
“H“で
X相IGBTオン
⑬
20kΩ
“H“で
Y相IGBTオン
0.1uF
C +
M
VccV
20kΩ
0.1uF
“H“で
Z相IGBTオン
AC200V
U
C +
VccV
0.1uF
P
④
+10uF
“H“で
U相IGBTオン
③
GNDU
HCPL4504
TLP521
(b)In case of no use of High side alarm
上アームアラーム不使用の場合
13. Package and Marking 梱包仕様
Please see the MT6M4140 which is packing specification of IPM.
IPM 梱包仕様書 MT6M4140を御参照ください。
14. Cautions for storage and transportation 保管、運搬上の注意
・ Store the modules at the normal temperature and humidity (5 to 35°C, 45 to 75%).
常温常湿(5~35℃、45~75%)で保存して下さい。
・ Avoid a sudden change in ambient temperature to prevent condensation on the module
surfaces.
モジュールの表面が結露しないよう、急激な温度変化を避けて下さい。
・ Avoid places where corrosive gas generates or much dust exists.
腐食性ガスの発生場所、粉塵の多い場所は避けて下さい。
・ Store the module terminals under unprocessed conditions
モジュールの端子は未加工の状態で保管すること。.
・ Avoid physical shock or falls during the transportation.
運搬時に衝撃を与えたり落下させないで下さい。
15. Scope of application 適用範囲
This specification is applied to the IGBT-IPM (type: 6MBP75TEA060).
本仕様書は、IGBT-IPM (型式:6MBP75TEA060)に適用する。
16. Based safety standards 準拠安全規格
UL1557
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18. Reliability Test Items
Test
categories
Test items
Environment Tests
Mechanical Tests
1 Terminal strength
端子強度
(Pull test)
2 Mounting Strength
締付け強度
3 Vibration
振動
Reference norms
EIAJ
ED-4701
Test methods and conditions
Pull force
: 20 N (main terminal)
10 N (control terminal)
Test time
: 10 ±1 sec.
Screw torque
: 2.5 ~ 3.5 N・m (M5)
Test time
: 10 ±1 sec.
Range of frequency
: 10~500 Hz
Sweeping time
: 15 min.
Acceleration
: 100 m/s2
Sweeping direction
: Each X,Y,Z axis
Test time
: 6 hr. (2hr./direction)
4 Shock
Maximum acceleration : 5000 m/s2
Pulse width
1.0 ms
衝撃
Direction
: Each X,Y,Z axis
Test time
: 3 times/direction
5 Solderabitlity
Solder temp.
: 235 ±5 ℃
はんだ付け性
Immersion duration
: 5.0 ±0.5 sec.
Test time
: 1 time
Each terminal should be Immersed in solder
within 1~1.5mm from the body.
6 Resistance to
Solder temp.
: 260 ±5 ℃
soldering heat
Immersion time
: 10 ±1sec.
はんだ耐熱性
Test time
: 1 time
Each terminal should be Immersed in solder
within 1~1.5mm from the body.
1 High temperature Storage temp.
: 125 ±5 ℃
storage 高温保存 Test duration
: 1000 hr.
2 Low temperature Storage temp.
: -40 ±5 ℃
storage 低温保存 Test duration
: 1000 hr.
3 Temperature
Storage temp.
: 85 ±2 ℃
humidity storage Relative humidity
: 85 ±5%
Test duration
: 1000hr.
高温高湿保存
4 Unsaturated
Test temp.
: 120 ±2 ℃
pressure cooker
Atmospheric pressure : 1.7x105 Pa
: 85 ±5%
プレッシャークッカー Test humidity
Test duration
: 96 hr.
5 Temperature
Test temp.
: Minimum storage temp. -40 ±5℃
cycle
Maximum storage temp. 125 ±5℃
Normal temp.
5 ~ 35℃
温度サイクル
Dwell time
: Tmin ~ TN ~ Tmax ~ TN
1hr. 0.5hr. 1hr. 0.5hr.
Number of cycles
: 100 cycles
6 Thermal shock
+0
Test temp.
: High temp. side 100 -5 ℃
熱衝撃
+5
Fluid used
Dipping time
Transfer time
Number of cycles
:
:
:
:
Number Acceptof
ance
sample number
5
(1:0)
Test Method 402
methodⅡ
Test Method 403
Condition code B
5
(1:0)
5
(1:0)
Test Method 404
Condition code B
5
(1:0)
Test Method 303
Condition code A
5
(1:0)
Test Method 302
Condition code A
5
(1:0)
Test Method 201
5
(1:0)
Test Method 202
5
(1:0)
Test Method 103
Test code C
5
(1:0)
Test Method 103
Test code E
5
(1:0)
Test Method 105
5
(1:0)
Test Method 307
method Ⅰ
Condition code A
5
(1:0)
Test Method 401
MethodⅠ
Low temp. side 0 -0 ℃
Pure water (running water)
5 min. par each temp.
10 sec.
10 cycles
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Test
categories
Test items
1 High temperature
reverse bias
高温逆バイアス
Endurance
Endurance
Tests Tests
AcceptReference norms
Number
EIAJ
ance
of sample
ED-4701
number
Test methods and conditions
Test temp.
Bias Voltage
Bias Method
Test duration
Test temp.
Relative humidity
Bias Voltage
2 Temperature
humidity bias
高温高湿バイアス
Bias Method
Test duration
ON time
OFF time
Test temp.
3 Intermitted
operating life
(Power cycle)
断続動作
Number of cycles
: Ta = 125 ±5℃
(Tj ≦ 150 ℃)
: VC = 0.8×VCES
: Applied DC voltage to C-E
Vcc = 15V
: 1000 hr.
: 85 ±2 ℃
: 85 ±5 %
: VC = 0.8×VCES
Vcc = 15V
: Applied DC voltage to C-E
: 1000 hr.
: 2 sec.
: 18 sec.
: ∆ Tj=100 ±5deg
Tj ≦ 150 ℃, Ta=25 ±5℃
: 15000 cycles
Test Method 101
5
(1:0)
Test Method 102
5
(1:0)
5
(1:0)
Condition code C
Test Method 106
19. Failure Criteria
Item
Characteristic
Electrical
Leakage current
characteristic
Saturation voltage
Forward voltage
Unit
ICES
-
USL×2
mA
VCE(sat)
-
USL×1.2
V
VF
-
USL×1.2
V
IGBT
Rth(j-c)
-
USL×1.2
℃/W
resistance
FWD
Rth(j-c)
-
USL×1.2
℃/W
Ioc
LSL×0.8
USL×1.2
A
Alarm signal hold time
tALM
LSL×0.8
USL×1.2
ms
Over heating Protection
TcOH
LSL×0.8
USL×1.2
℃
Isolation voltage
inspection
Failure criteria
Lower limit Upper limit
Thermal
Over Current Protection
Visual
Symbol
Viso
Broken insulation
-
-
The visual sample
-
Note
Visual inspection
Peeling
Plating
and the others
LSL : Lower specified limit.
USL : Upper specified limit.
Note : Each parameter measurement read-outs shall be made after stabilizing the components at room
ambient for 2 hours minimum, 24 hours maximum after removal from the tests. And in case of the
wetting tests, for example, moisture resistance tests, each component shall be made wipe or dry
completely before the measurement.
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Warnings
1. This product shall be used within its absolute maximum rating (voltage, current, and temperature).
This product may be broken in case of using beyond the ratings.
製品の絶対最大定格(電圧,電流,温度等)の範囲内で御使用下さい。絶対最大定格を超えて使用すると、素子が
破壊する場合があります。 2. Connect adequate fuse or protector of circuit between three-phase line and this product to prevent
the equipment from causing secondary destruction.
万一の不慮の事故で素子が破壊した場合を考慮し、商用電源と本製品の間に適切な容量のヒューズ又はブレーカーを
必ず付けて2次破壊を防いでください。
3. When studying the device at a normal turn-off action, make sure that working paths of the turn-off
voltage and current are within the RBSOA specification. And ,when studying the device duty at
a short-circuit current non-repetitive interruption, make sure that the paths are also within the
avalanche proof(PAV) specification which is calculated from the snubber inductance, the IPM
inner inductance and the turn-off current. In case of use of IGBT-IPM over these specifications,
it might be possible to be broken.
通常のターンオフ動作における素子責務の検討の際には、ターンオフ電圧・電流の動作軌跡がRBSOA仕様内にある
ことを確認して下さい。また、非繰返しの短絡電流遮断における素子責務の検討に際しては、スナバーインダクタンスと
IPM内部インダクタンス及びターンオフ電流から算出されるアバランシェ耐量(PAV)仕様内である事を確認して下さい。
これらの仕様を越えて使用すると、素子が破壊する場合があります。
4. Use this product after realizing enough working on environment and considering of product's reliability
life. This product may be broken before target life of the system in case of using beyond the product's
reliability life.
製品の使用環境を十分に把握し、製品の信頼性寿命が満足できるか検討の上、本製品を適用して下さい。製品の信頼性
寿命を超えて使用した場合、装置の目標寿命より前に素子が破壊する場合があります。
5. If the product had been used in the environment with acid, organic matter, and corrosive gas
(For example : hydrogen sulfide, sulfurous acid gas), the product's performance and appearance
can not be ensured easily.
酸・有機物・腐食性ガス(硫化水素,亜硫酸ガス等)を含む環境下で使用された場合、製品機能・外観などの保証は
致しかねます。
6. The thermal stress generated from rise and fall of Tj restricts the product lifetime.
You should estimate the ΔTj from power losses and thermal resistance, and design the inverter lifetime
within the number of cycles provided from the power cycle curve. (Technical Rep. No.: MT6M4057)
製品の寿命は、接合温度の上昇と下降によって起こる熱ストレスで決まります。損失と熱抵抗から∆Tjを推定し、パワー
サイクル寿命カーブで決まるサイクル数以下で、インバータの寿命を設計して下さい(技術資料№:MT6M4057)。
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7. Never add mechanical stress to deform the main or control terminal.
The deformed terminal may cause poor contact problem.
主端子及び制御端子に応力を与えて変形させないで下さい。 端子の変形により、接触不良などを引き起こす場合が
あります。
8. If excessive static electricity is applied to the control terminals, the devices can be broken.
Implement some countermeasures against static electricity.
制御端子に過大な静電気が印加された場合、素子が破壊する場合があります。取り扱い時は静電気対策を
実施して下さい。
Caution
1. Fuji Electric is constantly making every endeavor to improve the product quality and reliability.
However, semiconductor products may rarely happen to fail or malfunction. To prevent accidents
causing injury or death, damage to property like by fire, and other social damage resulted from
a failure or malfunction of the Fuji Electric semiconductor products, take some measures to keep
safety such as redundant design, spread-fire-preventive design, and malfunction-protective design.
富士電機は絶えず製品の品質と信頼性の向上に努めています。しかし、半導体製品は故障が発生したり、誤動作する
場合があります。富士電機製半導体製品の故障または誤動作が、結果として人身事故・火災等による財産に対する
損害や社会的な損害を起こさないように冗長設計・延焼防止設計・誤動作防止設計など安全確保のための手段を
講じて下さい。
2. The application examples described in this specification only explain typical ones that used the Fuji
Electric products. This specification never ensure to enforce the industrial property and other rights,
nor license the enforcement rights.
本仕様書に記載してある応用例は、富士電機製品を使用した代表的な応用例を説明するものであり、本仕様書に
よって工業所有権、その他権利の実施に対する保障または実施権の許諾を行うものではありません。
3. The product described in this specification is not designed nor made for being applied to the equipment
or systems used under life-threatening situations. When you consider applying the product of this
specification to particular used, such as vehicle-mounted units, shipboard equipment, aerospace
equipment, medical devices, atomic control systems and submarine relaying equipment or systems,
please apply after confirmation of this product to be satisfied about system construction and required
reliability.
本仕様書に記載された製品は、人命にかかわるような状況下で使用される機器あるいはシステムに用いられることを
目的として設計・製造されたものではありません。本仕様書の製品を車両機器、船舶、航空宇宙、医療機器、原子力
制御、海底中継機器あるいはシステムなど、特殊用途へのご利用をご検討の際は、システム構成及び要求品質に
満足することをご確認の上、ご利用下さい。
If there is any unclear matter in this specification, please contact Fuji Electric Co., Ltd.
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