40 ns Propagation Delay, CMOS Optocoupler Technical Data HCPL-7720 HCPL-7721 HCPL-0720 HCPL-0721 Features • +5 V CMOS Compatibility • 20 ns max. Prop. Delay Skew • High Speed: 25 MBd • 40 ns max. Prop. Delay • 10 kV/µs Minimum Common Mode Rejection • –40 to 85°C Temp. Range • Safety and Regulatory Approvals UL Recognized 2500 V rms for 1 min. per UL 1577 for HCPL-072X, 3750 V rms for 1 min. per UL 1577 for HCPL-772X CSA Component Acceptance Notice #5 VDE 0884 – VIORM = 630 Vpeak for HCPL-772X Option 060 – VIORM = 560 Vpeak for HCPL-072X Option 060 Applications • Digital Fieldbus Isolation: CC-Link, DeviceNet, Profibus, SDS • AC Plasma Display Panel Level Shifting • Multiplexed Data Transmission • Computer Peripheral Interface • Microprocessor System Interface Description Available in either an 8-pin DIP or SO-8 package style respectively, the HCPL-772X or HCPL-072X optocouplers utilize the latest CMOS IC technology to achieve outstanding performance with very low power consumption. The HCPL-772X/072X require only two bypass capacitors for complete CMOS compatability. Basic building blocks of the HCPL-772X/072X are a CMOS LED driver IC, a high speed LED and a CMOS detector IC. A CMOS logic input signal controls the LED driver IC which supplies current to the LED. The detector IC incorporates an integrated Functional Diagram **VDD1 1 8 VDD2** VI 2 7 NC* * 3 6 VO 5 GND2 IO LED1 GND1 4 SHIELD TRUTH TABLE (POSITIVE LOGIC) VI, INPUT LED1 VO, OUTPUT H L OFF ON H L photodiode, a high-speed transimpedance amplifier, and a voltage comparator with an output driver. *Pin 3 is the anode of the internal LED and must be left unconnected for guaranteed data sheet performance. Pin 7 is not connected internally. **A 0.1 µF bypass capacitor must be connected between pins 1 and 4, and 5 and 8. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. 2 Selection Guide 8-Pin DIP (300 Mil) HCPL-7721 HCPL-7720 Small Outline SO-8 HCPL-0721 HCPL-0720 Data Rate 25 MB 25 MB PWD 6 ns 8 ns Ordering Information Specify Part Number followed by Option Number (if desired) Example HCPL-7720#XXX 060 = VDE0884 Option. 300 = Gull Wing Surface Mount Option (HCPL-7720 only). 500 = Tape and Reel Packaging Option. No Option and Option 300 contain 50 units (HCPL-772X), 100 units (HCPL-072X) per tube. Option 500 contain 1000 units (HCPL-772X), 1500 units (HCPL-072X) per reel. Option data sheets available. Contact Agilent sales representative or authorized distributor. Package Outline Drawing HCPL-772X 8-Pin DIP Package 9.65 ± 0.25 (0.380 ± 0.010) TYPE NUMBER 8 7 6 7.62 ± 0.25 (0.300 ± 0.010) 5 OPTION 060 CODE* 6.35 ± 0.25 (0.250 ± 0.010) DATE CODE A XXXXV YYWW 1 1.19 (0.047) MAX. 2 3 4 1.78 (0.070) MAX. 5° TYP. 4.70 (0.185) MAX. + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002) 0.51 (0.020) MIN. 2.92 (0.115) MIN. 1.080 ± 0.320 (0.043 ± 0.013) 0.65 (0.025) MAX. 2.54 ± 0.25 (0.100 ± 0.010) DIMENSIONS IN MILLIMETERS AND (INCHES). *OPTION 300 AND 500 NOT MARKED. 3 Package Outline Drawing HCPL-772X Package with Gull Wing Surface Mount Option 300 PAD LOCATION (FOR REFERENCE ONLY) 9.65 ± 0.25 (0.380 ± 0.010) 8 6 7 1.016 (0.040) 1.194 (0.047) 5 4.826 TYP. (0.190) 6.350 ± 0.25 (0.250 ± 0.010) 1 3 2 9.398 (0.370) 9.906 (0.390) 4 1.194 (0.047) 1.778 (0.070) 9.65 ± 0.25 (0.380 ± 0.010) 1.780 (0.070) MAX. 1.19 (0.047) MAX. 0.381 (0.015) 0.635 (0.025) 7.62 ± 0.25 (0.300 ± 0.010) 4.19 MAX. (0.165) 1.080 ± 0.320 (0.043 ± 0.013) 0.635 ± 0.25 (0.025 ± 0.010) 0.635 ± 0.130 2.54 (0.025 ± 0.005) (0.100) BSC DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES). + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002) 12° NOM. Package Outline Drawing HCPL-072X Outline Drawing (Small Outline SO-8 Package) 8 7 6 5 5.842 ± 0.203 (0.236 ± 0.008) 72XV YWW 3.937 ± 0.127 (0.155 ± 0.005) OPTION 060 CODE* TYPE NUMBER (LAST 3 DIGITS) PIN 1 ONE 2 3 0.381 ± 0.076 (0.016 ± 0.003) DATE CODE 4 1.270 BSG (0.050) 7° 5.080 ± 0.005 (0.200 ± 0.005) 3.175 ± 0.127 (0.125 ± 0.005) 45° X 0.432 (0.017) 0.228 ± 0.025 (0.009 ± 0.001) 1.524 (0.060) 0.152 ± 0.051 (0.006 ± 0.002) DIMENSIONS IN MILLIMETERS AND (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES). *OPTION 500 NOT MARKED. 0.305 MIN. (0.012) 4 TEMPERATURE – °C Solder Reflow Thermal Profile 260 240 220 200 180 160 ∆T = 145°C, 1°C/SEC ∆T = 115°C, 0.3°C/SEC 140 120 100 80 ∆T = 100°C, 1.5°C/SEC 60 40 20 0 0 1 2 3 4 5 6 7 8 9 10 11 12 TIME – MINUTES (NOTE: USE OF NON-CHLORINE ACTIVATED FLUXES IS RECOMMENDED.) Regulatory Information The HCPL-772X/072X have been approved by the following organizations: UL Recognized under UL 1577, component recognition program, File E55361. CSA Approved under CSA Component Acceptance Notice #5, File CA88324. TUV Rheinland (HCPL-072X Option 060) Approved according to VDE 0884/06.92, Certificate R9650938. VDE (HCPL-772X Option 060) Approved according to VDE 0884/06.92, File 6591-23-4880-1005. Insulation and Safety Related Specifications Parameter Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Symbol L(I01) L(I02) Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI All Agilent data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit Value 772X 072X Units 7.1 4.9 mm 7.4 4.8 mm 0.08 0.08 mm ≥ 175 ≥ 175 Volts IIIa IIIa Conditions Measured from input terminals to output terminals, shortest distance through air. Measured from input terminals to output terminals, shortest distance path along body. Insulation thickness between emitter and detector; also known as distance through insulation. DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1) board, minimum creepage and clearance requirements must be met as specified for individual equipment standards. For creepage, the shortest distance path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered. There are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. Creepage and clearance distances will also change depending on factors such as pollution degree and insulation level. 5 VDE 0884 Insulation Related Characteristics (Option 060) Description Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage ≤ 150 V rms for rated mains voltage ≤ 300 V rms for rated mains voltage ≤ 450 V rms Climatic Classification Pollution Degree (DIN VDE 0110/1.89) Maximum Working Insulation Voltage Input to Output Test Voltage, Method b† VIORM x 1.875 = VPR , 100% Production Test with tm = 1 sec, Partial Discharge < 5 pC Input to Output Test Voltage, Method a† VIORM x 1.5 = VPR, Type and Sample Test, tm = 60 sec, Partial Discharge < 5 pC Highest Allowable Overvoltage† (Transient Overvoltage, tini = 10 sec) Safety Limiting Values (Maximum values allowed in the event of a failure, also see Thermal Derating curve, Figure 11.) Case Temperature Input Current Output Power Insulation Resistance at TS, V10 = 500 V Symbol HCPL-772X Option 060 HCPL-072X Option 060 I-IV I-III VIORM VPR I-IV I-IV I-III 55/85/21 2 630 1181 55/85/21 2 560 1050 V peak V peak VPR 945 840 V peak VIOTM 6000 4000 V peak TS IS,INPUT PS,OUTPUT RIO 175 230 600 ≥ 109 150 150 600 ≥ 109 °C mA mW Ω Units †Refer to the front of the optocoupler section of the Isolation and Control Component Designer’s Catalog, under Product Safety Regulations section (VDE 0884), for a detailed description. Note: These optocouplers are suitable for “safe electrical isolation” only within the safety limit data. Maintenance of the safety data shall be ensured by means of protective circuits. Note: The surface mount classification is Class A in accordance with CECC 00802. Absolute Maximum Ratings Parameter Storage Temperature Ambient Operating Temperature[1] Supply Voltages Input Voltage Output Voltage Average Output Current Lead Solder Temperature Solder Reflow Temperature Profile Symbol Min. Max. Units Figure TS –55 125 °C TA –40 +85 °C VDD1, VDD2 0 5.5 Volts VI –0.5 VDD1 +0.5 Volts VO –0.5 VDD2 +0.5 Volts IO 10 mA 260°C for 10 sec., 1.6 mm below seating plane See Solder Reflow Temperature Profile Section Recommended Operating Conditions Parameter Ambient Operating Temperature Supply Voltages Logic High Input Voltage Logic Low Input Voltage Input Signal Rise and Fall Times Symbol TA VDD1, VDD2 VIH VIL t r, t f Min. –40 4.5 2.0 0.0 Max. +85 5.5 VDD1 0.8 1.0 Units °C V V V ms Figure 1, 2 6 Electrical Specifications Test conditions that are not specified can be anywhere within the recommended operating range. All typical specifications are at TA = +25°C, VDD1 = VDD2 = +5 V. Parameter DC Specifications Logic Low Input Supply Current Logic High Input Supply Current Output Supply Current Input Current Logic High Output Voltage Logic Low Output Voltage Symbol Min. Typ. Max. Units Test Conditions IDD1L 6.0 10.0 mA VI = 0 V IDD1H 1.5 3.0 mA VI = VDD1 IDD2L IDD2H II VOH 5.5 7.0 9.0 9.0 10 mA –10 4.4 4.0 VOL Switching Specifications Propagation Delay Time tPHL to Logic Low Output Propagation Delay Time tPLH to Logic High Output Pulse Width PW Data Rate PWD Pulse Width Distortion |tPHL - tPLH| Propagation Delay Skew tPSK Output Rise Time tR (10 - 90%) Output Fall Time tF (90 - 10%) Common Mode |CMH| Transient Immunity at Logic High Output Common Mode |CM L| Transient Immunity at Logic Low Output Input Dynamic Power CPD1 Dissipation Capacitance Output Dynamic Power CPD2 Dissipation Capacitance 5.0 4.8 0 µA V V V 0.5 0.1 0.1 1.0 20 40 ns 23 40 3 3 25 6 8 20 Fig. Note 2 IO = –20 µA, VI = VIH 1, 2 IO = -4 mA, VI = VIH IO = 20 µA, VI = VIL IO = 400 µA, VI = VIL IO = 4 mA, VI = VIL CL = 15 pF CMOS Signal Levels 3, 6 3 7 4 40 7721/0721 7720/0720 MBd ns ns 5 9 ns 8 ns 10 20 10 20 60 10 kV/µs VI = VDD1, VO > 0.8 VDD1, VCM = 1000 V VI = 0 V, VO > 0.8 V, VCM = 1000 V pF 6 7 7 Package Characteristics Parameter Input-Output Momentary 072X Withstand Voltage 772X Resistance (Input-Output) Capacitance (Input-Output) Input Capacitance Input IC Junction-to-Case -772X Thermal Resistance -072X Output IC Junction-to-Case -772X Thermal Resistance -072X Package Power Dissipation Notes: 1. Absolute Maximum ambient operating temperature means the device will not be damaged if operated under these conditions. It does not guarantee functionality. 2. The LED is ON when VI is low and OFF when VI is high. 3. tPHL propagation delay is measured from the 50% level on the falling edge of the VI signal to the 50% level of the falling edge of the VO signal. tPLH propagation delay is measured from the 50% level on the rising edge of the VI signal to the 50% level of the rising edge of the VO signal. 4. PWD is defined as |tPHL - tPLH|. %PWD (percent pulse width distortion) is equal to the PWD divided by pulse width. 5. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the recommended operating conditions. Symbol Min. VISO 2500 3750 Typ. Max. Units Vrms RI-O 1012 Ω Test Conditions Fig. RH ≤ 50%, t = 1 min., TA = 25°C VI-O = 500 Vdc CI-O 0.6 pF f = 1 MHz CI θjci 3.0 145 160 140 135 θjco PPD Note 8, 9, 10 8 11 °C/W 150 Thermocouple located at center underside of package mW 6. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common mode voltage slew rates apply to both rising and falling common mode voltage edges. 7. Unloaded dynamic power dissipation is calculated as follows: C PD * VDD2 * f + I DD * VDD, where f is switching frequency in MHz. 8. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together. 9. In accordance with UL1577, each HCPL-072X is proof tested by applying an insulation test voltage ≥ 3000 VRMS for 1 second (leakage detection current limit, II-O ≤ 5 µA). Each HCPL-772X is proof tested by applying an insulation test voltage ≥ 4500 Vrms for 1 second (leakage detection current limit. II-O ≤ 5 µA.) 10. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to your equipment level safety specification or Agilent Application Note 1074 entitled “Optocoupler InputOutput Endurance Voltage.” 11. CI is the capacitance measured at pin 2 (VI). 2.2 0 °C 25 °C 85 °C 3 2 27 1.9 1.8 1 0 29 0 °C 25 °C 85 °C 2.0 VITH (V) 4 VO (V) 2.1 TPLH, TPHL (ns) 5 1.7 0 1 2 3 4 5 VI (V) Figure 1. Typical Output Voltage vs. Input Voltage. 1.6 4.5 25 TPLH 23 TPHL 21 19 17 4.75 5 5.25 5.5 VDD1 (V) Figure 2. Typical Input Voltage Switching Threshold vs. Input Supply Voltage. 15 0 10 20 30 40 50 60 70 80 TA (C) Figure 3. Typical Propagation Delays vs. Temperature. 8 4 7 11 6 3 2 TF (ns) TR (ns) PWD (ns) 10 5 4 9 1 0 3 20 0 40 60 8 80 20 0 40 TA (C) 29 6 27 5 25 21 TPLH 3 2 19 1 17 15 15 20 25 30 35 40 45 0 15 50 20 25 STANDARD 8 PIN DIP PRODUCT 800 PS (mW) IS (mA) 700 600 500 400 300 (230) 200 100 0 0 25 50 75 100 125 150 175 200 TA – CASE TEMPERATURE – °C 35 40 45 50 Figure 8. Typical Pulse Width Distortion vs. Output Load Capacitance. OUTPUT POWER – PS, INPUT CURRENT – IS Figure 7. Typical Propagation Delays vs. Output Load Capacitance. 30 CI (pF) CI (pF) SURFACE MOUNT SO8 PRODUCT 800 PS (mW) IS (mA) 700 600 500 400 300 200 (150) 100 0 0 25 50 20 40 60 Figure 6. Typical Fall Time vs. Temperature. 4 TPHL 23 0 TA (C) Figure 5. Typical Rise Time vs. Temperature. PWD (ns) TPLH, TPHL (ns) 2 80 TA (C) Figure 4. Typical Pulse Width Distortion vs. Temperature. OUTPUT POWER – PS, INPUT CURRENT – IS 60 75 100 125 150 175 200 TA – CASE TEMPERATURE – °C Figure 9. Thermal Derating Curve, Dependence of Safety Limiting Value with Case Temperature per VDE 0884. 80 9 Application Information CMOS IC technology allowing CMOS logic to be connected directly to the inputs and outputs. Bypassing and PC Board Layout The HCPL-772X/072X optocouplers are extremely easy to use. No external interface circuitry is required because the HCPL-772X/072X use high-speed VDD1 As shown in Figure 10, the only external components required for proper operation are two bypass capacitors. Capacitor values should be between 0.01 µF and VDD2 8 1 0.1 µF. For each capacitor, the total lead length between both ends of the capacitor and the power-supply pins should not exceed 20 mm. Figure 11 illustrates the recommended printed circuit board layout for the HPCL-772X/072X. C1 C2 VI 72X YWW 2 NC 3 GND1 7 NC 6 VO 5 4 GND2 C1, C2 = 0.01 µF TO 0.1 µF Figure 10. Recommended Printed Circuit Board Layout. VDD1 VDD2 72X YWW VI C1 C2 VO GND1 GND2 C1, C2 = 0.01 µF TO 0.1 µF Figure 11. Recommended Printed Circuit Board Layout. Propagation Delay, PulseWidth Distortion and Propagation Delay Skew Propagation Delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propaga- tion delay from low to high (tPLH) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (tPHL) is the INPUT VI 50% 5 V CMOS 0V tPLH OUTPUT VO Figure 12. 90% 10% tPHL 90% 10% VOH 2.5 V CMOS VOL amount of time required for the input signal to propagate to the output, causing the output to change from high to low. See Figure 12. 10 Pulse-width distortion (PWD) is the difference between tPHL and tPLH and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 20 - 30% of the minimum pulse width is tolerable. Propagation delay skew, tPSK, is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays VI will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delay is large enough it will determine the maximum rate at which parallel data can be sent through the optocouplers. of optocouplers are switched either ON or OFF at the same time, tPSK is the difference between the shortest propagation delay, either tPLH or tPHL, and the longest propagation delay, either tPLH or tPHL. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either t PLH or tPHL, for any given group of optocouplers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating temperature). As illustrated in Figure 13, if the inputs of a group As mentioned earlier, tPSK can determine the maximum parallel data transmission rate. Figure 14 is the timing diagram of a typical parallel data application with both the clock and data lines being sent through the optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. In this case the data is assumed to be clocked off of the rising edge of the clock. DATA 50% INPUTS VO 2.5 V, CMOS CLOCK tPSK VI 50% DATA OUTPUTS VO tPSK CLOCK 2.5 V, CMOS tPSK Figure 13. Propagation Delay Skew Waveform. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure 14 shows that there will be uncertainty in both the data and clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or Figure 14. Parallel Data Transmission Example. some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice tPSK. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. The HCPL-772X/072X optocouplers offer the advantage of guaranteed specifications for propagation delays, pulse-width distortion, and propagation delay skew over the recommended temperature and power supply ranges. 11 Digital Field Bus Communication Networks CONTROLLER To date, despite its many drawbacks, the 4 - 20 mA analog current loop has been the most widely accepted standard for implementing process control BUS INTERFACE OPTICAL ISOLATION TRANSCEIVER FIELD BUS TRANSCEIVER TRANSCEIVER TRANSCEIVER TRANSCEIVER OPTICAL ISOLATION OPTICAL ISOLATION OPTICAL ISOLATION OPTICAL ISOLATION BUS INTERFACE BUS INTERFACE BUS INTERFACE BUS INTERFACE XXXXXX SENSOR YYY DEVICE CONFIGURATION MOTOR CONTROLLER MOTOR STARTER Figure 15. Typical Field Bus Communication Physical Model. Optical Isolation for Field Bus Networks To recognize the full benefits of these networks, each recommends providing galvanic isolation using Agilent optocouplers. Since network communication is bi-directional (involving receiving data from and transmitting data onto the network), two Agilent optocouplers are needed. By providing galvanic isolation, data integrity is retained via noise reduction and the elimination of false signals. In addition, the AC LINE NODE/APP SPECIFIC uP/CAN HCPL 772x/072x LOCAL NODE SUPPLY GALVANIC ISOLATION BOUNDARY HCPL 772x/072x 5 V REG. TRANSCEIVER DRAIN/SHIELD V+ (SIGNAL) V– (SIGNAL) V+ (POWER) V– (POWER) SIGNAL POWER NETWORK POWER SUPPLY Figure 16. Typical DeviceNet Node. systems. In today’s manufacturing environment, however, automated systems are expected to help manage the process, not merely monitor it. With the advent of digital field bus communication networks such as CC-Link, DeviceNet, PROFIBUS, and Smart Distributed Systems (SDS), gone are the days of constrained information. Controllers can now receive multiple readings from field devices (sensors, actuators, etc.) in addition to diagnostic information. The physical model for each of these digital field bus communication networks is very similar as shown in Figure 15. Each includes one or more buses, an interface unit, optical isolation, transceiver, and sensing and/or actuating devices. network receives maximum protection from power system faults and ground loops. Within an isolated node, such as the DeviceNet Node shown in Figure 16, some of the node’s components are referenced to a ground other than V- of the network. These components could include such things as devices with serial ports, parallel ports, RS232 and RS485 type ports. As shown in Figure 16, power from the network is used only for the transceiver and input (network) side of the optocouplers. Isolation of nodes connected to any of the three types of digital field bus networks is best achieved by using the HCPL-772X/072X optocouplers. For each network, the HCPL-772X/072X satisify the critical propagation delay and pulse width distortion requirements over the temperature range of 0°C to +85°C, and power supply voltage range of 4.5 V to 5.5 V. 12 Implementing CC-Link with the HCPL-772X/ 072X CC-Link (Control and Communication Link) is developed to merge control and information in the low-level network (field network) by PCs, thereby making the multivendor environment a reality. It has data control and message-exchange function, as well as bit control function, and operates at the speed up to 10 Mbps. Power Supplies and Bypassing The recommended CC-Link circuit is shown in Figure 17. Since the HCPL-772X/072X are fully compatible with CMOS logic level signals, the optocoupler is connected directly to the transceiver. Two bypass capacitors (with values between 0.01 µF and 0.1 µF) are required and should be located as close as RS485 TRANSCEIVER IC FIL possible to the input and output power supply pins of the HCPL772X/072X. For each capacitor, the total lead length between both ends of capacitor and the power supply pins should not exceed 20 mm. The bypass capacitors are required because of the high speed digital nature of the signals inside the optocoupler. VDD2 (5 V) VCC VCC HCPL-7720#500 VDD1 DA VI VDD1 (5 V) VDD2 10 K VO RD1 0.1 µ DB 0.1 µ GND1 GND DG GND1 GND2 SLD GND GND HCPL-7720#500 VDD2 VO VDD1 VI SD 0.1 µ 0.1 µ GND GND FG HCPL-2611#560 VOE VDD 1K VO HC14 0.1 µ NC + MPU BOARD OUTPUT – 390 GND HC14 NC 10 K HCPL-2611#560 VOE VDD 1K VO HC14 10 K Figure 17. Recommended CC-Link Application Circuit. 0.1 µ NC + SDGATEON – 390 GND NC HC14 13 Implementing DeviceNet and SDS with the HCPL-772X/072X With transmission rates up to 1 Mbit/s, both DeviceNet and SDS are based upon the same broadcast-oriented, communications protocol — the Controller Area Network (CAN). Three types of isolated nodes are recommended for use on these networks: Isolated Node Powered NODE/APP SPECIFIC uP/CAN HCPL 772x/072x ISOLATED SWITCHING POWER SUPPLY HCPL 772x/072x GALVANIC ISOLATION BOUNDARY REG. TRANSCEIVER DRAIN/SHIELD V+ (SIGNAL) V– (SIGNAL) V+ (POWER) V– (POWER) SIGNAL POWER NETWORK POWER SUPPLY by the Network (Figure 18), Isolated Node with Transceiver Powered by the Network (Figure 19), and Isolated Node Providing Power to the Network (Figure 20). Isolated Node Powered by the Network This type of node is very flexible and as can be seen in Figure 18, is regarded as “isolated” because not all of its components have the same ground reference. Yet, all components are still powered by the network. This node contains two regulators: one is isolated and powers the CAN controller, nodespecific application and isolated (node) side of the two optocouplers while the other is nonisolated. The non-isolated regulator supplies the transceiver and the non-isolated (network) half of the two optocouplers. Figure 18. Isolated Node Powered by the Network. Isolated Node with Transceiver Powered by the Network Figure 19 shows a node powered by both the network and another source. In this case, the transceiver and isolated (network) side of the two optocouplers are powered by the network. The rest of the node is powered by the AC line which is very beneficial when an application requires a significant amount of power. This method is also desirable as it does not heavily load the network. More importantly, the unique “dual-inverting” design of the HCPL-772X/072X ensure the network will not “lock-up” if either AC line power to the node is lost or the node powered-off. Specifically, when input power (VDD1) to the HCPL-772X/072X located in the transmit path is eliminated, a RECESSIVE bus state is ensured as the HCPL-772X/072X output voltage (VO) go HIGH. *Bus V+ Sensing It is suggested that the Bus V+ sense block shown in Figure 19 14 AC LINE NODE/APP SPECIFIC NON ISO 5V uP/CAN HCPL 772x/072x HCPL 772x/072x *HCPL 772x/072x GALVANIC ISOLATION BOUNDARY REG. TRANSCEIVER DRAIN/SHIELD V+ (SIGNAL) V– (SIGNAL) V+ (POWER) V– (POWER) SIGNAL POWER NETWORK POWER SUPPLY * OPTIONAL FOR BUS V + SENSE Figure 19. Isolated Node with Transceiver Powered by the Network. Isolated Node Providing Power to the Network Figure 20 shows a node providing power to the network. The AC line powers a regulator which provides five (5) volts locally. The AC line also powers a 24 volt isolated supply, which powers the network, and another five-volt regulator, which, in turn, powers AC LINE DEVICENET NODE NODE/APP SPECIFIC 5 V REG. uP/CAN HCPL 772x/072x ISOLATED SWITCHING POWER SUPPLY HCPL 772x/072x GALVANIC ISOLATION BOUNDARY 5 V REG. TRANSCEIVER DRAIN/SHIELD SIGNAL POWER Figure 20. Isolated Node Providing Power to the Network. V+ (SIGNAL) V– (SIGNAL) V+ (POWER) V– (POWER) be implemented. A locally powered node with an unpowered isolated Physical Layer will accumulate errors and become bus-off if it attempts to transmit. The Bus V+ sense signal would be used to change the BOI attribute of the DeviceNet Object to the “auto-reset” (01) value. Refer to Volume 1, Section 5.5.3. This would cause the node to continually reset until bus power was detected. Once power was detected, the BOI attribute would be returned to the “hold in bus-off” (00) value. The BOI attribute should not be left in the “auto-reset” (01) value since this defeats the jabber protection capability of the CAN error confinement. Any inexpensive low frequency optical isolator can be used to implement this feature. the transceiver and isolated (network) side of the two optocouplers. This method is recommended when there are a limited number of devices on the network that don’t require much power, thus eliminating the need for separate power supplies. More importantly, the unique “dual-inverting” design of the HCPL-772X/072X ensure the network will not “lock-up” if either AC line power to the node is lost or the node powered-off. Specifically, when input power (VDD1) to the HCPL-772X/072X located in the transmit path is eliminated, a RECESSIVE bus state is ensured as the HCPL-772X/072X output voltage (VO) go HIGH. 15 Power Supplies and Bypassing The recommended DeviceNet application circuit is shown in Figure 21. Since the HCPL-772X/ 072X are fully compatible with CMOS logic level signals, the optocoupler is connected directly to the CAN transceiver. Two bypass capacitors (with values between 0.01 and 0.1 µF) are required and should be located as close as possible to the input and output power-supply pins of the HCPL-772X/072X. For each GALVANIC ISOLATION BOUNDARY ISO 5 V 5V 1 VDD1 TX0 2 VIN 0.01 µF 3 LINEAR OR SWITCHING REGULATOR VDD2 8 + 0.01 µF 7 HCPL-772x HCPL-072x VO 6 4 GND1 TxD 0.01 µF 6 VO GND2 5 + 7 5 V+ 4 CAN+ 3 SHIELD 82C250 C4 0.01 µF 2 CAN– CANL REF GND GND1 4 1 V– VREF RXD 0.01 µF 3 D1 30 V HCPL-772x HCPL-072x VIN 2 8 VDD2 ISO 5 V VCC Rs 5 GND2 + CANH GND RX0 capacitor, the total lead length between both ends of the capacitor and the power supply pins should not exceed 20 mm. The bypass capacitors are required because of the highspeed digital nature of the signals inside the optocoupler. VDD1 1 5V Figure 21. Recommended DeviceNet Application Circuit. Implementing PROFIBUS with the HCPL-772X/072X An acronym for Process Fieldbus, PROFIBUS is essentially a twistedpair serial link very similar to RS485 capable of achieving high-speed communication up to 12 MBd. As shown in Figure 22, a PROFIBUS Controller (PBC) establishes the connection of a field automation unit (control or central processing station) or a field device to the transmission medium. The PBC consists of the line transceiver, optical isolation, frame character transmitter/receiver (UART), and the FDL/APP processor with the interface to the PROFIBUS user. PROFIBUS USER: CONTROL STATION (CENTRAL PROCESSING) OR FIELD DEVICE USER INTERFACE FDL/APP PROCESSOR UART PBC OPTICAL ISOLATION TRANSCEIVER MEDIUM Figure 22. PROFIBUS Controller (PBC). C1 0.01 µF 500 V R1 1M Power Supplies and Bypassing The recommended PROFIBUS application circuit is shown in Figure 23. Since the HCPL-772X/ 072X are fully compatible with CMOS logic level signals, the optocoupler is connected directly to the transceiver. Two bypass capacitors (with values between 0.01 and 0.1 µF) are required and should be located as close as possible to the input and output power-supply pins of the HCPL-772X/072X. For each capacitor, the total lead length between both ends of the capacitor and the power supply pins should not exceed 20 mm. The bypass capacitors are required because of the highspeed digital nature of the signals inside the optocoupler. Being very similar to multi-station RS485 systems, the HCPL-061N optocoupler provides a transmit disable function which is necessary to make the bus free after each master/slave transmission cycle. Specifically, the HCPL-061N disables the transmitter of the line driver by putting it into a high state mode. In addition, the HCPL-061N switches the RX/TX driver IC into the listen mode. The HCPL-061N offers HCMOS compatibility and the high CMR performance (1 kV/µs at VCM = 1000 V) essential in industrial communication interfaces. GALVANIC ISOLATION BOUNDARY 5V ISO 5 V 8 VDD2 VDD1 1 VIN 2 7 0.01 µF HCPL-772x 6 VO HCPL-072x Rx ISO 5 V 5 GND2 1 0.01 µF 3 A 0.01 µF GND1 4 3 ISO 5 V 1 VDD1 2 VIN Tx 0.01 µF 7 + RT B 7 SHIELD – DE GND 5 0.01 µF 1M HCPL-772x HCPL-072x VO 6 3 0.01 µF D 2 RE VDD2 8 6 SN75176B 4 5V R 8 VCC 4 GND1 GND2 5 ISO 5 V VCC 8 1 5V Tx ENABLE 1, 0 kΩ 680 Ω VE 7 2 ANODE 0.01 µF VO 6 3 CATHODE 4 GND 5 HCPL-061N www.semiconductor.agilent.com Figure 23. Recommended PROFIBUS Application Circuit. Data subject to change. Copyright © 1999 Agilent Technologies Obsoletes 5967-6174E (5/98) 5968-2122E (11/99)