a Rail-to-Rail High Output Current Operational Amplifiers OP179/OP279 FEATURES Rail-to-Rail Inputs and Outputs High Output Current: ⴞ60 mA Single Supply: +5 V to +12 V Wide Bandwidth: 5 MHz High Slew Rate: 3 V/s Low Distortion: 0.01% Unity-Gain Stable No Phase Reversal Short Circuit Protected Drives Capacitive Loads: 10 nF PIN CONFIGURATIONS APPLICATIONS Multimedia Telecom DAA Transformer Driver LCD Driver Low Voltage Servo Control Modems FET Drivers 8-Lead SOIC and TSSOP SO-8 (R) and RU-8 5-Lead SOT-23-5 (RT-5) OUT A 1 Applications that benefit from the high output current of the OP179/OP279 include driving headphones, displays, transformers and power transistors. The powerful output is combined with a unique input stage that maintains very low distortion with wide common-mode range, even in single supply designs. The OP179/OP279 can be used as a buffer to provide much greater drive capability than can usually be provided by CMOS outputs. CMOS ASICs and DAC often have outputs that can swing to both the positive supply and ground, but cannot drive more than a few milliamps. Bandwidth is typically 5 MHz and the slew rate is 3 V/µs, making these amplifiers well suited for single supply applications that require audio bandwidths when used in high gain configurations. Operation is guaranteed from voltages as low as 4.5 V, up to 12 V. 5 V– V+ 2 4 2IN A +IN A 3 OUT A 1 2IN A 2 8 V+ OP279 +IN A 3 7 OUT B 6 2IN B 5 +IN B V2 4 8-Lead Plastic DIP (N-8) GENERAL DESCRIPTION The OP179 and OP279 are rail-to-rail, high output current, single-supply amplifiers. They are designed for low voltage applications that require either current or capacitive load drive capability. The OP179/OP279 can sink and source currents of ± 60 mA (typical) and are stable with capacitive loads to 10 nF. OP179 OUT A OP279 +V –IN A OUT B +IN A –IN B –V +IN B Very good audio performance can be attained when using the OP179/OP279 in +5 volt systems. THD is below 0.01% with a 600 Ω load, and noise is a respectable 21 nV/√Hz. Supply current is less than 3.5 mA per amplifier. The single OP179 is available in the 5-lead SOT-23-5 package. It is specified over the industrial (–40°C to +85°C) temperature range. The OP279 is available in 8-lead plastic DIP, TSSOP and SO-8 surface mount packages. They are specified over the industrial (–40°C to +85°C) temperature range. REV. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 OP179/OP279–SPECIFICATIONS ELECTRICAL SPECIFICATIONS (@ V = +5.0 V, V S CM = 2.5 V, –40ⴗC ≤ T A ≤ +85ⴗC unless otherwise noted) Parameter␣ Symbol Conditions INPUT CHARACTERISTICS␣ Offset Voltage OP179 OP279 Input Bias Current VOS VOS IB VOUT = 2.5 V VOUT = 2.5 V VOUT = 2.5 V, TA = +25°C VOUT = 2.5 V VOUT = 2.5 V, TA = +25°C VOUT = 2.5 V Input Offset Current IOS Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain Offset Voltage Drift VCM CMRR A VO ∆VOS/∆T OUTPUT CHARACTERISTICS␣ Output Voltage High Output Voltage Low Short Circuit Limit Output Impedance POWER SUPPLY␣ Power Supply Rejection Ratio Supply Current/Amplifier Supply Voltage Range DYNAMIC PERFORMANCE␣ Slew Rate Gain Bandwidth Product Phase Margin Capacitive Load Drive AUDIO PERFORMANCE␣ Total Harmonic Distortion Voltage Noise Density Min VCM = 0 V to 5 V RL = 1 kΩ, 0.3 V ≤ VOUT ≤ 4.7 V 0 56 20 Typ Max Units ±5 ±4 ± 300 ± 700 ± 50 ± 100 5 mV mV nA nA nA nA V dB V/mV µV/°C 66 4 IL = 10 mA Source IL = 10 mA Sink, TA = +25°C IL = 10 mA Sink TA = +25°C f = 1 MHz, AV = 1 VOH VOL ISC ZOUT PSRR ISY VS VS = +4.5 V to +12 V VOUT = 2.5 V SR GBP φm RL = 1 kΩ, 1 nF +4.8 75 100 ± 40 22 70 88 3.5 +12 +4.5 THD en V mV mV mA Ω dB mA V No Oscillation 3 5 60 10 V/µs MHz Degrees nF f = 1 kHz 0.01 22 % nV/√Hz ELECTRICAL SPECIFICATIONS (@ V = ⴞ5.0 V, –40ⴗC ≤ T ≤ +85ⴗC unless otherwise noted) S A Parameter␣ Symbol Conditions INPUT CHARACTERISTICS␣ Offset Voltage OP179 OP279 Input Bias Current VOS VOS IB VOUT = 0 VOUT = 0 TA = +25°C Input Offset Current IOS TA = +25°C Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain Offset Voltage Drift VCM CMRR A VO ∆VOS/∆T VCM = –5 V to +5 V RL = 1 kΩ, –4.7 V ≤ VOUT ≤ 4.7 V OUTPUT CHARACTERISTICS␣ Output Voltage High Output Voltage Low Short Circuit Limit Open-Loop Output Impedance VOH VOL ISC ZOUT IL = 10 mA Source IL = 10 mA Sink TA = +25°C f = 1 MHz, AV = +1 POWER SUPPLY␣ Supply Current/Amplifier ISY VS = ±6 V, V OUT = 0 V DYNAMIC PERFORMANCE␣ Slew Rate Full-Power Bandwidth Gain Bandwidth Product Phase Margin SR BWp GBP φm RL = 1 kΩ, 1 nF 1% Distortion NOISE PERFORMANCE␣ Voltage Noise Voltage Noise Density Current Noise Density e n p-p en in 0.1 Hz to 10 Hz f = 1 kHz Min –5 56 20 Typ Max Units ±5 ±4 ± 300 ± 700 ± 50 ± 100 +5 mV mV nA nA nA nA V dB V/mV µV/°C 66 3 +4.8 –4.85 ± 50 22 3.75 3 5 69 2 22 1 V V mA Ω mA V/µs kHz MHz Degrees µV p-p nV/√Hz pA/√Hz Specifications subject to change without notice. –2– REV. F OP179/OP279 ABSOLUTE MAXIMUM RATINGS Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +16 V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +16 V Differential Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . . ±1 V Output Short-Circuit Duration to GND . . . . . . . . . . Indefinite Storage Temperature Range P, S, RT, RU Package . . . . . . . . . . . . . . . . –65°C to +150°C Operating Temperature Range OP179G/OP279G . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Junction Temperature Range P, S, RT, RU Package . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300°C Package Types JA2 JC Unit 5-Lead SOT-23 (RT) 8-Lead Plastic DIP (P) 8-Lead SOIC (S) 8-Lead TSSOP (RU) 256 103 158 240 81 43 43 43 °C/W °C/W °C/W °C/W NOTES 1 The inputs are clamped with back-to-back diodes. If the differential input voltage exceeds 1 volt, the input current should be limited to 5 mA. 2 θ JA is specified for the worst case conditions, i.e., θJA is specified for device in socket for P-DIP, packages; θJA is specified for device soldered in circuit board for SOIC packages. ORDERING GUIDE Package Temperature Range␣ Package Description Package Option Brand Code OP179GRT OP279GP OP279GS OP279GRU –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C 5-Lead SOT-23 8-Lead Plastic DIP 8-Lead SOIC 8-Lead TSSOP RT-5 N-8 SO-8 RU-8 A2G CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the OP179/OP279 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. F –3– WARNING! ESD SENSITIVE DEVICE OP179/OP279 Typical Performance Graphs 160 90 VS = +5V 140 TA = +258C 620 x OP AMPS, PDIP 120 VS = +5V 40 20 –0.5 0.5 1.5 INPUT OFFSET – mV –ISC 70 +ISC 60 3.0 VS = +5V VCM = +2.5V 50 40 –50 2.5 Figure 1. Input Offset Distribution –25 100 +258C 0 +858C –100 –200 –300 0 25 50 TEMPERATURE – 8C 75 –400 100 0 Figure 2. Short Circuit Current vs. Temperature 1.5 1.0 0 0 1 2 3 4 COMMON-MODE VOLTAGE – Volts 5 –ISC 80 +ISC 70 60 50 –50 0 25 50 75 100 0 2 3 4 1 COMMON-MODE VOLTAGE – Volts 120 RL= 1kV 3 –EDGE 2 VS = +5V RL = 1kV CL = +1nF 1 75 Figure 7. Open-Loop Gain vs. Temperature 100 OPEN-LOOP GAIN – dB SLEW RATE – V/ms 400 +EDGE 0 –50 –25 VS 62.5V TA –408C RL = 2kV Figure 8. Slew Rate vs. Temperature –4– 75 100 270 225 180 80 GAIN 135 60 90 40 PHASE 45 20 0 0 –45 –20 0 25 50 TEMPERATURE – 8C 5 Figure 6. Bandwidth vs. Common-Mode Voltage 100 4.7V 0 25 50 TEMPERATURE – 8C 2 0 –25 4 –25 3 Figure 5. Short Circuit Current vs. Temperature 800 0 –50 4 1 5 200 5 VS = 65V RL= 2kV 600 VS = +5V TA = +258C 6 90 1000 VS = 15V 0.3 VOUT 5 7 TEMPERATURE – 8C Figure 4. Offset Voltage vs. Common-Mode Voltage 2 3 4 1 COMMON-MODE VOLTAGE – Volts Figure 3. Input Bias Current vs. Common-Mode Voltage BANDWIDTH – MHz SHORT CIRCUIT CURRENT – mA 2.0 0.5 OPEN-LOOP GAIN – V/mV –408C 200 100 VS = +5V TA = +258C 2.5 OFFSET VOLTAGE – mV 80 –40 100 PHASE – Degrees 60 INPUT BIAS CURRENT – nA 80 –1.5 300 SHORT CIRCUIT CURRENT – mA UNITS 100 0 –2.5 400 1k 10k 100k FREQUENCY – Hz 1M –90 10M Figure 9. Open-Loop Gain and Phase vs. Frequency REV. F OP179/OP279 5 120 5.5 VS = 65V 5.0 VS = +5V VCM = +2.5V 4.0 –50 –25 75 3 2 VS = 65V RL = 1kV CL = +1nF 0 –50 100 –25 80 120 75 100 –PSRR 60 +PSRR 40 20 90 20 45 0 0 –45 –40 100 1k –90 10M 10k 100k 1M FREQUENCY – Hz Figure 12. Open-Loop Gain and Phase vs. Frequency 180 TA = +258C VS = 62.5V AVCL = +1 RL 1kV 5 4 TA = +258C VS = 62.5V OR 65V 160 140 IMPEDANCE – V 80 MAXIMUM OUTPUT SWING – Volts 100 180 PHASE –20 0 25 50 TEMPERATURE – 8C 225 135 40 6 VS 62.5V TA = +258C GAIN 60 Figure 11. Slew Rate vs. Temperature Figure 10. Supply Current vs. Temperature POWER SUPPLY REJECTION – dB –EDGE 1 0 25 50 TEMPERATURE – 8C OPEN-LOOP GAIN – dB VS = 66V 4.5 100 4 SLEW RATE – V/ms SUPPLY CURRENT – mA +EDGE 6.0 270 VS 62.5V TA –408C RL = 2kV CL = 500pF 3 2 120 AVCL = 10 OR 100 100 80 60 40 1 20 AVCL = 1 0 100 1k 10k 100k FREQUENCY – Hz 1M 0 1k 10M Figure 13. Power Supply Rejection vs. Frequency 100k 1M FREQUENCY – Hz 10M Figure 14. Maximum Output Swing vs. Frequency 10 100 1k 10k 100k FREQUENCY – Hz 1M 10M Figure 15. Closed-Loop Output Impedance vs. Frequency 50 12 10 VS 62.5V TA = +258C RL 1kV AVCL = +100 TA = +258C VS = 65V AVCL = +1 RL 1kV 40 CLOSED-LOOP GAIN – dB MAXIMUM OUTPUT SWING – Volts 0 10k 8 6 4 2 80 TA = +258C AVCL = +1 RL 1kV VS 62.5V VIN = +100mV p-p 70 30 60 AVCL = +10 OVERSHOOT – % 10 20 10 AVCL = +1 0 –10 50 40 30 POSITIVE EDGE AND NEGATIVE EDGE 20 –20 10 0 1k 10k 100k 1M FREQUENCY – Hz 10M Figure 16. Maximum Output Swing vs. Frequency REV. F –30 1k 10k 100k 1M FREQUENCY – Hz 10M 100M Figure 17. Closed-Loop Gain vs. Frequency –5– 0 0 2k 4k 6k 8k LOAD CAPACITANCE – pF 10k Figure 18. Small Signal Overshoot vs. Load Capacitance PHASE – Degrees 6.5 OP179/OP279 Typical Performance Graphs 120 60 80 60 40 20 0 1 10 100 1k FREQUENCY – Hz 10k Figure 19. Voltage Noise Density vs. Frequency VS = +5V TA = +258C FREQUENCY = 1kHz 50 COMMON-MODE REJECTION – dB VS = +5V TA = +258C VOLTAGE NOISE DENSITY – nV/!Hz VOLTAGE NOISE DENSITY – nV/!Hz 100 40 30 20 10 80 60 40 20 0 0 1 2 3 4 COMMON-MODE VOLTAGE – Volts TA = +258C VS 62.5V 100 0 100 5 Figure 20. Voltage Noise Density vs. Common-Mode Voltage 1k 10k 100k FREQUENCY – Hz 1M Figure 21. Common-Mode Rejection vs. Frequency THEORY OF OPERATION VPOS The OP179/OP279 is the latest entry in Analog Devices’ expanding family of single-supply devices, designed for the multimedia and telecom marketplaces. It is a high output current drive, rail-to-rail input /output operational amplifier, powered from a single +5 V supply. It is also intended for other low supply voltage applications where low distortion and high output current drive are needed. To combine the attributes of high output current and low distortion in rail-to-rail input/output operation, novel circuit design techniques are used. R1 6kV R2 3kV Q2 Q3 Q4 R3 2.5kV R4 2.5kV D5 For example, Figure 1 illustrates a simplified equivalent circuit for the OP179/OP279’s input stage. It is comprised of two PNP differential pairs, Q5-Q6 and Q7-Q8, operating in parallel, with diode protection networks. Diode networks D5-D6 and D7-D8 serve to clamp the applied differential input voltage to the OP179/OP279, thereby protecting the input transistors against avalanche damage. The fundamental differences between these two PNP gain stages are that the Q7-Q8 pair are normally OFF and that their inputs are buffered from the operational amplifier inputs by Q1-D1-D2 and Q9-D3-D4. Operation is best understood as a function of the applied common-mode voltage: When the inputs of the OP179/OP279 are biased midway between the supplies, the differential signal path gain is controlled by the resistively loaded (via R7, R8) Q5-Q6. As the input common-mode level is reduced toward the negative supply (VNEG or GND), the input transistor current sources, I1 and I3, are forced into saturation, thereby forcing the Q1-D1-D2 and Q9-D3-D4 networks into cutoff; however, Q5-Q6 remain active, providing input stage gain. On the other hand, when the common-mode input voltage is increased toward the positive supply, Q5-Q6 are driven into cutoff, Q3 is driven into saturation, and Q4 becomes active, providing bias to the Q7-Q8 differential pair. The point at which the Q7-Q8 differential pair becomes active is approximately equal to (VPOS – 1 V). –6– Q1 IN+ Q6 D7 D1 D2 Q7 I1 D6 Q5 D8 R5 4kV – I2 R6 4kV Q9 IN– D3 D4 Q8 VO + R8 2.2kV R7 2.2kV I3 VNEG Figure 22. OP179/OP279 Equivalent Input Circuit The key issue here is the behavior of the input bias currents in this stage. The input bias currents of the OP179/OP279 over the range of common-mode voltages from (VNEG + 1 V) to (VPOS – 1 V) are the arithmetic sum of the base currents in Q1Q5 and Q9-Q6. Outside of this range, the input bias currents are dominated by the base current sum of Q5-Q6 for input signals close to VNEG, and of Q1-Q5 (Q9-Q6) for input signals close to VPOS. As a result of this design approach, the input bias currents in the OP179/OP279 not only exhibit different amplitudes, but also exhibit different polarities. This input bias current behavior is best illustrated in Figure 3. It is, therefore, of paramount importance that the effective source impedances connected to the OP179/OP279’s inputs are balanced for optimum dc and ac performance. REV. F OP179/OP279 In order to achieve rail-to-rail output behavior, the OP179/OP279 design employs a complementary common-emitter (or gm RL) output stage (Q15-Q16), as illustrated in Figure 23. These amplifiers provide output current until they are forced into saturation which occurs at approximately 50 mV from either supply rail. Thus, their saturation voltage is the limit on the maximum output voltage swing in the OP179/OP279. The output stage also exhibits voltage gain, by virtue of the use of common-emitter amplifiers; and, as a result, the voltage gain of the output stage (thus, the open-loop gain of the device) exhibits a strong dependence to the total load resistance at the output of the OP179/OP279 as illustrated in Figure 7. ensure optimum dc and ac performance, it is important to balance source impedance levels. For more information on general overvoltage characteristics of amplifiers refer to the 1993 Seminar Applications Guide, available from the Analog Devices Literature Center. 5 4 INPUT CURRENT – mA 3 VPOS Q3 0 –1 –2 Q13 –4 I3 Q7 1 –3 105V I1 2 –5 –2.0 Q15 Q4 Q1 Q8 VOUT Q2 Some operational amplifiers designed for single supply operation exhibit an output voltage phase reversal when their inputs are driven beyond their useful common-mode range. Typically for single-supply bipolar op amps, the negative supply determines the lower limit of their common-mode range. With these devices, external clamping diodes, with the anode connected to ground and the cathode to the inputs, input signal excursions are prevented from exceeding the device’s negative supply (i.e., GND), preventing a condition that could cause the output voltage to change phase. JFET input amplifiers may also exhibit phase reversal and, if so, a series input resistor is usually required to prevent it. Q9 Q16 I2 Q6 Q10 105V I4 Q14 VNEG Figure 23. OP179/OP279 Equivalent Output Circuit Input Overvoltage Protection As with any semiconductor device, whenever the condition exists for the input to exceed either supply voltage, the device’s input overvoltage characteristic must be considered. When an overvoltage occurs, the amplifier could be damaged, depending on the magnitude of the applied voltage and the magnitude of the fault current. Figure 24 illustrates the input overvoltage characteristic of the OP179/OP279. This graph was generated with the power supplies at ground and a curve tracer connected to the input. As can be seen, when the input voltage exceeds either supply by more than 0.6 V, internal pn-junctions energize, which allows current to flow from the input to the supplies. As illustrated in the simplified equivalent input circuit (Figure 22), the OP179/OP279 does not have any internal current limiting resistors, so fault currents can quickly rise to damaging levels. The OP179/OP279 is free from reasonable input voltage range restrictions provided that input voltages no greater than the supply voltages are applied. Although the device’s output will not change phase, large currents can flow through the input protection diodes, shown in Figure 22. Therefore, the technique recommended in the Input Overvoltage Protection section should be applied in those applications where the likelihood of input voltages exceeding the supply voltages is possible. Capacitive Load Drive The OP179/OP279 has excellent capacitive load driving capabilities. It can drive up to 10 nF directly as the performance graph titled Small Signal Overshoot vs. Load Capacitance (Figure 18) shows. However, even though the device is stable, a capacitive load does not come without a penalty in bandwidth. As shown in Figure 25, the bandwidth is reduced to under 1 MHz for loads greater than 3 nF. A “snubber” network on the output won’t increase the bandwidth, but it does significantly reduce the amount of overshoot for a given capacitive load. A snubber consists of a series R-C network (RS, C S), as shown in Figure 26, connected from the output of the device to ground. This network operates in parallel with the load capacitor, CL, to provide phase lag compensation. The actual value of the resistor and capacitor is best determined empirically. This input current is not inherently damaging to the device as long as it is limited to 5 mA or less. For the OP179/OP279, once the input voltage exceeds the supply by more than 0.6 V, the input current quickly exceeds 5 mA. If this condition continues to exist, an external series resistor should be added. The size of the resistor is calculated by dividing the maximum overvoltage by 5 mA. For example, if the input voltage could reach 100 V, the external resistor should be (100 V/5 mA) = 20 kΩ. This resistance should be placed in series with either or both inputs if they are exposed to an overvoltage. Again, in order to REV. F 2.0 Output Phase Reversal Q12 Q5 0 1.0 INPUT VOLTAGE – V Figure 24. OP179/OP279 Input Overvoltage Characteristic Q11 150V –1.0 –7– OP179/OP279 Table I. Snubber Networks for Large Capacitive Loads 7 VS = 65V RL = 1kV TA = +258C Load Capacitance (CL ) Snubber Network (RS, CS) 4 10 nF 100 nF 1 µF 20 Ω, 1 µF 5 Ω, 10 µF 0 Ω, 10 µF 3 Overload Recovery Time BANDWIDTH – MHz 6 5 Overload, or overdrive, recovery time of an operational amplifier is the time required for the output voltage to recover to its linear region from a saturated condition. This recovery time is important in applications where the amplifier must recover after a large transient event. The circuit in Figure 28 was used to evaluate the OP179/OP279’s overload recovery time. The OP179/OP279 takes approximately 1 µs to recover from positive saturation and approximately 1.2 µs to recover from negative saturation. 2 1 0 0.01 0.100 1 CAPACITIVE LOAD – nF 10 Figure 25. OP179/OP279 Bandwidth vs. Capacitive Load +5V 1/2 OP279 VIN 100mV p-p R2 1kV +5V VOUT RS 20V CS 1mF R3 10kV CL 10nF R1 909V 2V p-p @ 100Hz Figure 26. Snubber Network Compensates for Capacitive Load 1/2 OP279 VOUT RL 499V –5V Figure 28. Overload Recovery Time Test Circuit The first step is to determine the value of the resistor, RS . A good starting value is 100 Ω (typically, the optimum value will be less than 100 Ω). This value is reduced until the small-signal transient response is optimized. Next, CS is determined—10 µF is a good starting point. This value is reduced to the smallest value for acceptable performance (typically, 1 µF). For the case of a 10 nF load capacitor on the OP179/OP279, the optimal snubber network is a 20 Ω in series with 1 µF. The benefit is immediately apparent as seen in the scope photo in Figure 27. The top trace was taken with a 10 nF load and the bottom trace with the 20 Ω, 1 µF snubber network in place. The amount of overshot and ringing is dramatically reduced. Table I illustrates a few sample snubber networks for large load capacitors. Output Transient Current Recovery In many applications, operational amplifiers are used to provide moderate levels of output current to drive the inputs of ADCs, small motors, transmission lines and current sources. It is in these applications that operational amplifiers must recover quickly to step changes in the load current while maintaining steady-state load current levels. Because of its high output current capability and low closed-loop output impedance, the OP179/OP279 is an excellent choice for these types of applications. For example, when sourcing or sinking a 25 mA steadystate load current, the OP179/OP279 exhibits a recovery time of less than 500 ns to 0.1% for a 10 mA (i.e., 25 mA to 35 mA and 35 mA to 25 mA) step change in load current. A Precision Negative Voltage Reference 10nF LOAD ONLY SNUBBER IN CIRCUIT In many data acquisition applications, the need for a precision negative reference is required. In general, any positive voltage reference can be converted into a negative voltage reference through the use of an operational amplifier and a pair of matched resistors in an inverting configuration. The disadvantage to that approach is that the largest single source of error in the circuit is the relative matching of the resistors used. 100 90 10 0% 50mV The circuit illustrated in Figure 29 avoids the need for tightly matched resistors with the use of an active integrator circuit. In this circuit, the output of the voltage reference provides the input drive for the integrator. The integrator, to maintain circuit equilibrium, adjusts its output to establish the proper relationship between the reference’s VOUT and GND. Thus, various negative output voltages can be chosen simply by substituting for the appropriate reference IC (see table). To speed up the 2ms Figure 27. Overshoot and Ringing Is Reduced by Adding a “Snubber” Network in Parallel with the 10 nF Load –8– REV. F OP179/OP279 ON-OFF settling time of the circuit, R2 can be reduced to 50 kΩ or less. Although the integrator’s time constant chosen here is 1 ms, room exists to trade-off circuit bandwidth and noise by increasing R3 and decreasing C2. The SHUTDOWN feature is maintained in the circuit with the simple addition of a PNP transistor and a 10 kΩ resistor. One caveat with this approach should be mentioned: although rail-to-rail output amplifiers work best in the application, these operational amplifiers require a finite amount (mV) of headroom when required to provide any load current. The choice for the circuit’s negative supply should take this issue into account. +5V SHUTDOWN TTL/CMOS R5 10kV 2N3904 VOUT (V) U1 REF192 2.5 REF193 3.0 REF196 3.3 C2 REF194 4.5 1mF REF195 R3 1kV 6 C1 1mF GND 4 R2 100kV R1 10kV Transient performance of the reference/regulator for a 10 mA step change in load current is also quite good and is determined largely by the R5-C5 output network. With values as shown, the transient is about 10 mV peak and settles to within 2 mV in 8 µs, for either polarity. Although room exists for optimizing the transient response, any changes to the R5-C5 network should be verified by experiment to preclude the possibility of excessive ringing with some capacitor types. 2 U1 3 The low dropout performance of this circuit is provided by stage U2, one-half of an OP179/OP279 connected as a follower/buffer for the basic reference voltage produced by U1. The low voltage saturation characteristic of the OP179/OP279 allows up to 30 mA of load current in the illustrated use, as a 5 V to 3.3 V converter with high dc accuracy. In fact, the dc output voltage change for a 30 mA load current delta measures less than 1 mV. This corresponds to an equivalent output impedance of < 0.03 Ω. In this application, the stable 3.3 V from U1 is applied to U2 through a noise filter, R1-C1. U2 replicates the U1 voltage within a few mV, but at a higher current output at VOUT1 , with the ability to both sink and source output current(s)—unlike most IC references. R2 and C2 in the feedback path of U2 provide bias compensation for lowest dc error and additional noise filtering. +5V 1/2 OP279 R4 10V –VREF –10V To scale VOUT2 to another (higher) output level, the optional resistor R3 (shown dotted) is added, causing the new VOUT1 to become: Figure 29. A Negative Precision Voltage Reference That Uses No Precision Resistors Exhibits High Output Current Drive R2 V OUT 1 = V OUT 2 × 1 + R3 A High Output Current, Buffered Reference/Regulator Many applications require stable voltage outputs relatively close in potential to an unregulated input source. This “low dropout” type of reference/regulator is readily implemented with a rail-torail output op amp, and is particularly useful when using a higher current device such as the OP179/OP279. A typical example is the 3.3 V or 4.5 V reference voltage developed from a 5 V system source. Generating these voltages requires a threeterminal reference, such as the REF196 (3.3 V) or the REF194 (4.5 V), both of which feature low power, with sourcing outputs of 30␣ mA or less. Figure 30 shows how such a reference can be outfitted with an OP179/OP279 buffer for higher currents and/ or voltage levels, plus sink and source load capability. +VS +5V As an example, for a VOUT1 = 4.5 V, and VOUT2 = 2.5 V from a REF192, the gain required of U2 is 1.8 times, so R2 and R3 would be chosen for a ratio of 0.8:1, or 18 kΩ:22.5 kΩ. Note that for the lowest VOUT1 dc error, the parallel combination of R2 and R3 should be maintained equal to R1 (as here), and the R2-R3 resistors should be stable, close tolerance metal film types. The circuit can be used as shown as either a 5 V to 3.3 V reference/regulator, or it can be used with ON/OFF control. By driving Pin 3 of U1 with a logic control signal as noted, the output is switched ON/OFF. Note that when ON/OFF control is used, resistor R4 should be used with U1 to speed ON-OFF switching. U2 1/2 OP279 C1 0.1mF VOUT1 = 3.3V @ 30mA R3 (SEE TEXT) 2 6 VC ON/OFF CONTROL INPUT CMOS HI (OR OPEN) = ON LO = OFF VS COMMON U1 3 REF196 VOUT2 = 3.3V 4 R4 3.3kV C4 1mF Figure 31 illustrates a +5 V only transmit/receive telephone line interface for 110 Ω transmission systems. It allows full duplex transmission of signals on a transformer coupled 110 Ω line in a differential manner. Amplifier A1 provides gain that can be adjusted to meet the modem output drive requirements. Both A1 and A2 are configured to apply the largest possible signal on a single supply to the transformer. Because of the OP179/ OP279’s high output current drive and low dropout voltage, the largest signal available on a single +5 V supply is approximately 4.5 V p-p into a 110 Ω transmission system. Amplifier A3 is configured as a difference amplifier to extract the receive signal from the transmission line for amplification by A4. A4’s gain can be adjusted in the same manner as A1’s to meet the modem’s input signal requirements. Standard resistor values permit the use of SIP (Single In-line Package) format resistor arrays. Couple this with the OP179/OP279’s 8-lead SOIC footprint and this circuit offers a compact, cost-sensitive solution. R2 10kV 1% R1 10kV 1% C3 0.1mF Direct Access Arrangement for Telephone Line Interface C2 0.1mF C5 10mF/25V TANTALUM R5 1V VOUT COMMON Figure 30. A High Output Current Reference/Regulator REV. F –9– OP179/OP279 P1 TX GAIN ADJUST TO TELEPHONE LINE 1:1 2kV R3 55V 1 ZO 110V 6.2V C1 R1 0.1mF 10kV 2 A1 R5 10kV 6.2V TRANSMIT TXA 3 R4 55V A Single Supply, Balanced Line Driver +5V DC T1 R6 10kV 6 7 A2 R7 10kV 5 R8 10kV 10mF R9 10kV R10 10kV 3 1 A3 R14 9.09kV R13 10kV 2 R11 10kV The AMP04 is configured for a gain of 100, producing a circuit sensitivity of 80 mV/Ω. Capacitor C2 is used across the AMP04’s Pins 8 and 6 to provide a 16-Hz noise filter. If additional noise filtering is required, an optional capacitor, CX, can be used across the AMP04’s input to provide differential-mode noise rejection. R2 9.09kV P2 RX GAIN ADJUST 2kV 6 R12 A1, A2 = 1/2 OP279 10kV A3, A4 = 1/2 OP279 5 C2 0.1mF 7 A4 RECEIVE RXA Figure 31. A Single Supply Direct Access Arrangement for Modems The circuit in Figure 33 is a unique line driver circuit topology used in professional audio applications and has been modified for automotive audio applications. On a single +12 V supply, the line driver exhibits less than 0.02% distortion into a 600 Ω load across the entire audio band (not shown). For loads greater than 600 Ω, distortion performance improves to where the circuit exhibits less than 0.002%. The design is a transformerless, balanced transmission system where output common-mode rejection of noise is of paramount importance. Like the transformer-based system, either output can be shorted to ground for unbalanced line driver applications without changing the circuit gain of 1. Other circuit gains can be set according to the equation in the diagram. This allows the design to be easily configured for noninverting, inverting, or differential operation. A Single Supply, Remote Strain Gage Signal Conditioner The circuit in Figure 32 illustrates a way by which the OP179/ OP279 can be used in a +12 V single supply, 350 Ω strain gage signal conditioning circuit. In this circuit, the OP179/OP279 serves two functions: (1) By servoing the output of the REF43’s +2.5 V output across R1, it provides a 20 mA drive to the 350 Ω strain gage. In this way, small changes in the strain gage produce large differential output voltages across the AMP04’s inputs. (2) To maximize the circuit’s dynamic range, the other half of the OP179/OP279 is configured as a supply-splitter connected to the AMP04’s REF terminal. Thus, tension or compression in the application can be measured by the circuit. R3 10kV 3 R2 10kV 8 1 F+ 3 +2.5V 6 C1 22mF A1 3 4 CX 100-ft TWISTED PAIR BELDEN TYPE 9502 R1 124V 0.1%, LOW TCR VO1 +12V 7 A1 VIN R1 10kV SET: R6, R12, R13 = R3 R8 100kV 5 R9 100kV RL 600V C2 1mF R11 R12 10kV 10kV 6 5 A2 7 R14 50V C4 47mF VO2 R13 10kV Figure 33. A Single Supply, Balanced Line Driver for Automotive Applications +12V R4 C2 1kV 0.1mF 7 1 3 8 6 AMP04 2 VO 5 80mV/V 4 20mA DRIVE S+ S– 1 SET: R7, R10, R11 = R2 4 R7 10kV 6 A1 C3 47mF R6 10kV 2 0.1mF REF43 2 1 +12V GAIN = R3 R2 2 A2 +12V A1, A2 = 1/2 OP279 +12V R5 50V 2 VO COMMON +12V F– 350V STRAIN GAGE 6 R2 10kV C1 10mF R3 10kV 5 A2 7 +6V A1, A2 = 1/2 OP279 Figure 32. A Single Supply, Remote Strain Gage Signal Conditioner –10– REV. F OP179/OP279 A Single Supply Headphone Amplifier UNITY-GAIN, SALLEN-KEY (VCVS) FILTERS High Pass Configurations Because of its high speed and large output drive, the OP179/ OP279 makes for an excellent headphone driver, as illustrated in Figure 34. Its low supply operation and rail-to-rail inputs and outputs give a maximum signal swing on a single +5 V supply. To ensure maximum signal swing available to drive the headphone, the amplifier inputs are biased to V+/2, which is in this case 2.5 V. The 100 kΩ resistor to the positive supply is equally split into two 50 kΩ with their common point bypassed by 10 µF to prevent power supply noise from contaminating the audio signal. In Figure 35a is the HP form of a unity-gain 2-pole SK filter using an OP179/OP279 section. For this filter and its LP counterpart, the gain in the passband is inherently unity, and the signal phase is noninverting due to the follower hookup. For simplicity and practicality, capacitors C1-C2 are set equal, and resistors R2-R1 are adjusted to a ratio “N,” which provides the filter damping “α” as per the design expressions. A HP design is begun with selection of standard capacitor values for C1 and C2 and a calculation of N; then R1 and R2 are calculated as per the figure expressions. In these examples, α (or 1/Q) is set equal to √2, providing a Butterworth (maximally flat) response characteristic. The filter corner frequency is normalized to 1 kHz, with resistor values shown in both rounded and (exact) form. Various other 2-pole response shapes are also possible with appropriate selection of α. For a given response type (α), frequency can be easily scaled, using proportional R or C values. +V + 5V 50kV 10mF 50kV LEFT INPUT +V + 5V 1/2 OP279 16V 220mF LEFT HEADPHONE 50kV 10mF 100kV C1 0.01mF R1 11kV (11.254kV) OUT IN +V C2 0.01mF +VS 3 8 50kV 50kV RIGHT INPUT 10mF 1/2 OP279 16V R2 22kV (22.508kV) 220mF U1A OP279 1 2 SET C1 = C2 = C ALPHA = 2/(N^0.5) = 1/Q N = 4/(ALPHA)^2 = R2/R1 4 –VS RIGHT HEADPHONE 50kV R = R2 10mF GIVEN: ALPHA, F 100kV R1 = 1/(2*PI*F*C* (N^0.5)) R2 = N*R1 1kHz BW SHOWN 0.1mF Zf (HIGH PASS) Figure 34. A Single Supply, Stereo Headphone Driver a. High Pass R1 11kV (11.254kV) The audio signal is then ac-coupled to each input through a 10 µF capacitor. A large value is needed to ensure that the 20 Hz audio information is not blocked. If the input already has the proper dc bias, the ac coupling and biasing resistors are not required. A 220 µF capacitor is used at the output to couple the amplifier to the headphone. This value is much larger than that used for the input because of the low impedance of the headphones, which can range from 32 Ω to 600 Ω. An additional 16 Ω resistor is used in series with the output capacitor to protect the op amp’s output stage by limiting capacitor discharge current. When driving a 48 Ω load, the circuit exhibits less than 0.02% THD+N at low output drive levels (not shown). The OP179/OP279’s high current output stage can drive this heavy load to 4 V p-p and maintain less than 1% THD+N. REV. F OUT R2 11kV (11.254kV) 5 U1B OP279 7 C2 0.01mF 6 R = R1+R2 GIVEN: ALPHA, F SET R1 = R2 = R ALPHA = 2/(M^0.5) = 1/Q N = 4/(ALPHA)^2 = C2/C1 PICK C1 C1 = M*C1 R = 1/(2*P1*F*C1* (M^0.5)) 1kHz BW SHOWN 0.1mF Zf (LOW PASS) b. Low Pass Active Filters Several active filter topologies are useful with the OP179/OP279. Among these are two popular architectures, the familiar SallenKey (SK) voltage controlled voltage source (VCVS) and the multiple feedback (MFB) topologies. These filter types can be arranged for high pass (HP), low pass (LP), and bandpass (BP) filters. The SK filter type uses the op amp as a fixed gain voltage follower at unity or a higher gain, while the MFB structure uses it as an inverting stage. Discussed here are simplified, 2-pole forms of these filters, highly useful as system building blocks. C1 0.02mF IN Figure 35. 2-Pole Unity-Gain Sallen Key HP/LP Filters Low Pass Configurations In the LP SK arrangement of Figure 35b, R and C elements are interchanged, and the resistors are made equal. Here the C2/C1 ratio “M” is used to set the filter α, as noted. This design is begun with the choice of a standard capacitor value for C1 and a calculation of M, which forces a value of “M × C1” for C2. Then, the value “R” for R1 and R2 is calculated as per the expression. For highest performance, the passive components used for tuning active filters deserve attention. Resistors should be 1%, low TC, metal film types of the RN55 or RN60 style, or similar. –11– OP179/OP279 reactive, and limits overall practicality of this filter. The dire effect of C1 loading can be tempered somewhat by using a small series input resistance of about 100 Ω, but can still be an issue. Capacitors should be 1% or 2% film types preferably, such as polypropylene or polystyrene, or NPO (COG) ceramic for smaller values. Somewhat lesser performance is available with the use polyester capacitors. C1 0.01mF Parasitic Effects in Sallen-Key Implementations In designing these circuits, moderately low (10 kΩ or less) values for R1-R2 can be used to minimize the effects of Johnson noise when critical, with of course practical tradeoffs of capacitor size and expense. DC errors will result for larger values of resistance, unless bias current compensation is used. To add bias compensation in the HP filter of Figure 35a, a feedback compensation resistor with a value equal to R2 is used, shown optionally as Zf. This will minimize bias induced offset, reducing it to the product of the OP179/OP279’s IOS and R2. Similar compensation is applied to the LP filter, using a Zf resistance of R1 + R2. Using dc compensation and relatively low filter values, filter output dc errors using the OP179/OP279 will be dominated by VOS, which is limited to 4 mV or less. A caveat here is that the additional resistors increase noise substantially— for example, an unbypassed 10 kΩ resistor generates ≈ 12 nV/ √Hz of noise. However, the resistance can be ac-bypassed to eliminate noise with a simple shunt capacitor, such as 0.1 µF. Sallen-Key Implementations in Single Supply Applications The hookups shown illustrate a classical dual supply op amp application, which for the OP179/OP279 would use supplies up to ± 5 V. However, these filters can also use the op amp in a single-supply mode, with little if any alteration to the filter itself. To operate single-supply, the OP179/OP279 is powered from +5 V at Pin 8 with Pin 4 grounded. The input dc bias for the op amp must be supplied from a dc source equal to 1/2 supply, or 2.5 V in this case. For the HP section, dc bias is applied to the common end of R2. R2 is simply returned to an ac ground that is a well-bypassed 2:1 divider across the 5 V source. This can be as simple as a pair of 100 kΩ resistors with a 10 µF bypass cap. The output from the stage is then ac coupled, using an appropriate coupling cap from U1A to the next stage. For the LP section dc bias is applied to the input end of R1, in common with the input signal. This dc can be taken from an unbypassed dual 100 kΩ divider across the supply, with the input signal ac coupled to the divider and R1. IN OUT C3 0.01mF R2 33.6kV GIVEN: ALPHA, F AND H (PASSBAND GAIN) ALPHA = 1/Q 6 7 R1 7.5kV PICK A STD C1 VALUE, THEN: C3 = C1, C2 = C1/H R1 = ALPHA / ((2*PI*F*C1)*(2+(1/H))) R2 = (H*(2+(1/H))) / (ALPHA*(2*PI*F*C1)) 5 U1B OP279 R = R2 1kHz BW EXAMPLE SHOWN (NOTE: SEE TEXT ON C1 LOADING CONSIDERATIONS) 0.1mF Zb Figure 36. Two-Pole, High Pass Multiple Feedback Filters In this example, the filter gain is set to unity, the corner frequency is 1 kHz, and the response is a Butterworth type. For applications where dc output offset is critical, bias current compensation can be used for the amplifier. This is provided by network Zb, where R is equal to R2, and the capacitor provides a noise bypass. Low Pass Configurations Figure 37 is a LP MFB 2-pole filter using an OP179/OP279 section. For this filter, the gain in the pass band is user configurable over a wide range, and the pass band signal phase is inverting. Given the design parameters for α, F, and H, a simplified design process is begun by picking a standard value for C2. Then C1 and resistors R1-R3 are selected as per the relationships noted. Optional dc bias current compensation is provided by Zb, where R is equal to the value of R3 plus the parallel equivalent value of R1 and R2. R1 11.3kV R2 11.3kV OUT IN C2 0.01mF R3 5.62kV 5 C1 0.04mF Multiple Feedback Filters GIVEN: ALPHA, F AND H (PASSBAND GAIN) ALPHA = 1/Q 7 6 U1B OP279 MFB filters, like their SK relatives, can be used as building blocks as well. They feature LP and HP operation as well, but can also be used in a bandpass BP mode. They have the property of inverting operation in the pass band, since they are based on an inverting amplifier structure. Another useful asset is their ability to be easily configured for gain. (R1 R2)+R3 PICK A STD C2 VALUE, THEN: C1 = C2 • (4 • (H +1))/ALPHA^2 R1 = ALPHA/(4 • H • PI • F • C2) R2 = H • R1 R3 = ALPHA/(4 • (H + 1) • PI • F • C2) 1kHz BW EXAMPLE SHOWN (NOTE: SEE TEXT ON C1 LOADING CONSIDERATIONS) 0.1mF Zb High Pass Configurations Figure 36 shows an HP MFB 2-pole filter using an OP179/ OP279 section. For this filter, the gain in the passband is user configurable, and the signal phase is inverting. The circuit uses one more tuning component than the SK types. For simplicity, capacitors C1 and C3 are set to equal standard values, and resistors R1-R2 are selected as per the relationships noted. Gain of this filter, H, is set by capacitors C1 and C2, and this factor limits both gain selectability and precision. Also, input capacitance C1 makes the load seen by the driving stage highly C2 0.01mF Figure 37. Two-Pole, Low-Pass Multiple Feedback Filters Gain of this filter, H, is set here by resistors R2 and R1 (as in a standard op amp inverter), and can be just as precise as these resistors allow at low frequencies. Because of this flexible and accurate gain characteristic, plus a low range of component value spread, this filter is perhaps the most practical of all the MFB types. Capacitor ratios are best satisfied by paralleling two or more common types, as in the example, which is a 1 kHz unity gain Butterworth filter. –12– REV. F OP179/OP279 Bandpass Configurations C1 0.01mF The MFB bandpass filter using an OP179/OP279 section is shown in Figure 38. This filter provides reasonably stable medium Q designs for frequencies of up to a few kHz. For best predictability and stability, operation should be restricted to applications where the OP179/OP279 has an open-loop gain in excess of 2Q2 at the filter center frequency. R3 49.9V R1 31.6kV HI +VS C2 0.01mF 500Hz AND UP U1A OP279 3 1 2 R2 31.6kV VIN 4 –VS R1 26.4kV (264kV) C1 0.1mF R5 31.6kV IN R4 49.9V R6 31.6kV LO OUT C2 0.1mF R3 530kV 6 R2 1.4kV (1.33kV) 7 5 U1B OP279 R = R3 0.1mF C3 0.01mF R7 15.8kV GIVEN: Q, F, AND AO (PASSBAND GAIN) ALPHA = 1/Q, H = AO/Q C4 0.02mF DC – 500Hz 6 7 5 PICK A STD C1 VALUE, THEN: C2 = C1 R1 = 1/(H*(2*PI*F*C1)) R2 = 1/(((2*Q) –H)*(2*PI*F*C1)) R3 = Q/(PI*F*C1) U1B OP279 +5V +VS 0.1mF EXAMPLE: 60Hz, Q = 10, AO = 10 (OR 1) AO = 1 FOR '( )' VALUES 100mF/25V TO U1 COM Zb 0.1mF 100mF/25V –5V –VS Figure 38. Two-Pole, Bandpass Multiple Feedback Filters Given the bandpass design parameters for Q, F, and pass band gain AO, the design process is begun by picking a standard value for C1. Then C2 and resistors R1-R3 are selected as per the relationships noted. This filter is subject to a wide range of component values by nature. Practical designs should attempt to restrict resistances to a 1 kΩ to 1 MΩ range, with capacitor values of 1 µF or less. When needed, dc bias current compensation is provided by Zb, where R is equal to R3. Two-Way Loudspeaker Crossover Networks Active filters are useful in loudspeaker crossover networks for reasons of small size, relative freedom from parasitic effects, and the ease of controlling low/high channel drive, plus the controlled driver damping provided by a dedicated amplifier. Both Sallen-Key (SK) VCVS and multiple-feedback (MFB) filter architectures are useful in implementing active crossover networks (see Reference 4), and the circuit shown in Figure 39 is a two-way active crossover which combines the advantages of both filter topologies. This active crossover exhibits less than 0.01% THD+N at output levels of 1 V rms using general purpose unity gain HP/LP stages. In this two-way example, the LO signal is a dc-500 Hz LP woofer output, and the HI signal is the HP (> 500 Hz) tweeter output. U1B forms a MFB LP section at 500 Hz, while U1A provides a SK HP section, covering frequencies ≥ 500 Hz. Figure 39. Two-Way Active Crossover Networks In the filter sections, component values have been selected for good balance between reasonable physical/electrical size, and lowest noise and distortion. DC offset errors can be minimized by using dc compensation in the feedback and bias paths, ac bypassed with capacitors for low noise. Also, since the network input is reactive, it should driven from a directly coupled low impedance source at VIN. Figure 40 shows this filter architecture adapted for single supply operation from a 5 V dc source, along the lines discussed previously. This crossover network is a Linkwitz-Riley type (see Reference 5), with a damping factor or α of 2 (also referred to as “Butterworth squared”). A hallmark of the Linkwitz-Riley type of filter is the fact that the summed magnitude response is flat across the pass band. A necessary condition for this to happen is the relative signal polarity of the HI output must be inverted with respect to the LOW outputs. If only SK filter sections were used, this requires that the connections to one speaker be reversed on installation. Alternately, with one inverting stage used in the LO channel, this accomplishes the same effect. In the circuit as shown, stage U1B is the MFB LP filter which provides the necessary polarity inversion. Like the SK sections, it is configured for unity gain and an α of 2. The cutoff frequency is 500 Hz, which complements the SK HP section of U4. REV. F C1 0.01mF R3 49.9V 10mF + R1 31.6kV +VS C2 0.01mF VIN RIN 100kV 3 500Hz AND UP HI 100kV U1A OP279 1 2 R2 31.6kV 4 CIN 10mF R5 31.6kV +VS 100kV R4 49.9V 10mF + R6 31.6kV C3 0.01mF R7 15.8kV C4 0.02mF DC – 500Hz LO 100kV 6 7 5 100kV +5V +VS 0.1mF TO U1 U1B OP279 10mF 100mF/25V COM Figure 40. A Single Supply, Two-Way Active Crossover –13– OP179/OP279 The crossover example frequency of 500 Hz can be shifted lower or higher by frequency scaling of either resistors or capacitors. In configuring the circuit for other frequencies, complementary LP/HP action must be maintained between sections, and component values within the sections must be in the same ratio. Table II provides a design aid to adaptation, with suggested standard component values for other frequencies. Table II. RC Component Selection for Various Crossover Frequencies Crossover Frequency (Hz) R1/C1 (U1A)* R5/C3 (U1B)** 100 200 319 500 1k 2k 5k 10 k 160 kΩ/0.01 µF 80.6 kΩ/0.01 µF 49.9 kΩ/0.01 µF 31.6 kΩ/0.01 µF 16 kΩ/0.01 µF 8.06 kΩ/0.01 µF 3.16 kΩ/0.01 µF 1.6 kΩ/0.01 µF References on Active Filters and Active Crossover Networks 1. Sallen, R.P.; Key, E.L., “A Practical Method of Designing RC Active Filters,” IRE Transactions on Circuit Theory, vol. CT-2, March 1955. 2. Huelsman, L.P.; Allen, P.E., Introduction to the Theory and Design of Active Filters, McGraw-Hill, 1980. 3. Zumbahlen, H., “Chapter 6: Passive and Active Analog Filtering,” within 1992 Analog Devices Amplifier Applications Guide. 4. Zumbahlen, H., “Speaker Crossovers,” within Chapter 8 of 1993 Analog Devices System Applications Guide. 5. Linkwitz, S., “Active Crossover Networks for Noncoincident Drivers,” JAES, Vol. 24, #1, Jan/Feb 1976. Table notes (applicable for α = 2). * For SK stage U1A: R1 = R2, and C1 = C2, etc. ** For MFB stage U1B: R6 = R5, R7 = R5/2, and C4 = 2C3. –14– REV. F OP179/OP279 OP179/OP279 Spice Macro Model * OP179/OP279 SPICE Macro-model * Rev. A, 5/94 ARG / ADI * * Copyright 1994 by Analog Devices * * Refer to “README.DOC” file for License Statement. Use of * this model indicates your acceptance of the terms and pro* visions in the License Statement. * * Node assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT OP179/OP279 3 2 99 50 45 * * INPUT STAGE AND POLE AT 6 MHz * I1 1 50 60.2E-6 Q1 5 2 7 QN Q2 6 4 8 QN D1 4 2 DX D2 2 4 DX R1 1 7 1.628E3 R2 1 8 1.628E3 R3 5 99 2.487E3 R4 6 99 2.487E3 C1 5 6 5.333E-12 EOS 4 3 POLY(1) (16,39) 0.25E-3 50.118 IOS 2 3 5E-9 GB1 2 98 (24,98) 100E-9 GB2 4 98 (24,98) 100E-9 CIN 2 3 1E-12 * * GAIN STAGE AND DOMINANT POLE AT 16 Hz * EREF 98 0 (39,0) 1 G1 98 9 (5,6) 402.124E-6 R7 9 98 497.359E6 C2 9 98 20E-12 V1 99 10 0.58 V2 11 50 0.47 D5 9 10 DX D6 11 9 DX * * COMMON-MODE STAGE WITH ZERO AT 10 kHz * ECM 15 98 POLY(2) (3,39) (2,39) 0 0.5 0.5 R9 15 16 1E6 REV. F R10 16 98 10 C3 15 16 15.915E-12 * * ZERO AT 1.5 MHz * E1 14 98 (9,39) 1E6 R5 14 18 1E6 R6 18 98 1 C4 14 18 106.103E-15 * * BIAS CURRENT-VS-COMMON-MODE VOLTAGE * EP 97 0 (99,0) 1 EN 51 0 (50,0) 1 V3 20 21 1.6 V4 22 23 2.8 R12 97 20 530 R13 23 51 1E3 D13 15 21 DX D14 22 15 DX FIB 98 24 POLY(2) V3 V4 0 –1 1 RIB 24 98 10E3 E3 97 25 POLY(1) (99,39) –1.63 1 E4 26 51 POLY(1) (39,50) –2.73 1 D15 24 25 DX D16 26 24 DX * * POLE AT 6 MHz * G6 98 40 (18,39) 1E 6 R20 40 98 1E6 C10 40 98 26.526E-15 * * OUTPUT STAGE * RS1 99 39 6.0345E3 RS2 39 50 6.0345E3 RO1 99 45 40 RO2 45 50 40 G7 45 99 (99,40) 25E-3 G8 50 45 (40,50) 25E-3 G9 98 60 (45,40) 25E-3 D9 60 61 DX D10 62 60 DX V7 61 98 DC 0 V8 98 62 DC 0 FSY 99 50 POLY(2) V7 V8 1.711E-3 1 1 D11 41 45 DZ D12 45 42 DZ V5 40 41 1.54 V6 42 40 1.54 .MODEL DX D() .MODEL DZ D(IS=1E-6) .MODEL QN NPN(BF=300) .ENDS –15– OP179/OP279 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead Narrow-Body SO (SO-8) 0.1968 (5.00) 0.1890 (4.80) 0.430 (10.92) 0.348 (8.84) 8 5 1 4 0.060 (1.52) 0.015 (0.38) PIN 1 0.210 (5.33) MAX 8 0.280 (7.11) 0.240 (6.10) 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.100 0.070 (1.77) 0.014 (0.356) (2.54) 0.045 (1.15) BSC 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.0688 (1.75) 0.0532 (1.35) 0.1220 (3.100) 0.1063 (2.700) 5 0.0709 (1.800) 0.0590 (1.500) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) 8° 0° 0.0500 (1.27) 0.0160 (0.41) 5-Lead SOT-23 (RT-5) 0.122 (3.10) 0.114 (2.90) 1 0.0196 (0.50) x 45° 0.0099 (0.25) 0.0500 0.0192 (0.49) SEATING (1.27) 0.0098 (0.25) PLANE BSC 0.0138 (0.35) 0.0075 (0.19) 8-Lead TSSOP (RU-8) 8 0.2440 (6.20) 0.2284 (5.80) 4 PIN 1 0.0098 (0.25) 0.0040 (0.10) 0.195 (4.95) 0.115 (2.93) 0.130 (3.30) MIN SEATING PLANE 5 0.1574 (4.00) 0.1497 (3.80) 1 C3497a–0–10/99 8-Lead Plastic DIP (N-8) 3 2 1 4 5 PIN 1 0.1181 (3.000) 0.0984 (2.500) 0.0374 (0.950) REF 4 0.0748 (1.900) REF PIN 1 0.0118 (0.30) SEATING PLANE 0.0075 (0.19) 0.0433 (1.10) MAX 0.0079 (0.20) 0.0035 (0.090) 0.0512 (1.300) 0.0354 (0.900) 88 08 0.0590 (0.150) 0.0000 (0.000) 0.028 (0.70) 0.020 (0.50) 0.0079 (0.200) 0.0035 (0.090) 0.0571 (1.450) 0.0354 (0.900) 0.0197 (0.500) 0.0118 (0.300) SEATING PLANE 108 08 0.0236 (0.600) 0.0039 (0.100) NOTE: PACKAGE OUTLINE INCLUSIVE AS SOLDER PLATING. PRINTED IN U.S.A. 0.0256 (0.65) 0.006 (0.15) BSC 0.002 (0.05) –16– REV. F