50 dB GSM PA Controller AD8315 Its high sensitivity allows control at low signal levels, thus reducing the amount of power that needs to be coupled to the detector. FEATURES Complete RF detector/controller function >50 dB range at 0.9 GHz (−49 dBm to +2 dBm, re 50 Ω) Accurate scaling from 0.1 GHz to 2.5 GHz Temperature-stable linear-in-dB response Log slope of 23 mV/dB, intercept at −60 dBm at 0.9 GHz True integration function in control loop Low power: 20 mW at 2.7 V, 38 mW at 5 V Power-down to 10.8 μW For convenience, the signal is internally ac-coupled. This high-pass coupling, with a corner at approximately 0.016 GHz, determines the lowest operating frequency. Therefore, the source can be dc grounded. The AD8315 provides a voltage output, VAPC, that has the voltage range and current drive to directly connect to most handset power amplifiers’ gain control pin. VAPC can swing from 250 mV above ground to within 200 mV below the supply voltage. Load currents of up to 6 mA can be supported. APPLICATIONS Single, dual, and triple band mobile handset (GSM, DCS, EDGE) Transmitter power control The setpoint control input is applied to the VSET pin and has an operating range of 0.25 V to 1.4 V. The associated circuit determines the slope and intercept of the linear-in-dB measurement system; these are nominally 23 mV/dB and −60 dBm for a 50 Ω termination (−73 dBV) at 0.9 GHz. Further simplifying the application of the AD8315, the input resistance of the setpoint interface is over 100 MΩ, and the bias current is typically 0.5 μA. GENERAL DESCRIPTION The AD8315 is a complete low cost subsystem for the precise control of RF power amplifiers operating in the frequency range 0.1 GHz to 2.5 GHz and over a typical dynamic range of 50 dB. It is intended for use in cellular handsets and other batteryoperated wireless devices. The log amp technique provides a much wider measurement range and better accuracy than controllers using diode detectors. In particular, its temperature stability is excellent over a specified range of −30°C to +85°C. The AD8315 is available in MSOP and LFCSP packages and consumes 8.5 mA from a 2.7 V to 5.5 V supply. When powered down, the sleep current is 4 μA. FUNCTIONAL BLOCK DIAGRAM VPOS LOW NOISE BAND GAP REFERENCE LOW NOISE GAIN BIAS ENBL DET DET DET DET OUTPUT ENABLE DELAY DET HI-Z ×1.35 VAPC LOW NOISE (25nV/√Hz) RAIL-TO-RAIL BUFFER RFIN 10dB 10dB FLTR 10dB V-I OFFSET COMP’N INTERCEPT POSITIONING COMM VSET 23mV/dB 250mV TO 1.4V = 50dB 01520-001 10dB Figure 1. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. AD8315 TABLE OF CONTENTS Features .............................................................................................. 1 Practical Loop ............................................................................. 15 Applications....................................................................................... 1 A Note About Power Equivalency ........................................... 16 General Description ......................................................................... 1 Basic Connections...................................................................... 16 Functional Block Diagram .............................................................. 1 Range on VSET and RFIN ........................................................ 17 Revision History ............................................................................... 2 Transient Response .................................................................... 17 Specifications..................................................................................... 3 Mobile Handset Power Control Example ............................... 18 Absolute Maximum Ratings............................................................ 5 Enable and Power-On................................................................ 19 ESD Caution.................................................................................. 5 Input Coupling Options ............................................................ 19 Pin Configuration and Function Descriptions............................. 6 Using the Chip Scale Package ................................................... 20 Typical Performance Characteristics ............................................. 7 Evaluation Board ........................................................................ 20 Theory of Operation ...................................................................... 12 Outline Dimensions ....................................................................... 22 Basic Theory................................................................................ 12 Ordering Guide .......................................................................... 23 Controller-Mode Log Amps ..................................................... 13 Control Loop Dynamics............................................................ 13 REVISION HISTORY 6/06—Rev. B to Rev. C Updated Format..................................................................Universal Changes to Ordering Guide .......................................................... 23 1/03—Rev. 0 to Rev. B Edits to Product Description Section ............................................ 1 Edit to Functional Block Diagram ................................................. 1 Edits to Specifications ...................................................................... 2 Edits to Absolute Maximum Ratings ............................................. 3 Ordering Guide Updated................................................................. 3 TPC 9 Replaced with New Figure .................................................. 5 Edits to TPC 27 ................................................................................. 8 Edit to Figure 1.................................................................................. 9 Edit to Figure 3................................................................................ 10 Edit to Equation 9........................................................................... 10 Edit to Equation 10......................................................................... 10 Edit to Equation 11......................................................................... 10 Edits to Example section ............................................................... 10 Edit to Basic Connections Section ............................................... 12 Edits to Input Coupling Options Section.................................... 14 Table III Becomes Table II............................................................. 15 Table II Recommended Components Deleted ........................... 15 Using the Chip-Scale Package Section Added............................ 15 Edits to Evaluation Board Section................................................ 15 Figure 12 Title Edited..................................................................... 16 Figure 13 Title Edited..................................................................... 16 8-Lead Chip Scale Package (CP-8) Added .................................. 17 Updated Outline Dimensions....................................................... 17 10/99—Revision 0: Initial Version Rev. C | Page 2 of 24 AD8315 SPECIFICATIONS VS = 2.7 V, T = 25°C, 52.3 Ω termination on RFIN, unless otherwise noted. Table 1. Parameter OVERALL FUNCTION Frequency Range 1 Input Voltage Range Equivalent dBm Range Logarithmic Slope 2 Logarithmic Intercept2 Equivalent dBm Level RF INPUT INTERFACE Input Resistance 3 Input Capacitance3 OUTPUT Minimum Output Voltage Maximum Output Voltage vs. Temperature 4 General Limit Output Current Drive Output Buffer Noise Output Noise Small Signal Bandwidth Slew Rate Response Time SETPOINT INTERFACE Nominal Input Range Logarithmic Scale Factor Input Resistance Slew Rate ENABLE INTERFACE Logic Level to Enable Power Input Current when Enable High Logic Level to Disable Power Enable Time Disable Time Power-On/Enable Time Conditions Min To meet all specifications ±1 dB log conformance, 0.1 GHz 0.1 −57 −44 21.5 −79 −66 0.1 GH 0.1 GHz Pin RFIN 0.1 GHz 0.1 GHz Pin VAPC VSET ≤ 200 mV, ENBL high ENBL low RL ≥ 800 Ω 85°C, VPOS = 3 V, IOUT = 6 mA 2.7 V ≤ VPOS ≤ 5.5 V, RL = ∞ Source/Sink RF input = 2 GHz, 0 dBm, fNOISE = 100 kHz, CFLT = 220 pF 0.2 V to 2.6 V swing 10% to 90%, 1.2 V step (VSET), open loop 5 FLTR = open, see Figure 26 Pin VSET Corresponding to central 50 dB Typ Max Unit 24 −70 −57 2.5 −11 +2 25.5 −64 −51 GHz dBV dBm mV/dB dBV dBm 2.8 0.9 0.25 0.27 0.02 2.45 2.54 kΩ pF 0.3 2.6 VPOS − 0.1 5/200 25 130 30 13 150 0.25 V V V V V mA/μA nV√Hz nV/√Hz MHz V/μs ns 1.4 V dB/V kΩ V/μs VPOS V μA 4 0.8 5 V μs 8 9 μs 2 3 μs 100 200 ns 43.5 100 16 Pin ENBL 1.8 20 Time from ENBL high to VAPC within 1% of final value, VSET ≤ 200 mV, refer to Figure 23 Time from ENBL low to VAPC within 1% of final value, VSET ≤ 200 mV, refer to Figure 23 Time from VPOS/ENBL high to VAPC within 1% of final value, VSET ≤ 200 mV, refer to Figure 28 Time from VPOS/ENBL low to VAPC within 1% of final value, VSET ≤ 200 mV, refer to Figure 28 Rev. C | Page 3 of 24 AD8315 Parameter POWER INTERFACE Supply Voltage Quiescent Current Over Temperature Disable Current 6 Over Temperature Conditions Pin VPOS Min Typ 2.7 ENBL high −30°C ≤ TA ≤ +85°C ENBL low −30°C ≤ TA ≤ +85°C 8.5 4 Max Unit 5.5 10.7 12.9 10 13 V mA mA μA μA 1 Operation down to 0.02 GHz is possible. Mean and standard deviation specifications are available in Table 2 See Figure 11 for plot of input impedance vs. frequency. 4 This parameter is guaranteed but not tested in production. Limit is −3 sigma from the mean. 5 Response time in a closed-loop system depends on the filter capacitor (CFLT) used and the response of the variable gain element. 6 This parameter is guaranteed but not tested in production. Maximum specified limit on this parameter is the 6 sigma value. 2 3 Table 2. Typical Specifications at Selected Frequencies at 25°C (Mean and Sigma) Frequency (GHz) 0.1 0.9 1.9 2.5 Slope (mV/dB) Mean Sigma 23.8 0.3 23.2 0.4 22.2 0.3 22.3 0.4 Intercept (dBV) Mean Sigma −70.1 1.8 −72.6 1.8 −73.8 1.6 −75.6 1.5 Rev. C | Page 4 of 24 ±1 dB Dynamic Range Low Point (dBV) High Point (dBV) Mean Sigma Mean Sigma −57.7 1.3 −10.6 0.8 −61.0 1.3 −11.2 0.8 −62.9 0.9 −18.5 1.7 −64.0 1.1 −20.0 1.7 AD8315 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Supply Voltage VPOS Temporary Overvoltage VPOS (100 cycles, 2 sec duration, ENBL Low) VAPC, VSET, ENBL RFIN Equivalent Voltage Internal Power Dissipation θJA (MSOP) θJA (LFCSP, Paddle Soldered) θJA (LFCSP, Paddle Not Soldered) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering 60 sec) MSOP LFCSP Rating 5.5 V 6.3 V 0 V, VPOS 17 dBm 1.6 V rms 60 mW 200°C/W 80°C/W 200°C/W 125°C −40°C to +85°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 300°C 240°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. C | Page 5 of 24 AD8315 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RFIN 1 VSET 3 FLTR 4 8 VPOS AD8315 7 VAPC TOP VIEW 6 NC (Not to Scale) 5 COMM NC = NO CONNECT 01520-002 ENBL 2 Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic RFIN ENBL VSET FLTR COMM NC VAPC VPOS Description RF Input. Connect to VPOS for Normal Operation Connect Pin to Ground for Disable Mode. Setpoint Input. Nominal input range 0.25 V to 1.4 V. Integrator Capacitor. Connect between FLTR and COMM. Device Common (Ground). No Connection. Output. Control voltage for gain control element. Positive Supply Voltage: 2.7 V to 5.5 V. Rev. C | Page 6 of 24 AD8315 10 23 4 0 13 3 2.5GHz –20 –7 0.1GHz –17 –27 –40 2.5GHz –37 –47 –60 1.2 1.4 –4 0.2 0.4 0.6 0.8 1.0 VSET (V) 1.2 1.4 1.6 Figure 6. Log Conformance vs. VSET Figure 3. Input Amplitude vs. VSET 10 4 10 4 3 0 3 2 (+3dBm) –10 –30°C 0 +25°C +85°C –20 +85°C –30 1 0 +25°C –40 –1 –50 –2 RF INPUT AMPLITUDE (dBV) –30°C ERROR (dB) RF INPUT AMPLITUDE (dBV) (+3dBm) –10 2 +85°C –20 0 +25°C –40 0.3 0.5 0.7 0.9 VSET (V) 1.1 (–47dBm) –60 –4 1.5 1.3 01520-004 –70 0.1 –2 +85°C 0 –30°C +25°C –40 2 (+3dBm) –10 ERROR AT +85°C AND –30°C BASED ON DEVIATION FROM SLOPE AND INTERCEPT AT +25°C 0.3 0.5 0.7 0.9 VSET (V) 1.1 1.3 2 –30°C –20 +85°C 1 0 –30 +25°C –40 –1 –2 –50 +25°C (–47dBm) –60 –3 –30°C +85°C –4 1.5 01520-005 –70 0.1 3 –2 (–47dBm) –60 –4 1.5 0 –1 –50 1.3 3 0 +25°C 1.1 4 1 –30 0.7 0.9 VSET (V) –3 10 –30°C –20 –70 0.1 RF INPUT AMPLITUDE (dBV) +85°C –30°C 0.3 0.5 ERROR AT +85°C AND –30°C BASED ON DEVIATION FROM SLOPE AND INTERCEPT AT +25°C 4 ERROR (dB) RF INPUT AMPLITUDE (dBV) (+3dBm) –10 +85°C Figure 7. Input Amplitude and Log Conformance vs. VSET at 1.9 GHz Figure 4. Input Amplitude and Log Conformance vs. VSET at 0.1 GHz 10 –1 –50 –3 ERROR AT +85°C AND –30°C BASED ON DEVIATION FROM SLOPE AND INTERCEPT AT +25°C 1 –30 +25°C (–47dBm) –60 –30°C 01520-007 0.8 1.0 VSET (V) –1 ERROR (dB) 0.6 01520-003 –67 0.4 0 –3 –57 –80 0.2 1 –2 1.9GHz –70 0.9GHz Figure 5. Input Amplitude and Log Conformance vs. VSET at 0.9 GHz Rev. C | Page 7 of 24 ERROR (dB) 0.9GHz –50 1.9GHz 0.1GHz –70 0.1 0.3 0.5 ERROR AT +85°C AND –30°C BASED ON DEVIATION FROM SLOPE AND INTERCEPT AT +25°C 0.7 0.9 VSET (V) 1.1 1.3 –3 –4 1.5 Figure 8. Input Amplitude and Log Conformance vs. VSET at 2.5 GHz 01520-008 –30 2 01520-006 –10 ERROR (dB) 3 RF INPUT AMPLITUDE (dBm) RF INPUT AMPLITUDE (dBV) TYPICAL PERFORMANCE CHARACTERISTICS AD8315 4 3 2 2 1 1 ERROR (dB) 3 0 –1 +85°C –2 –4 –80 –70 –60 –50 –40 –30 –20 RF INPUT AMPLITUDE (dBV) (–47dBm) –10 0 (+3dBm) –10 0 (+3dBm) 3 2 1 1 –1 +85°C –3 –50 –40 –30 –20 –10 –60 RF INPUT AMPLITUDE (dBV) (–47dBm) (+3dBm) 0 2700 –200 2400 –400 FREQUENCY MSOP CHIP SCALE (LFCSP) R – jXΩ R – jXΩ (GHz) –600 2900 – j1900 2700 – j1500 0.1 700 – j240 730 – j220 0.9 –800 130 – j80 460 – j130 1.9 170 – j70 440 – j110 2.5 –1000 X (LFCSP) 1500 1200 R X –1400 X (MSOP) R (LFCSP) 600 300 1.0 1.5 FREQUENCY (GHz) 0 (+3dBm) 6 4 DECREASING VENBL INCREASING VENBL 2 –1600 –1800 R (MSOP) 0.5 –1200 –10 8 2.0 –2000 2.5 01520-011 1800 –50 –40 –30 –20 RF INPUT AMPLITUDE (dBV) (–47dBm) –60 10 SUPPLY CURRENT (mA) 0 –70 +85°C Figure 13. Distribution of Error at Temperature After Ambient Normalization vs. Input Amplitude, 3 Sigma to Either Side of Mean, 2.5 GHz REACTANCE (Ω) 3000 ERROR AT +85°C AND –30°C BASED ON DEVIATION FROM SLOPE AND INTERCEPT AT +25°C –4 –80 Figure 10. Distribution of Error at Temperature After Ambient Normalization vs. Input Amplitude, 3 Sigma to Either Side of Mean, 0.9 GHz 2100 –30°C Figure 11. Input Impedance 0 1.3 1.4 1.5 VENBL (V) 1.6 Figure 14. Supply Current vs. VENBL Rev. C | Page 8 of 24 1.7 01520-014 –70 –1 –2 ERROR AT +85°C AND –30°C BASED ON DEVIATION FROM SLOPE AND INTERCEPT AT +25°C –4 –80 0 01520-013 ERROR (dB) 2 01520-010 ERROR (dB) –60 –50 –40 –30 –20 RF INPUT AMPLITUDE (dBV) (–47dBm) –30°C –2 RESISTANCE (Ω) –70 Figure 12. Distribution of Error at Temperature After Ambient Normalization vs. Input Amplitude, 3 Sigma to Either Side of Mean, 1.9 GHz 0 0 ERROR AT +85°C AND –30°C BASED ON DEVIATION FROM SLOPE AND INTERCEPT AT +25°C 4 3 –3 –30°C –4 –80 4 0 –1 –3 Figure 9. Distribution of Error at Temperature After Ambient Normalization vs. Input Amplitude, 3 Sigma to Either Side of Mean, 0.1 GHz 900 0 –2 ERROR AT +85°C AND –30°C BASED ON DEVIATION FROM SLOPE AND INTERCEPT AT +25°C –3 +85°C 01520-012 –30°C 01520-009 ERROR (dB) 4 AD8315 25 –66 –68 24 +85°C INTERCEPT (dBV) SLOPE (mV/dB) –70 +85°C 23 –30°C 22 +25°C –72 +25°C –74 –30°C –76 21 0.5 0 1.0 1.5 FREQUENCY (GHz) 2.0 2.5 –80 01520-015 20 0.5 1.0 1.5 FREQUENCY (GHz) 2.0 2.5 Figure 18. Intercept vs. Frequency; −30°C, +25°C, and +85°C Figure 15. Slope vs. Frequency; −30°C, +25°C, and +85°C 24 0 01520-018 –78 –68 0.1GHz 0.1GHz –70 1.9GHz 22 2.5GHz 3.5 4.0 VS (V) 4.5 –74 5.0 5.5 –80 2.5 1k 10k 100k FREQUENCY (Hz) 1M 3.0 10M NOISE SPECTRAL DENSITY (nV/√Hz) 10000 PHASE (Degrees) CFLT = 220pF 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 01520-017 AMPLITUDE (dB) CFLT = 0pF 100 2.5GHz 3.5 4.0 VS (V) 4.5 5.0 5.5 Figure 19. Intercept vs. Supply Voltage Figure 16. Slope vs. Supply Voltage 45 40 35 30 25 20 15 10 5 0 –5 –10 –15 –20 –25 –30 –35 –40 10 1.9GHz –76 CFLT = 220pF, RF INPUT = 2GHz RF INPUT –51dBV –48dBV –33dBV –43dBV 1000 –23dBV –13dBV 100 –53dBV AND –63dBV 10 100 1k 10k 100k FREQUENCY (Hz) 1M Figure 20. VAPC Noise Spectral Density Figure 17. AC Response from VSET to VAPC Rev. C | Page 9 of 24 10M 01520-020 3.0 0.9GHz –78 01520-016 21 2.5 –72 01520-019 23 INTERCEPT (dBV) SLOPE (mV/dB) 0.9GHz AD8315 2.8 3.5 3.3 2mA 2.9 VAPC (V) VAPC (V) 2.7 0mA 3.1 4mA 2.6 6mA 2.7 2.5 2.5 2.9 3.0 3.1 3.2 SUPPLY VOLTAGE (V) 3.3 3.4 3.5 2.4 2.7 Figure 21. Maximum VAPC Voltage vs. Supply Voltage by Load Current 2.9 2.8 SUPPLY VOLTAGE (V) 01520-024 2.8 01520-021 2.3 2.7 SHADING INDICATES ±3 SIGMA 3.0 Figure 24. Maximum VAPC Voltage vs. Supply Voltage with 4 mA Load Current AVERAGE = 16 SAMPLES AVERAGE = 16 SAMPLES VAPC 200mV PER VERTICAL DIVISION 1V PER VERTICAL DIVISION VAPC GND GND 2µs PER HORIZONTAL DIVISION GND PULSED RF 0.1GHz, –13dBV RF INPUT 100ns PER HORIZONTAL DIVISION VENBL 01520-022 GND Figure 22. ENBL Response Time TIMEBASE Figure 25. VAPC Response Time, Full-Scale Amplitude Change, Open-Loop R AND S SMT03 10MHz REF OUTPUT SIGNAL GENERATOR PULSE PULSE MODE IN MODULATION MODE RF OUT TRIG STANFORD DS345 OUT PULSE GENERATOR PULSE OUT RF OUT AD8315 52.3Ω 2 RFIN ENBL TEK P6205 FET PROBE VAPC 7 3 VSET NC 6 4 FLTR COMM 5 PULSE OUT 2.7V AD8315 TEK TDS694C SCOPE 220pF NC = NO CONNECT TRIG OUT 0.1µF TRIG VPOS 8 TEK P6205 FET PROBE PICOSECOND PULSE LABS PULSE GENERATOR –3dB 52.3Ω 01520-023 1 OUT RF SPLITTER –3dB 2.7V 0.1µF EXT TRIG Figure 23. Test Setup for ENBL Response Time 1 RFIN VPOS 8 2.7V 2 ENBL VAPC 7 0.3V 3 VSET NC 6 NC 4 FLTR COMM 5 TRIG TEK P6205 FET PROBE TEK TDS694C SCOPE NC = NO CONNECT Figure 26. Test Setup for VAPC Response Time Rev. C | Page 10 of 24 01520-026 10MHz REF R AND S OUTPUT SMT03 SIGNAL GENERATOR 01520-025 1V PER VERTICAL DIVISION AD8315 AVERAGE = 16 SAMPLES 500mV PER VERTICAL DIVISION VAPC 200mV PER VERTICAL DIVISION VAPC GND GND VS AND VENBL 1V PER VERTICAL DIVISION 2µs PER HORIZONTAL DIVISION 1V PER VERTICAL DIVISION VS AVERAGE = 16 SAMPLES Figure 29. Power-On and Power-Off Response with VSET and ENBL Grounded EXT TRIG STANFORD DS345 PULSE GENERATOR 10MHz REF R AND S OUTPUT SMT03 SIGNAL GENERATOR TRIG OUT PULSE OUT RF OUT AD811 AD811 49.9Ω 2 RFIN ENBL VPOS 8 VAPC 7 3 VSET NC 6 4 FLTR COMM 5 220pF NC = NO CONNECT TRIG 52.3Ω TEK P6205 FET PROBE TEK TDS694C SCOPE Figure 28. Test Setup for Power-On and Power-Off Response with VSET Grounded Rev. C | Page 11 of 24 49.9Ω 732Ω AD8315 01520-028 1 TEK P6205 FET PROBE TRIG OUT PULSE OUT RF OUT 732Ω AD8315 EXT TRIG STANFORD DS345 PULSE GENERATOR 1 RFIN VPOS 8 2 ENBL VAPC 7 3 VSET NC 4 FLTR COMM 5 6 TEK P6205 FET PROBE TEK P6205 FET PROBE TRIG TEK TDS694C SCOPE 220pF NC = NO CONNECT Figure 30. Test Setup for Power-On and Power-Off Response with VSET and ENBL Grounded 01520-030 Figure 27. Power-On and Power-Off Response with VSET Grounded 10MHz REF R AND S OUTPUT SMT03 SIGNAL GENERATOR 01520-029 GND 01520-027 GND 52.3Ω 2µs PER HORIZONTAL DIVISION AD8315 THEORY OF OPERATION when the net resistive part of the input impedance of the log amp is 50 Ω. However, both the slope and the intercept are dependent on frequency (see Figure 15 and Figure 18). The AD8315 is a wideband logarithmic amplifier (log amp) similar in design to the AD8313 and AD8314. However, it is strictly optimized for use in power control applications rather than as a measurement device. Figure 31 shows the main features in block schematic form. The output (Pin 7, VAPC) is intended to be applied directly to the automatic power-control (APC) pin of a power amplifier module. Keeping in mind that log amps do not respond to power but only to voltages and that the calibration of the intercept is waveform dependent and is only quoted for a sine wave signal, the equivalent power response can be written as BASIC THEORY VOUT = VDB (PIN − PZ) Logarithmic amplifiers provide a type of compression in which a signal having a large range of amplitudes is converted to one of smaller range. The use of the logarithmic function uniquely results in the output representing the decibel value of the input. The fundamental mathematical form is: VIN VZ where: PIN, the input power, and PZ, the equivalent intercept, are both expressed in dBm (thus, the quantity in parentheses is simply a number of decibels). VDB is the slope expressed as so many mV/dB. (1) For a log amp having a slope VDB of 24 mV/dB and an intercept at −57 dBm, the output voltage for an input power of –30 dBm is 0.024 [−30 − (−57)] = 0.648 V. Here VIN is the input voltage, VZ is called the intercept (voltage) because when VIN = VZ the argument of the logarithm is unity and thus the result is zero, and VSLP is called the slope (voltage), which is the amount by which the output changes for a certain change in the ratio (VIN/VZ). When BASE-10 logarithms are used, denoted by the function log10, VSLP represents the volts/ decade, and since a decade corresponds to 20 dB, VSLP/20 represents the volts/dB. For the AD8315, a nominal (low frequency) slope of 24 mV/dB was chosen, and the intercept VZ was placed at the equivalent of −70 dBV for a sine wave input (316 μV rms). This corresponds to a power level of −57 dBm Further details about the structure and function of log amps can be found in data sheets for other log amps produced by Analog Devices, Inc. Refer to the AD640 data sheet and AD8307 data sheet, both of which include a detailed discussion of the basic principles of operation and explain why the intercept depends on waveform, an important consideration when complex modulation is imposed on an RF carrier. (PRECISE GAIN CONTROL) (PRECISE SLOPE CONTROL) (ELIMINATES GLITCH) LOW NOISE GAIN BIAS LOW NOISE BAND GAP REFERENCE OUTPUT ENABLE DELAY VPOS ENBL (CURRENT-MODE SIGNAL) DET DET DET DET DET ×1.35 VAPC LOW NOISE (25nV/√Hz) RAIL-TO-RAIL BUFFER RFIN 10dB COMM (PADDLE) HI-Z 10dB OFFSET COMP’N 10dB 10dB FLTR (CURRENTNULLING MODE) INTERCEPT POSITIONING (WEAK GM STAGE) Figure 31. Block Schematic Rev. C | Page 12 of 24 (CURRENT-MODE FEEDBACK) V-I (SMALL INTERNAL FILTER CAPACITOR FOR GHz RIPPLE) VSET 23mV/dB 250mV TO 1.4V = 50dB 01520-031 VOUT = VSLP log10 (2) AD8315 1.5 dB 1.416V @ –11dBV SL O PE VSET = 24 m V/ 1.0 ACTUAL 0.5 –70dBV IDEAL 0 100µV 1mV –80dBV –60dBV –67dBm –47dBm 10mV –40dBV –27dBm VIN, dBVIN, PIN 100mV –20dBV –7dBm 1V (RMS) 0dBV +13dBm (RE 50Ω) 01520-032 0.288V @ –58dBV Figure 32. Basic Calibration of the AD8315 at 0.1 GHz CONTROLLER-MODE LOG AMPS The AD8315 combines the two key functions required for the measurement and control of the power level over a moderately wide dynamic range. First, it provides the amplification needed to respond to small signals in a chain of four amplifier/limiter cells (see Figure 31), each having a small signal gain of 10 dB and a bandwidth of approximately 3.5 GHz. At the output of each of these amplifier stages is a full-wave rectifier, essentially a square law detector cell that converts the RF signal voltages to a fluctuating current having an average value that increases with signal level. A further passive detector stage is added before the first stage. These five detectors are separated by 10 dB, spanning some 50 dB of dynamic range. Their outputs are each in the form of a differential current, making summation a simple matter. It is readily shown that the summed output can closely approximate a logarithmic function. The overall accuracy at the extremes of this total range, viewed as the deviation from an ideal logarithmic response, that is, the log conformance error, can be judged by referring to Figure 6, which shows that errors across the central 40 dB are moderate. Other performance curves show how conformance to an ideal logarithmic function varies with supply voltage, temperature, and frequency. In a device intended for measurement applications, this current would then be converted to an equivalent voltage, to provide the log (VIN) function shown in Equation 1. However, the design of the AD8315 differs from standard practice in that its output needs to be a low noise control voltage for an RF power amplifier not a direct measure of the input level. Furthermore, it is highly desirable that this voltage be proportional to the time integral of the error between the actual input VIN and the dc voltage VSET (applied to Pin 3, VSET) that defines the setpoint, that is, a target value for the power level, typically generated by a DAC. This is achieved by converting the difference between the sum of the detector outputs (still in current form) and an internally generated current proportional to VSET to a single-sided, current-mode signal. This, in turn, is converted to a voltage (at Pin 4, FLTR, the low-pass filter capacitor node) to provide a close approximation to an exact integration of the error between the power present in the termination at the input of the AD8315 and the setpoint voltage. Finally, the voltage developed across the ground-referenced filter capacitor CFLT is buffered by a special low noise amplifier of low voltage gain (×1.35) and presented at Pin 7 (VAPC) for use as the control voltage for the RF power amplifier. This buffer can provide rail-to-rail swings and can drive a substantial load current, including large capacitors. Note that the RF power amplifier is assumed to have a positive slope with RF power increasing monotonically with an increasing APC control voltage. CONTROL LOOP DYNAMICS To understand how the AD8315 behaves in a complete control loop, an expression for the current in the integration capacitor as a function of the input VIN and the setpoint voltage VSET must be developed (see Figure 33). Rev. C | Page 13 of 24 VSET 3 VSET RFIN 1 VIN SETPOINT INTERFACE LOGARITHMIC RF DETECTION SUBSYSTEM ISET = VSET/4.15kΩ FLTR IDET IERR VAPC ×1.35 4 CFLT IDET = ISLPlog10 (VIN/VZ) Figure 33. Behavioral Model of the AD8315 7 01520-033 The intercept need not correspond to a physically realizable part of the signal range for the log amp. Therefore, the specified intercept is −70 dBV, at 0.1 GHz, whereas the smallest input for accurate measurement (a +1 dB error, see Table 2) at this frequency is higher, being about −58 dBV. At 2.5 GHz, the +1 dB error point shifts to −64 dBV. This positioning of the intercept is deliberate and ensures that the VSET voltage is within the capabilities of certain DACs, whose outputs cannot swing below 200 mV. Figure 32 shows the 100 MHz response of the AD8315; the vertical axis does not represent the output (at pin VAPC) but the value required at the power control pin, VSET, to null the control loop. AD8315 First, the summed detector currents are written as a function of the input IDET = ISLP log10 (VIN/VZ) Equation 6 can be restated as VAPC ( s ) = (3) where: VSET − VSLP log 10 (VIN VZ ) (7) sT where VSLP is the volts-per-decade slope from Equation 1, having a value of 480 mV/decade, and T is an effective time constant for the integration, being equal to 4.15 kΩ × CFLT/1.35; the resistor value comes from the setpoint interface scaling Equation 4 and the factor 1.35 arises because of the voltage gain of the buffer. Therefore, the integration time constant can be written as IDET is the partially filtered demodulated signal, whose exact average value is extracted through the subsequent integration step. ISLP is the current-mode slope and has a value of 115 μA per decade (that is, 5.75 μA/dB). VIN is the input in V rms. VZ is the effective intercept voltage, which, as previously noted, is dependent on waveform but is 316 μV rms (−70 dBV) for a sine wave input. T = 3.07 CFLT in μs, when C is expressed in nF (8) (4) To simplify our understanding of the control loop dynamics, begin by assuming that the power amplifier gain function is actually linear in dB, and for the moment, use voltages to express the signals at the power amplifier input and output. Let the RF output voltage be VPA and let its input be VCW. Furthermore, to characterize the gain control function, this form is used (9) VPA = GOVCW 10 (VAPC VGBC ) VFLT(s) = (ISET − IDET)/sCFLT (5) where: = (6) Now the current generated by the setpoint interface is simply ISET(4) = VSET/415 kΩ The difference between this current and IDET is applied to the loop filter capacitor CFLT. It follows that the voltage appearing on this capacitor, VFLT, is the time integral of the difference current: VSET 4.15 kΩ − I SLP log 10 (VIN VZ ) sC FLT GO is the gain of the power amplifier when VAPC = 0. The control output VAPC is slightly greater than this, because the gain of the output buffer is ×1.35. In addition, an offset voltage is deliberately introduced in this stage; this is inconsequential because the integration function implicitly allows for an arbitrary constant to be added to the form of Equation 6. The polarity is such that VAPC rises to its maximum value for any value of VSET greater than the equivalent value of VIN. In practice, the VAPC output rails to the positive supply under this condition unless the control loop through the power amplifier is present. In other words, the AD8315 seeks to drive the RF power to its maximum value whenever it falls below the setpoint. The use of exact integration results in a final error that is theoretically 0, and the logarithmic detection law would ideally result in a constant response time following a step change of either the setpoint or the power level, if the poweramplifier control function were likewise linear in dB. However, this latter condition is rarely true, and it follows that in practice, the loop response time depends on the power level, and this effect can strongly influence the design of the control loop. VGBC is the gain scaling. While few amplifiers conform so conveniently to this law, it provides a clearer starting point for understanding the more complex situation that arises when the gain control law is less ideal. This idealized control loop is shown in Figure 34. With some manipulation, it is found that the characteristic equation of this system is VAPC ( s ) = (VSET VGBC ) VSLP − VGBC log10 (kGO VCW 1 + sTO VZ ) (10) where: k is the coupling factor from the output of the power amplifier to the input of the AD8315 (for example, ×0.1 for a 20 dB coupler). TO is a modified time constant (VGBC/VSLP)T. This is quite easy to interpret. First, it shows that a system of this sort exhibits a simple single-pole response, for any power level, with the customary exponential time domain form for either increasing or decreasing step polarities in the demand level VSET or the carrier input VCW. Second, it reveals that the final value of the control voltage VAPC is determined by several fixed factors: VAPC (τ = ∞ ) = (VSET VGBC ) VSLP − log 10 (kGO VCW VZ ) (11) Rev. C | Page 14 of 24 AD8315 Example Assume that the gain magnitude of the power amplifier runs from a minimum value of ×0.316 (−10 dB) at VAPC = 0 to ×100 (40 dB) at VAPC = 2.5 V. Applying Equation 9, GO = 0.316 and VGBC = 1 V. Using a coupling factor of k = 0.0316 (that is, a 30 dB directional coupler) and recalling that the nominal value of VSLP is 480 mV and VZ = 316 μV for the AD8315, first calculate the range of values needed for VSET to control an output range of +33 dBm to −17 dBm. This can be found by noting that, in the steady state, the numerator of Equation 7 must be 0, that is: VSET = VSLP log10 (kVPA/VZ) VSET (min) = 0.48 log10 (1 mV/316 μV) = 0.24 V (14) Now, the value of VAPC is of interest, although it is a dependent parameter, inside the loop. It depends on the characteristics of the power amplifier, and the value of the carrier amplitude VCW. Using the control values previously derived, that is, GO = 0.316 and VGBC = 1 V, and assuming the applied power is fixed at −7 dBm (so VCW = 100 mV rms), the following is true using Equation 11 VAPC(max) = (VSETVGBC)/VSLP − log10 kGOVCW/VZ = (1.44 × 1)/0.48 − log10(0.0316 × 0.316 × 0.1/316 μV) RESPONSE-SHAPING OF OVERALL CONTROLLOOP (EXTERNAL CAP) VAPC CFLT Figure 34. Idealized Control Loop for Analysis Finally, using the loop time constant for these parameters and an illustrative value of 2 nF for the filter capacitor CFLT TO = (VGBC/VSLP) T = (1/0.48)3.07 μs × 2 (nF) = 12.8 μs (17) (15) At present time, power amplifiers, or VGAs preceding such amplifiers, do not provide an exponential gain characteristic. It follows that the loop dynamics (the effective time constant) varies with the setpoint because the exponential function is unique in providing constant dynamics. The procedure must therefore be as follows. Beginning with the curve usually provided for the power output vs. the APC voltage, draw a tangent at the point on this curve where the slope is highest (see Figure 35). Using this line, calculate the effective minimum value of the variable VGBC and use it in Equation 17 to determine the time constant. Note that the minimum in VGBC corresponds to the maximum rate of change in the output power vs. VAPC. For example, suppose it is found that, for a given drive power, the amplifier generates an output power of P1 at VAPC = V1 and P2 at VAPC = V2. Then, it is readily shown that VGBC = 20 (V2 − V1)/(P2 − P1) VAPC(min) = (VSETVGBC)/VSLP − log10 kGOVCW/VZ = (0.24 × 1)/0.48 − log10(0.0316 × 0.316 × 0.1/316 μV) = 0.5 − 0.5 = 0 AD8315 01520-034 VSET PRACTICAL LOOP Check that the power range is 50 dB, which should correspond to a voltage change in VSET of 50 dB × 24 mV/dB = 1.2 V, which agrees. = 3.0 − 0.5 = 2.5 V VCW RF PA VIN = kVRF (13) For a delivered power of −17 dBm, VPA = 31.6 mV rms VRF RF DRIVE: UP TO 2.5GHz (12) where VIN is expanded to kVPA, the fractional voltage sample of the power amplifier output. For 33 dBm, VPA = 10 V rms, which evaluates to VSET (max) = 0.48 log10 (316 mV/316 μV) = 1.44 V DIRECTIONAL COUPLER (16) both of which results are consistent with the assumptions made about the amplifier control function. Note that the second term is independent of the delivered power and a fixed function of the drive power. (18) This should be used to calculate the filter capacitance. The response time at high and low power levels (on the shoulders of the curve shown in Figure 35) is slower. Note also that it is sometimes useful to add a 0 in the closed-loop response by placing a resistor in series with CFLT. For more information on this, see the Transient Response section. Rev. C | Page 15 of 24 AD8315 V2, P2 The logarithmic slope, VSLP in Equation 1, which is the amount by which the setpoint voltage needs to be changed for each decibel of input change (voltage or power), is, in principle, independent of waveform or termination impedance. In practice, it usually falls off somewhat at higher frequencies, due to the declining gain of the amplifier stages and other effects in the detector cells (see Figure 15). 33 13 BASIC CONNECTIONS Figure 36 shows the basic connections for operating the AD8315, and Figure 37 shows a block diagram of a typical application. The AD8315 is typically used in the RF power control loop of a mobile handset. 0 0.5 V1, P1 1.0 1.5 2.0 VAPC (V) 2.5 Figure 35. Typical Power-Control Curve A NOTE ABOUT POWER EQUIVALENCY In using the AD8315, it must be understood that log amps do not fundamentally respond to power. It is for this reason that dBV (decibels above 1 V rms) are used rather than the commonly used metric of dBm. The dBV scaling is fixed, independent of termination impedance, while the corresponding power level is not. For example, 224 mV rms is always −13 dBV (with one further condition of an assumed sinusoidal waveform; see the AD640 data sheet for more information about the effect of waveform on logarithmic intercept), and this corresponds to a power of 0 dBm when the net impedance at the input is 50 Ω. When this impedance is altered to 200 Ω, however, the same voltage corresponds to a power level that is four times smaller (P = V2/R) or −6 dBm. A dBV level can be converted to dBm in the special case of a 50 Ω system and a sinusoidal signal by simply adding 13 dB (0 dBV is then, and only then, equivalent to 13 dBm). A supply voltage of 2.7 V to 5.5 V is required for the AD8315. The supply to the VPOS pin should be decoupled with a low inductance 0.1 μF surface-mount ceramic capacitor, close to the device. The AD8315 has an internal input coupling capacitor. This negates the need for external ac coupling. This capacitor, along with the low frequency input impedance of the device of approximately 2.8 kΩ, sets the minimum usable input frequency to around 0.016 GHz. A broadband 50 Ω input match is achieved in this example by connecting a 52.3 Ω resistor between RFIN and ground. A plot of input impedance vs. frequency is shown in Figure 11. Other coupling methods are also possible (see Input Coupling Options section). Therefore, the external termination added ahead of the AD8315 determines the effective power scaling. This often takes the form of a simple resistor (52.3 Ω provides a net 50 Ω input), but more elaborate matching networks can be used. The choice of impedance determines the logarithmic intercept, that is, the input power for which the VSET vs. PIN function would cross the baseline if that relationship were continuous for all values of VIN. This is never the case for a practical log amp; the intercept (so many dBV) refers to the value obtained by the minimum error straight line fit to the actual graph of VSET vs. PIN (more generally, VIN). Where the modulation is complex, as in CDMA, the calibration of the power response needs to be adjusted; the intercept remains stable for any given arbitrary waveform. When a true power (waveform independent) response is needed, a mean-responding detector, such as the AD8361, should be considered. Rev. C | Page 16 of 24 R1 52.3Ω C1 0.1µF AD8315 1 RFIN VPOS 8 +VS +VS 2 ENBL VAPC 7 (2.7V TO 5.5V) +VAPC VSET 3 VSET NC 6 4 FLTR COMM 5 RFIN CFLT 01520-036 –7 01520-035 3 NC = NO CONNECT Figure 36. Basic Connections POWER AMP DIRECTIONAL COUPLER ATTENUATOR RFIN GAIN CONTROL VOLTAGE VAPC AD8315 VSET RFIN 52.3Ω DAC FLTR CFLT Figure 37. Typical Application 01520-037 PRF (dBm) 23 AD8315 In a power control loop, the AD8315 provides both the detector and controller functions. A sample of the power amplifier’s (PA) output power is coupled to the RF input of the AD8315, usually via a directional coupler. In dual-mode applications, where there are two PAs and two directional couplers, the outputs of the directional couplers can be passively combined (both PAs will never be turned on simultaneously) before being applied to the AD8315. A setpoint voltage is applied to VSET from the controlling source (generally, this is a DAC). Any imbalance between the RF input level and the level corresponding to the setpoint voltage is corrected by the AD8315’s VAPC output that drives the gain control terminal of the PA. This restores a balance between the actual power level sensed at the input of the AD8315 and the value determined by the setpoint. This assumes that the gain control sense of the variable gain element is positive, that is, an increasing voltage from VAPC tends to increase gain. VAPC can swing from 250 mV to within 100 mV of the supply rail and can source up to 6 mA. If the control input of the PA needs to source current, a suitable load resistor can be connected between VAPC and COMM. The output swing and current sourcing capability of VAPC is shown in Figure 21. RANGE ON VSET AND RFIN The relationship between the RF input level and the setpoint voltage follows from the nominal transfer function of the device (see Figure 4, Figure 5, Figure 7, and Figure 8). At 0.9 GHz, for example, a voltage of 1 V on VSET indicates a demand for −30 dBV (−17 dBm, re 50 Ω) at RFIN. The corresponding power level at the output of the power amplifier is greater than this amount due to the attenuation through the directional coupler. For setpoint voltages of less than approximately 250 mV, VAPC remains unconditionally at its minimum level of approximately 250 mV. This feature can be used to prevent any spurious emissions during power-up and power-down phases. Above 250 mV, VSET has a linear control range up to 1.4 V, corresponding to a dynamic range of 50 dB. This results in a slope of 23 mV/dB or approximately 43.5 dB/V. TRANSIENT RESPONSE The time domain response of power amplifier control loops, using any kind of controller, is only partially determined by the choice of filter, which, in the case of the AD8315, has a true integrator form 1/sT, as shown in Equation 7, with a time constant given by Equation 8. The large signal step response is also strongly dependent on the form of the gain-control law. Nevertheless, some simple rules can be applied. When the filter capacitor CFLT is very large, it dominates the time domain response, but the incremental bandwidth of this loop still varies as VAPC traverses the nonlinear gain-control function of the PA, as shown in Figure 35. This bandwidth is highest at the point where the slope of the tangent drawn on this curve is greatest, that is, for power outputs near the center of the PA’s range, and is much reduced at both the minimum and the maximum power levels, where the slope of the gain control curve is lowest due to its S-shaped form. Using smaller values of CFLT, the loop bandwidth generally increases in inverse proportion to its value. Eventually, however, a secondary effect appears due to the inherent phase lag in the power amplifier’s control path, some of which can be due to parasitic or deliberately added capacitance at the VAPC pin. This results in the characteristic poles in the ac loop equation moving off the real axis and thus becoming complex (and somewhat resonant). This is a classic aspect of control loop design. The lowest permissible value of CFLT needs to be determined experimentally for a particular amplifier. For GSM and DCS power amplifiers, CFLT typically ranges from 150 pF to 300 pF. In many cases, some improvement in the worst-case response time can be achieved by including a small resistance in series with CFLT; this generates an additional 0 in the closed-loop transfer function, that serves to cancel some of the higher order poles in the overall loop. A combination of main capacitor CFLT shunted by a second capacitor and resistor in series is also useful in minimizing the settling time of the loop. Rev. C | Page 17 of 24 AD8315 3.5V 4.7µF 4.7µF 1000pF 1000pF BAND SELECT 0V/2V LDC15D190A0007A TO ANTENNA POUT GSM 35dBm MAX 7 1 8 4 49.9Ω 5 3 2 PIN GSM 3dBm VCTL PF08107B PIN DCS 3dBm VAPC POUT DCS 32dBm MAX 6 500Ω ATTN 20dB (OPTIONAL, SEE TEXT) 0.1µF R1 52.3Ω 8-BIT RAMP DAC 0V TO 2.55V ENABLE 0V/2.7V R21 600Ω R31 1kΩ AD8315 1 RFIN VPOS 8 2 ENBL VAPC 7 3 VSET NC 6 4 FLTR COMM 5 +VS 2.7V 1R2, R3 OPTIONAL, 1.5kΩ NC = NO CONNECT SEE TEXT 01520-038 150pF Figure 38. Dual-Mode (GSM/DCS) PA Control Example MOBILE HANDSET POWER CONTROL EXAMPLE Figure 38 shows a complete power amplifier control circuit for a dual-mode handset. The PF08107B (Hitachi), a dual mode (GSM, DCS) PA, is driven by a nominal power level of 3 dBm. The PA has a single gain control line; the band to be used is selected by applying either 0 V or 2 V to the PA’s VCTL input. Some of the output power from the PA is coupled off using a dual-band directional coupler (Murata LDC15D190A0007A). This has a coupling factor of approximately 19 dB for the GSM band and 14 dB for DCS and an insertion loss of 0.38 dB and 0.45 dB, respectively. Because the PF08107B transmits a maximum power level of 35 dBm for GSM and 32 dBm for DCS, additional attenuation of 20 dB is required before the coupled signal is applied to the AD8315. This results in peak input levels to the AD8315 of −4 dBm (GSM) and −2 dBm (DCS). While the AD8315 gives a linear response for input levels up to 2 dBm, for highly temperature-stable performance at maximum PA output power, the maximum input level should be limited to approximately −2 dBm (see Figure 5 and Figure 7). This does, however, reduce the sensitivity of the circuit at the low end. The operational setpoint voltage, in the range 250 mV to 1.4 V, is applied to the VSET pin of the AD8315. This is typically supplied by a DAC. The AD8315’s VAPC output drives the level control pin of the power amplifier directly. VAPC reaches a maximum value of approximately 2.5 V on a 2.7 V supply while delivering the 3 mA required by the level control input of the PA. This is more than sufficient to exercise the gain control range of the PA. During initialization and completion of the transmit sequence, VAPC should be held at its minimum level of 250 mV by keeping VSET below 200 mV. In this example, VSET is supplied by an 8-bit DAC that has an output range from 0 V to 2.55 V or 10 mV per bit. This sets the control resolution of VSET to 0.4 dB/bit (0.04 dB/mV times 10 mV). If finer resolution is required, the DAC’s output voltage can be scaled using two resistors, as shown in Figure 38. This converts the DAC’s maximum voltage of 2.55 V down to 1.6 V and increases the control resolution to 0.25 dB/bit. A filter capacitor (CFLT) must be used to stabilize the loop. The choice of CFLT depends to a large degree on the gain control dynamics of the power amplifier, something that is frequently poorly characterized, so some trial and error can be necessary. In this example, a 150 pF capacitor is used and a 1.5 kΩ series resistor is included. This adds a zero to the control loop and Rev. C | Page 18 of 24 AD8315 increases the phase margin, which helps to make the step response of the circuit more stable when the PA output power is low and the slope of the PA’s power control function is the steepest. In both situations, the voltage on VSET should be kept below 200 mV during power-on and power-off to prevent any unwanted transients on VAPC. A smaller filter capacitor can be used by inserting a series resistor between VAPC and the control input of the PA. A series resistor works with the input impedance of the PA to create a resistor divider and reduces the loop gain. The size of the resistor divider ratio depends upon the available output swing of VAPC and the required control voltage on the PA. INPUT COUPLING OPTIONS This technique can also be used to limit the control voltage in situations where the PA cannot deliver the power level being demanded by VAPC. Overdrive of the control input of some PAs causes increased distortion. It should be noted, however, that if the control loop opens (that is, VAPC goes to its maximum value in an effort to balance the loop), the quiescent current of the AD8315 increases somewhat, particularly at supply voltages greater than 3 V. Figure 39 shows the relationship between VSET and output power (POUT) at 0.9 GHz . The overall gain control function is linear in dB for a dynamic range of over 40 dB. Note that for VSET voltages below 300 mV, the output power drops off steeply as VAPC drops toward its minimum level of 250 mV. 40 4 +85°C 30 3 +25°C 20 2 +85°C 10 1 –30°C 0 0 –10 –1 –2 –30 –3 –40 0 0.2 0.4 0.6 0.8 VSET (V) 1.0 1.2 1.4 –4 1.6 AD8315 01520-039 –30°C –20 A reactive match can also be implemented as shown in Figure 41. This is not recommended at low frequencies as device tolerances dramatically vary the quality of the match because of the large input resistance. For low frequencies, Figure 40 or Figure 42 is recommended. In Figure 41, the matching components are drawn as generic reactances. Depending on the frequency, the input impedance and the availability of standard value components, either a capacitor or an inductor is used. As in the previous case, the input impedance at a particular frequency is plotted on a Smith Chart and matching components are chosen (shunt or series L, shunt or series C) to move the impedance to the center of the chart. ERROR (dB) POUT (dBm) +25°C The internal 5 pF coupling capacitor of the AD8315, along with the low frequency input impedance of 2.8 kΩ, give a high-pass input corner frequency of approximately 16 MHz. This sets the minimum operating frequency. Figure 40, Figure 41, and Figure 42 show three options for input coupling. A broadband resistive match can be implemented by connecting a shunt resistor to ground at RFIN (see Figure 40). This 52.3 Ω resistor (other values can also be used to select different overall input impedances) combines with the input impedance of the AD8315 to give a broadband input impedance of 50 Ω. While the input resistance and capacitance (CIN and RIN) of the AD8315 varies from device to device by approximately ±20%, and over frequency (see Figure 11), the dominance of the external shunt resistor means that the variation in the overall input impedance is close to the tolerance of the external resistor. This method of matching is most useful in wideband applications or in multiband systems where there is more than one operating frequency. RFIN Figure 39. POUT vs. VSET at 0.9 GHz for Dual-Mode Handset Power Amplifier Application, −30°C, +25°C, and +85°C RSHUNT 52.3V CC CIN RIN Figure 40. Broadband Resistive Input Coupling Option AD8315 X1 X2 RFIN CC CIN RIN 01520-041 The AD8315 can be disabled by pulling the ENBL pin to ground. This reduces the supply current from its nominal level of 7.4 mA to 4 μA. The logic threshold for turning on the device is at 1.5 V with 2.7 V supply voltage. A plot of the enable glitch is shown in Figure 22. Alternatively, the device can be completely disabled by pulling the supply voltage to ground. To minimize glitch in this mode, ENBL and VPOS should be tied together. If VPOS is applied before the device is enabled, a narrow 750 mV glitch results (see Figure 29). 01520-040 ENABLE AND POWER-ON Figure 41. Narrow-Band Reactive Input Coupling Option Rev. C | Page 19 of 24 AD8315 EVALUATION BOARD ANTENNA AD8315 RFIN RATTN CIN PA RIN 01520-042 STRIPLINE CC Figure 42. Series Attention Input Coupling Option Figure 42 shows a third method for coupling the input signal into the AD8315. A series resistor, connected to the RF source, combines with the input impedance of the AD8315 to resistively divide the input signal being applied to the input. This has the advantage of very little power being tapped off in RF power transmission applications. Figure 43 shows the schematic of the AD8315 MSOP evaluation board. The layout and silkscreen of the component side are shown in Figure 44 and Figure 45. An evaluation board is also available for the LFCSP package (see the Ordering Guide for exact part numbers). Apart from the slightly smaller device footprint, the LFCSP evaluation board is identical to the MSOP board. The board is powered by a single supply in the 2.7 V to 5.5 V range. The power supply is decoupled by a single 0.1 μF capacitor. Table 5 details the various configuration options of the evaluation board. J1 RFIN USING THE CHIP SCALE PACKAGE On the underside of the chip scale package, there is an exposed paddle. This paddle is internally connected to the chip’s ground. There is no thermal requirement to solder the paddle down to the printed circuit board’s ground plane. However, soldering down the paddle has been shown to increase the stability over frequency of the AD8315 ACP’s response at low input power levels (that is, at around −45 dBm) in the DCS and PCS bands. R1 0Ω R2 52.3Ω VPOS SW1 J2 VSET 1 RFIN VPOS 8 2 ENBL VAPC 7 LK1 4 FLTR TP1 R3 0Ω VPOS R4 NC 6 TP2 (OPEN) 3 VSET C4 (OPEN) C1 0.1µF AD8315 J2 VAPC C2 (OPEN) COMM 5 NC = NO CONNECT LK2 VPOS C3 0.1µF C5 0.1µF R7 16.2kΩ R8 10kΩ AD8031 01520-043 R6 17.8kΩ R5 10kΩ Figure 43. Evaluation Board Schematic (MSOP) Table 5. Evaluation Board Configuration Options Component TP1, TP2 SW1 R1, R2 R3, R4, C2 C1 C4 LK1, LK2 Function Supply and Ground Vector Pins. Device Enable. When in Position A, the ENBL pin is connected to VPOS and the AD8315 is in operating mode. In Position B, the ENBL pin is grounded putting the device in power-down mode. Input Interface. The 52.3 Ω resistor in Position R2 combines with the AD8315’s internal input impedance to give a broadband input impedance of around 50 Ω. A reactive match can be implemented by replacing R2 with an inductor and R1 (0 Ω) with a capacitor. Note that the AD8315’s RF input is internally ac-coupled. Output Interface. R4 and C2 can be used to check the response of VAPC to capacitive and resistive loading. R3/R4 can be used to reduce the slope of VAPC. Power Supply Decoupling. The nominal supply decoupling consists of a 0.1 μF capacitor. Filter Capacitor. The response time of VAPC can be modified by placing a capacitor between FLTR (Pin 4) and ground. Measurement Mode. A quasimeasurement mode can be implemented by installing LK1 and LK2 (connecting an inverted VAPC to VSET) to yield the nominal relationship between RFIN and VSET. In this mode, a large capacitor (0.01 μF or greater) must be installed in C4. Rev. C | Page 20 of 24 Default Condition Not Applicable SW1 = A R2 = 52.3 Ω (Size 0603) R1 = 0 Ω (Size 0402) R4 = C2 = Open (Size 0603) R3 = 0 Ω (Size 0603) C1 = 0.1 μF (Size 0603) C4 = Open (Size 0603) LK1, LK2 = Installed AD8315 For operation in controller mode, both jumpers, LK1 and LK2, should be removed. The setpoint voltage is applied to VSET, RFIN is connected to the RF source (PA output or directional coupler), and VAPC is connected to the gain control pin of the PA. When used in controller mode, a capacitor must be installed in C4 for loop stability. For GSM/DCS handset power amplifiers, this capacitor should typically range from 150 pF to 300 pF. 01520-044 A quasimeasurement mode (where the AD8315 delivers an output voltage that is proportional to the log of the input signal) can be implemented, to establish the relationship between VSET and RFIN, by installing the two jumpers, LK1 and LK2. This mimics an AGC loop. To establish the transfer function of the log amp, the RF input should be swept while the voltage on VSET is measured, that is, the SMA connector labeled VSET now acts as an output. This is the simplest method to validate operation of the evaluation board. When operated in this mode, a large capacitor (0.01 μF or greater) must be installed in C4 (filter capacitor) to ensure loop stability. Figure 44. Layout of Component Side (MSOP) EVALUATION BOARD REV A TP2 SW1 RFIN J1 B AD8315 GND VPOS TP1 PWDN R3 C2 A R4 PWUP VAPC J2 C1 R2 Z1 C5 R7 R1 C4 R5 J3 VSET A1 R6 R8 C3 LK2 08 - 006794 REV A COMPONENT SIDE 01520-045 LK1 Figure 45. Silkscreen of Component Side (MSOP) Rev. C | Page 21 of 24 AD8315 OUTLINE DIMENSIONS 3.20 3.00 2.80 8 3.20 3.00 2.80 5 1 5.15 4.90 4.65 4 PIN 1 0.65 BSC 0.95 0.85 0.75 1.10 MAX 0.15 0.00 0.38 0.22 COPLANARITY 0.10 0.80 0.60 0.40 8° 0° 0.23 0.08 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 46. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 1.89 1.74 1.59 3.25 3.00 2.75 1.95 1.75 1.55 TOP VIEW 12° MAX 5 BOTTOM VIEW 8 EXPOSEDPAD 4 2.95 2.75 2.55 PIN 1 INDICATOR 1.00 0.85 0.80 0.60 0.45 0.30 2.25 2.00 1.75 0.55 0.40 0.30 0.50 BSC 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 0.20 REF Figure 47. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] 2 mm × 3 mm Body, Very Thin, Dual Lead (CP-8-1) Dimensions shown in millimeters Rev. C | Page 22 of 24 0.15 0.10 0.05 1 0.25 0.20 0.15 AD8315 ORDERING GUIDE Model AD8315ARM AD8315ARM-REEL AD8315ARM-REEL7 AD8315ARMZ 1 AD8315ARMZ-RL1 AD8315-EVAL AD8315ACP-REEL AD8315ACP-REEL7 AD8315ACPZ-REEL1 AD8315ACPZ-REEL71 AD8315ACP-EVAL AD8315CSURF AD8315ACHIPS 1 Temperature Range −30°C to +85°C −30°C to +85°C −30°C to +85°C −30°C to +85°C −30°C to +85°C −30°C to +85°C −30°C to +85°C −30°C to +85°C −30°C to +85°C Package Description 8-Lead MSOP, Tube 8-Lead MSOP, 13" Tape and Reel 8-Lead MSOP, 7" Tape and Reel 8-Lead MSOP, Tube 8-Lead MSOP, 13" Tape and Reel MSOP Evaluation Board 8-Lead LFCSP_VD, 13" Tape and Reel 8-Lead LFCSP_VD, 7" Tape and Reel 8-Lead LFCSP_VD, 13" Tape and Reel 8-Lead LFCSP_VD, 7" Tape and Reel LFCSP_VD Evaluation Board Die, Surf Tape Die, Waffle Pack Z = Pb-free part. Rev. C | Page 23 of 24 Package Option RM-8 RM-8 RM-8 RM-8 RM-8 Ordering Quantity 50 3,000 1,000 50 3,000 Branding J7A J7A J7A Q0S Q0S CP-8-1 CP-8-1 CP-8-1 CP-8-1 10,000 3,000 10,000 3,000 J7 J7 0J 0J DIE DIE 5,000 325 AD8315 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C01520-0-6/06(C) Rev. C | Page 24 of 24

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