ETC CS51033/D

CS51033
Fast PFET Buck Controller
The CS51033 is a switching controller for use in DC–DC
converters. It can be used in the buck topology with a minimum
number of external components. The CS51033 consists of a 1.0 A
power driver for controlling the gate of a discrete P–channel transistor,
fixed frequency oscillator, short circuit protection timer,
programmable Soft Start, precision reference, fast output voltage
monitoring comparator, and output stage driver logic with latch.
The high frequency oscillator allows the use of small inductors and
output capacitors, minimizing PC board area and systems cost. The
programmable Soft Start reduces current surges at start up. The short
circuit protection timer significantly reduces the PFET duty cycle to
approximately 1/30 of its normal cycle during short circuit conditions.
The CS51033 is available in 8 Lead SO and 8 Lead PDIP plastic
packages.
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MARKING
DIAGRAMS
8
SO–8
D SUFFIX
CASE 751
8
1
51033
ALYW
1
8
Features
1.0 A Totem Pole Output Driver
High Speed Oscillator (700 kHz max)
No Stability Compensation Required
Lossless Short Circuit Protection
2.0% Precision Reference
Programmable Soft Start
Wide Ambient Temperature Range:
– Industrial Grade: –40°C to 85°C
– Commercial Grade: 0°C to 70°C
•
•
•
•
•
•
•
DIP–8
N SUFFIX
CASE 626
8
CS51033
AWL
YYWW
1
1
A
WL, L
YY, Y
WW, W
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN CONNECTIONS
VGATE
1
VC
PGND
CS
COSC
GND
VCC
VFB
ORDERING INFORMATION*
Device
Package
Shipping
CS51033ED8
SO–8
95 Units/Rail
CS51033EDR8
SO–8
2500 Tape & Reel
CS51033EN8
DIP–8
50 Units/Rail
CS51033GD8
SO–8
95 Units/Rail
CS51033GDR8
SO–8
2500 Tape & Reel
CS51033GN8
DIP–8
50 Units/Rail
*Additional ordering information can be found on page
9 of this data sheet.
 Semiconductor Components Industries, LLC, 2001
January, 2001 – Rev. 7
1
Publication Order Number:
CS51033/D
CS51033
3.3VIN
CIN
100 µF
D2
1N4148
RC
10 Ω
D4
1N5818
C1
D3
1N4148
0.1 µF
RG
VC V
GATE
VCC
COSC
U1
CS51033
10 Ω
VFB
IRF7404
0.1 µF
4.7 µH
1.5VOUT
@ 3.0 Amp
100
C2
1.0 µF
C3
100 µF
COSC
150 pF
GND PGND CS
0.1 µF
CS
C0
100 µF
0.1 µF
100 µF
C4
0.1 µF
D1
1N5821
GND
GND
RA
1.5 k
RB
300
Note: Capacitors C2, C3, and C4, are low
ESR tantalum caps used for noise reduction.
Figure 1. Typical Application Diagram
ABSOLUTE MAXIMUM RATINGS*
Rating
Value
Unit
Power Supply Voltage, VCC
5.0
V
Driver Supply Voltage, VC
20
V
Driver Output Voltage, VGATE
20
V
COSC, CS, VFB (Logic Pins)
5.0
V
Peak Output Current
1.0
A
Steady State Output Current
200
mA
Operating Junction Temperature, TJ
150
°C
–65 to 150
°C
2.0
kV
260 peak
230 peak
°C
°C
Storage Temperature Range, TS
ESD (Human Body Model)
Lead Temperature Soldering:
Wave Solder: (through hole styles only) (Note 1.)
Reflow (SMD styles only) (Note 2.)
1. 10 sec. maximum.
2. 60 sec. max above 183°C.
*The maximum package power dissipation must be observed.
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2
CS51033
ELECTRICAL CHARACTERISTICS (Specifications apply for 3.135 ≤ VCC ≤ 3.465, 3.0 V ≤ VC ≤ 16 V;
Industrial Grade: –40°C < TA < 85°C; –40°C < TJ < 125°C: Commercial Grade: 0°C < TA < 70°C; 0°C < TJ < 125°C, unless otherwise specified.)
Test Conditions
Characteristic
Oscillator
Min
Typ
Max
Unit
160
200
240
kHz
VFB = 1.2 V
Frequency
COSC = 470 pF
Charge Current
1.4 V < VCOSC < 2.0 V
–
110
–
µA
Discharge Current
2.7 V > VCOSC > 2.0 V
–
660
–
µA
Maximum Duty Cycle
1 – (tOFF/tON)
80.0
83.3
–
%
Short Circuit Timer
VFB = 1.0 V; CS = 0.1 F; VCOSC = 2.0 V
Charge Current
1.0 V < VCS < 2.0 V
175
264
325
µA
Fast Discharge Current
2.55 V > VCS > 2.4 V
40
66
80
µA
Slow Discharge Current
2.4 V > VCS > 1.5 V
4.0
6.0
10
µA
0.70
0.85
1.40
ms
Start Fault Inhibit Time
–
Valid Fault Time
2.6 V > VCS > 2.4 V
0.2
0.3
0.45
ms
GATE Inhibit Time
2.4 V > VCS > 1.5 V
9.0
15
23
ms
–
2.5
3.1
4.6
%
–
–
2.5
–
V
Duty Cycle
CS Comparator
VFB = 1.0 V
Fault Enable CS Voltage
Max. CS Voltage
VFB = 1.5 V
–
2.6
–
V
Fault Detect Voltage
VCS when GATE goes high
–
2.4
–
V
Fault Inhibit Voltage
Minimum VCS
–
1.5
–
V
Hold Off Release Voltage
VFB = 0 V
0.4
0.7
1.0
V
Regulator Threshold Voltage Clamp
VCS = 1.5 V
0.725
0.866
1.035
V
VFB Comparators
VCOSC = VCS = 2.0 V
Regulator Threshold Voltage
TJ = 25°C (Note 3.)
TJ = –40 to 125°C
1.225
1.210
1.250
1.250
1.275
1.290
V
V
Fault Threshold Voltage
TJ = 25°C (Note 3.)
TJ = –40 to 125°C
1.12
1.10
1.15
1.15
1.17
1.19
V
V
Threshold Line Regulation
3.135 V ≤ VCC ≤ 3.465
–
6.0
15
mV
Input Bias Current
VFB = 0 V
–
1.0
4.0
µA
Voltage Tracking
(Regulator Threshold – Fault Threshold Voltage)
70
100
120
mV
–
–
4.0
20
mV
Input Hysteresis Voltage
Power Stage
VC = 10 V; VFB = 1.2 V
GATE DC Low Saturation Voltage
VCOSC = 1.0 V; 200 mA Sink
–
1.2
1.5
V
GATE DC High Saturation Voltage
VCOSC = 2.7 V; 200 mA Source; VC = VGATE
–
1.5
2.1
V
Rise Time
CGATE = 1.0 nF; 1.5 V < VGATE < 9.0 V
–
25
60
ns
Fall Time
CGATE = 1.0 nF; 9.0 V > VGATE > 1.5 V
–
25
60
ns
ICC
3.135 V < VCC < 3.465 V, Gate switching
–
3.5
6.0
mA
IC
3.0 V < VC < 16 V, Gate non–switching
–
2.7
4.0
mA
Current Drain
3. Guaranteed by design, not 100% tested in production.
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3
CS51033
PACKAGE LEAD DESCRIPTION
PACKAGE PIN NUMBER
SO–8
DIP–8
PIN SYMBOL
1
1
VGATE
Driver pin to gate of external PFET.
2
2
PGND
Output power stage ground connection.
3
3
COSC
Oscillator frequency programming capacitor.
4
4
GND
Logic ground.
5
5
VFB
Feedback voltage input.
6
6
VCC
Logic supply voltage.
7
7
CS
Soft Start and fault timing capacitor.
8
8
VC
Driver supply voltage.
FUNCTION
VC
VCC
RG
IC
Oscillator
7IC
VGATE
VGATE
Flip–Flop
+ Comparator
A1
–
COSC
G1
R
Q
F2
G2
Q
2.5 V
–
–
+
–
+
1.5 V
PGND
S
VFB
Comparator
A6
+
0.7 V
–
+
+
VCC
–
+
Hold Off
Comp
VFB
1.25 V
–
VCC
–
1.15 V
CS Charge
Sense
Comparator
G3
+
A4
IT
CS
Comparator
–
+
+
A2
–
1.5 V
R
2.3 V
Q
F1
G5
2.5 V
2.4 V
–
+
IT
5
–
+
IT
55
–
+
CS
–
+
G4
–
+
Fault
Comp
–
A3
+
Slow Discharge
Comparator
S
Q
Slow Discharge
Flip–Flop
GND
Figure 2. Block Diagram
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4
CS51033
CIRCUIT DESCRIPTION
THEORY OF OPERATION
pin during startup, permitting the control loop and the output
voltage to slowly increase. Once the CS pin charges above
the Holdoff Comparator trip point of 0.7 V, the low feedback
to the VFB Comparator sets the GATE flip–flop during
COSC’s charge cycle. Once the GATE flip–flop is set,
VGATE goes low and turns on the PFET. When VCS exceeds
2.4 V, the CS charge sense comparator (A4) sets the VFB
comparator reference to 1.25 V completing the startup cycle.
Control Scheme
The CS51033 monitors the output voltage to determine
when to turn on the PFET. If VFB falls below the internal
reference voltage of 1.25 V during the oscillator’s charge
cycle, the PFET is turned on and remains on for the duration
of the charge time. The PFET gets turned off and remains off
during the oscillator’s discharge cycle time with the
maximum duty cycle to 80%. It requires 7.0 mV typical, and
20 mV maximum ripple on the VFB pin to operate. This
method of control does not require any loop stability
compensation.
Lossless Short Circuit Protection
The CS51033 has “lossless” short circuit protection since
there is no current sense resistor required. When the voltage
at the CS pin (the fault timing capacitor voltage ) reaches
2.5 V, the fault timing circuitry is enabled. During normal
operation the CS voltage is 2.6 V. During a short circuit or
a transient condition, the output voltage moves lower and the
voltage at VFB drops. If VFB drops below 1.15 V, the output
of the fault comparator goes high and the CS51033 goes into
a fast discharge mode. The fault timing capacitor, CS,
discharges to 2.4 V. If the VFB voltage is still below 1.15 V
when the CS pin reaches 2.4 V, a valid fault condition has
been detected. The slow discharge comparator output goes
high and enables gate G5 which sets the slow discharge flip
flop. The VGATE flip flop resets and the output switch is
turned off. The fault timing capacitor is slowly discharged
to 1.5 V. The CS51033 then enters a normal startup routine.
If the fault is still present when the fault timing capacitor
voltage reaches 2.5 V, the fast and slow discharge cycles
repeat as shown in Figure 3.
If the VFB voltage is above 1.15 V when CS reaches 2.4 V
a fault condition is not detected, normal operation resumes
and CS charges back to 2.6 V. This reduces the chance of
erroneously detecting a load transient as a fault condition.
Startup
The CS51033 has an externally programmable Soft Start
feature that allows the output voltage to come up slowly,
preventing voltage overshoot on the output.
At startup, the voltage on all pins is zero. As VCC rises, the
VC voltage along with the internal resistor RG keeps the
PFET off. As VCC and VC continue to rise, the oscillator
capacitor (COSC ) and the Soft Start/Fault Timing capacitor
(CS) charges via internal current sources. COSC gets charged
by the current source IC and CS gets charged by the IT source
combination described by:
I
I
ICS IT T T
55
5
The internal Holdoff Comparator ensures that the external
PFET is off until VCS > 0.7 V, preventing the GATE flip–flop
(F2) from being set. This allows the oscillator to reach its
operating frequency before enabling the drive output. Soft
Start is obtained by clamping the VFB comparator’s (A6)
reference input to approximately 1/2 of the voltage at the CS
2.6 V
VCS
S2
2.4 V
S2
S1
S3
S3
S1
2.5 V
S2
S3
S1
S3
1.5 V
0V
0V
TSTART
START
td1
NORMAL OPERATION
tFAULT
tRESTART
td2
FAULT
VGATE
1.25 V
1.15 V
VFB
Figure 3. Voltage on Start Capacitor (VGS), the Gate (VGATE), and in the
Feedback Loop (VFB), During Startup, Normal and Fault Conditions.
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5
tFAULT
CS51033
Buck Regulator Operation
and R2 and the reference voltage VREF, the power transistor
Q1 switches on and current flows through the inductor to the
output. The inductor current rises at a rate determined by
(VIN – VOUT)/Load. The duty cycle (or “on” time) for the
CS51033 is limited to 80%. If output voltage remains higher
than nominal during the entire COSC change time, the Q1
does not turn on, skipping the pulse.
A block diagram of a typical buck regulator is shown in
Figure 4. If we assume that the output transistor is initially
off, and the system is in discontinuous operation, the
inductor current IL is zero and the output voltage is at its
nominal value. The current drawn by the load is supplied by
the output capacitor CO. When the voltage across CO drops
below the threshold established by the feedback resistors R1
L
Q1
VIN
R1
CIN
CO
D1
RLOAD
R2
Control
Feedback
Figure 4. Buck Regulator Block Diagram.
Charge Pump Circuit
turns on, it’s drain voltage will be approximately equal to
VIN. Since the voltage across C1 can not change
instantaneously, D2 is reverse biased and the anode voltage
rises to approximately 2.0 × 3.3 V – VD2. C1 transfers some
of its stored charge C2 via D3. After several cycles there is
sufficient gate drive voltage.
(Refer to the CS51033 Application Diagram on page 2).
An external charge pump circuit is necessary when the VC
input voltage is below 5.0 V to ensure that there is suffifient
gate drive voltage for the external FET. When VIN is applied,
capacitors C1 and C2 will be charged to a diodes drop below
VIN via diodes D2 and D4, respectively. When the PFET
APPLICATIONS INFORMATION
DESIGNING A POWER SUPPLY WITH THE CS51033
In this case we can assume that VD = 0.6 V and VSAT =
0.6 V so the equation reduces to:
Specifications
•
•
•
•
•
V
D OUT
VIN
VIN = 3.3 V ±10% (i.e. 3.63 V max., 2.97 V min.)
VOUT = 1.5 V ±2.0%
IOUT = 0.3 A to 3.0 A
Output ripple voltage < 33 mV.
FSW = 200 kHz
From this, the maximum duty cycle DMAX is 53%, this
occurs when VIN is at it’s minimum while the minimum duty
cycle DMIN is 0.35%.
2) Switching Frequency and On and Off Time
Calculations
1) Duty Cycle Estimates
Since the maximum duty cycle D, of the CS51033 is
limited to 80% min., it is best to estimate the duty cycle for
the various input conditions to see that the design will work
over the complete operating range.
The duty cycle for a buck regulator operating in a
continuous conduction mode is given by:
FSW = 200 kHz. The switching frequency is determined
by COSC, whose value is determined by:
COSC V
VD
D OUT
VIN VSAT
95
SW 3010
FSW 1 310
6 FSW
F
T 1.0 5.0 s
FSW
where:
VSAT = RDS(ON) × IOUT Max.
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6
3 2
470 pF
CS51033
TON(MAX) 5.0 s 0.53 2.65 s
5) VFB Divider
TON(MIN) 5.0 s 0.35 1.75 s
VOUT 1.25 V R1 R2 1.25 V R1 1.0
R2
R2
TOFF(MAX) 5.0 s 0.7 s 4.3 s
Pick the inductor value to maintain continuous mode
operation down to 0.3 Amps.
The ripple current ∆I = 2 × IOUT(MIN) = 2 × 0.3 A = 0.6 A.
The input bias current to the comparator is 4.0 µA. The
resistor divider current should be considerably higher than
this to ensure that there is sufficient bias current. If we
choose the divider current to be at least 250 times the bias
current this gives a divider current of 1.0 mA and simplifies
the calculations.
2.1 V 4.3 s
V
VD TOFF(MAX)
LMIN OUT
15 H
I
0.6 A
1.5 V R1 R2 1.5 k
1.0 mA
3) Inductor Selection
Let R2 = 1.0 k
Rearranging the divider equation gives:
The CS51033 will operate with almost any value of
inductor. With larger inductors the ripple current is reduced
and the regulator will remain in a continuous conduction
mode for lower values of load current. A smaller inductor
will result in larger ripple current. The core must not saturate
with the maximum expected current, here given by:
OUT 1.0 1.0 k1.5 V 200 V1.25
1.25
R1 R2
6) Divider Bypass Capacitor CRR
I
I
IMAX OUT
3.0 A 0.6 A2.0 3.3 A
2.0
Since the feedback resistors divide the output voltage by
a factor of 4.0, i.e. 5.0 V/1.25 V= 4.0, it follows that the
output ripple is also divided by four. This would require that
the output ripple be at least 60 mV (4.0 × 15 mV) to trip the
feedback comparator. We use a capacitor CRR to act as an
AC short so that the output ripple is not attenuated by the
divider network. The ripple voltage frequency is equal to the
switching frequency so we choose CRR so that:
4) Output Capacitor
The output capacitor limits the output ripple voltage. The
CS51033 needs a maximum of 15 mV of output ripple for
the feedback comparator to change state. If we assume that
all the inductor ripple current flows through the output
capacitor and that it is an ideal capacitor (i.e. zero ESR), the
minimum capacitance needed to limit the output ripple to
50 mV peak to peak is given by:
CO XC 1.0
2fC
is negligible at the switching frequency.
In this case FSW is 200 kHz if we allow XC = 3.0 Ω then:
I
8.0 FSW V
C 1.0 0.265 F
2f3
0.6 A
11.4 F
8.0 (200 103 Hz) (33 103 V)
The minimum ESR needed to limit the output voltage
ripple to 50 mV peak to peak is:
7) Soft Start and Fault Timing Capacitor CS
CS performs several important functions. First it provides
a dead time for load transients so that the IC does not enter
a fault mode every time the load changes abruptly. Secondly
it disables the fault circuitry during startup, it also provides
Soft Start by clamping the reference voltage during startup
to rise slowly and finally it controls the hiccup short circuit
protection circuitry. This function reduces the PFET’s duty
cycle to 2.0% of the CS period.
The most important consideration in calculating CS is that
it’s voltage does not reach 2.5 V (the voltage at which the
fault detect circuitry is enabled) before VFB reaches 1.15 V
otherwise the power supply will never start.
If the VFB pin reaches 1.15 V, the fault timing comparator
will discharge CS and the supply will not start. For the VFB
voltage to reach 1.15 V the output voltage must be at least
4 × 1.15 = 4.6 V.
3
ESR V 50 10
55 m
0.6 A
I
The output capacitor should be chosen so that its ESR is
at least half of the calculated value and the capacitance is at
least ten times the calculated value. It is often advisable to
use several capacitors in parallel to reduce ESR.
Low impedance aluminum electrolytic, tantalum or
organic semiconductor capacitors are a good choice for an
output capacitor. Low impedance aluminum are the
cheapest but are not available in surface mount at present.
Solid tantalum chip capacitors are available from a number
of suppliers and offer the best choice for surface mount
applications. The capacitor working voltage should be
greater than the output voltage in all cases.
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7
CS51033
If we choose an arbitrary startup time of 200 µs, we
calculate the value of CS from:
A larger value of CS will increase the fault time out time
but will also increase the Soft Start time.
T CS 2.5 V
ICHARGE
CS(MIN) 8) Input Capacitor
The input capacitor reduces the peak currents drawn from
the input supply and reduces the noise and ripple voltage on
the VCC and VC pins. This capacitor must also ensure that
the VCC remains above the UVLO voltage in the event of an
output short circuit. CIN should be a low ESR capacitor of
at least 100 µF. A ceramic surface mount capacitor should
also be connected between VCC and ground to prevent
spikes.
200 s 264 A
0.02 F
2.5 V
Use 0.1 µf.
The fault time out time is the sum of the slow discharge
time the fast discharge time and the recharge time and is
obviously dominated by the slow discharge time.
The first parameter is the slow discharge time, it is the time
for the CS capacitor to discharge from 2.4 V to 1.5 V and is
given by:
TSLOWDISCHARGE 9) MOSFET Selection
The CS51033 drives a P–channel MOSFET. The VGATE
pin swings from GND to VC. The type of PFET used
depends on the operating conditions but for input voltages
below 7.0 V a logic level FET should be used.
Choose a PFET with a continuous drain current (ID) rating
greater than the maximum output current. RDS(ON) should
be less than
CS (2.4 V 1.5 V)
IDISCHARGE
where IDISCHARGE is 6.0 µA typical.
TSLOWDISCHARGE CS 1.5 V 105
RDS The fast discharge time occurs when a fault is first
detected. The CS capacitor is discharged from 2.5 V to 2.4 V.
The Gate–to–Source voltage VGS and the Drain–to
Source Breakdown Voltage should be chosen based on the
input supply voltage.
The power dissipation due to the conduction losses is
given by:
CS (2.5 V 2.4 V)
TFASTDISCHARGE IFASTDISCHARGE
where IFASTDISCHARGE is 66 µA typical.
TFASTDISCHARGE CS 1515
PD IOUT2 RDS(ON) D
The recharge time is the time for CS to charge from 1.5 V
to 2.5 V.
TCHARGE 0.6 V
167 m
IOUT(MAX)
The power dissipation due to the switching losses is given
by:
CS (2.5 V 1.5 V)
ICHARGE
PD 0.5 VIN IOUT (TRr TF) FSW
where ICHARGE is 264 µA typical.
where TR = Rise Time and TF = Fall Time.
TCHARGE CS 3787
10) Diode Selection
The flyback or catch diode should be a Schottky diode
because of it’s fast switching ability and low forward voltage
drop. The current rating must be at least equal to the
maximum output current. The breakdown voltage should be
at least 20 V for this 12 V application.
The diode power dissipation is given by:
The fault time out time is given by:
TFAULT CS (3787 1515 1.5 105)
TFAULT CS (1.55 105)
For this circuit
PD IOUT VD (1.0 DMIN)
TFAULT 0.1 106 1.55 105 0.0155
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8
CS51033
ORDERING INFORMATION
Operating
Temperature Range
Package
Shipping
CS51033ED8
–40°C < TA < 85°C
SO–8
95 Units/Rail
CS51033EDR8
–40°C < TA < 85°C
SO–8
2500 Tape & Reel
CS51033EN8
–40°C < TA < 85°C
DIP–8
50 Units/Rail
CS51033GD8
0°C < TA < 70°C
SO–8
95 Units/Rail
CS51033GDR8
0°C < TA < 70°C
SO–8
2500 Tape & Reel
CS51033GN8
0°C < TA < 70°C
DIP–8
50 Units/Rail
Device
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9
CS51033
PACKAGE DIMENSIONS
SO–8
D SUFFIX
CASE 751–07
ISSUE V
–X–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
A
8
5
0.25 (0.010)
S
B
1
M
Y
M
4
K
–Y–
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 SEATING
PLANE
–Z–
0.10 (0.004)
H
D
0.25 (0.010)
Z Y
M
X
S
M
J
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0
8
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0
8
0.010
0.020
0.228
0.244
DIP–8
N SUFFIX
CASE 626–05
ISSUE L
8
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5
–B–
1
4
DIM
A
B
C
D
F
G
H
J
K
L
M
N
F
–A–
NOTE 2
L
C
J
–T–
N
SEATING
PLANE
D
H
MILLIMETERS
MIN
MAX
9.40
10.16
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.78
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC
--10
0.76
1.01
M
K
G
0.13 (0.005)
M
T A
M
B
M
PACKAGE THERMAL DATA
Parameter
SO–8
DIP–8
Unit
RΘJC
Typical
45
52
°C/W
RΘJA
Typical
165
100
°C/W
http://onsemi.com
10
INCHES
MIN
MAX
0.370
0.400
0.240
0.260
0.155
0.175
0.015
0.020
0.040
0.070
0.100 BSC
0.030
0.050
0.008
0.012
0.115
0.135
0.300 BSC
--10
0.030
0.040
CS51033
Notes
http://onsemi.com
11
CS51033
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CS51033/D