CHERRY CS51033YD8

CS51033
CS51033
Fast PFET Buck Controller
Does Not Require Compensation
Features
Description
The CS51033 is a switching controller for use in DC-DC converters.
It can be used in the buck topology
with a minimum number of external components. The CS51033 consists of a 1.0A power driver for controlling the gate of a discrete Pchannel transistor, fixed frequency
oscillator, short circuit protection
timer, programmable soft start, precision reference, fast output voltage
monitoring comparator, and output
stage driver logic with latch.
The high frequency oscillator
allows the use of small inductors
and output capacitors, minimizing
PC board area and systems cost.
The programmable soft start
reduces current surges at start up.
The short circuit protection timer
significantly reduces the PFET duty
cycle to approximately 1/30 of its
normal cycle during short circuit
conditions.
■ 1A Totem Pole Output
Driver
The CS51033 is available in 8L SO
and 8L PDIP plastic packages.
■ Programmable Soft Start
■ High Speed Oscillator
(700kHz max)
■ No Stability
Compensation Required
■ Lossless Short Circuit
Protection
■ 2% Precision Reference
Typical Application Diagram
3.3VIN
D2
1N4148
CIN
100µF
RC
10Ω
C1
0.1µF
Package Options
D4
1N5818
D3
1N4148
8 Lead SO Narrow & PDIP
VGATE
RG
10Ω
VC
VCC
VGATE
IRF 7404
U1
CS51033
0.01µF
VFB
COSC
4.7µH
C2
1µF
C3
100µF
COSC
150pF
PGnd
CS
COSC
VCC
Gnd
VFB
1.5VOUT
@3Amp
100
CS
Gnd
VC
1
.1µF
PGnd
CS
0.1µF
D1
1N5821
C0
100µF
C4
0.1µF
100µF
Gnd
Gnd
RA
1.5k
RB
300
NOTE: Capacitors C2, C3 and C4 are low ESR tantalum
caps used for noise reduction.
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: info@cherry-semi.com
Web Site: www.cherry-semi.com
Rev. 2/13/98
1
A
®
Company
CS51033
Absolute Maximum Ratings
Power Supply Voltage, VCC ..........................................................................................................................................................5V
Driver Supply Voltage, VC ..........................................................................................................................................................20V
Driver Output Voltage, VGATE ...................................................................................................................................................20V
COSC, CS, VFB (Logic Pins) ............................................................................................................................................................5V
Peak Output Current ................................................................................................................................................................. 1.0A
Steady State Output Current ................................................................................................................................................200mA
Operating Junction Temperature, TJ ..................................................................................................................................... 150°C
Storage Temperature Range, TS ...................................................................................................................................-65 to 150°C
ESD (Human Body Model).........................................................................................................................................................2kV
Lead Temperature Soldering
Wave Solder (through hole styles only) .....................................................................................10 sec. max, 260°C peak
Reflow (SMD styles only) ......................................................................................60 sec. max above 183°C, 230°C peak
Electrical Characteristics: Specifications apply for 3.135 ≤ VCC ≤ 3.465V, 3V ≤ VC ≤ 16V,
-40°C ≤ TA ≤ 125°C, -40°C ≤ TJ ≤ 125°C, unless otherwise specified.
PARAMETER
TEST CONDITIONS
■ Oscillator
Frequency
Charge Current
Discharge Current
Maximum Duty Cycle
VFB = 1.2V
COSC = 470pF
1.4V < VCOSC < 2V
2.7V > VCOSC > 2V
1 – (tOFF/tON)
■ Short Circuit Timer
Charge Current
Fast Discharge Current
Slow Discharge Current
Start Fault Inhibit Time
Valid Fault Time
GATE Inhibit Time
Duty Cycle
VFB = 1.0V; CS = 0.1µF; VCOSC = 2V
1V < VCS < 2V
2.55V > VCS > 2.4V
2.4V > VCS > 1.5V
■ CS Comparator
Fault Enable CS Voltage
Max. CS Voltage
Fault Detect Voltage
Fault Inhibit Voltage
Hold Off Release Voltage
Regulator Threshold
Voltage Clamp
VFB = 1V
■ VFB Comparator
Regulator Threshold Voltage
Fault Threshold Voltage
Threshold Line Regulation
Input Bias Current
Voltage Tracking
MIN
160
2.6V > VCS > 2.4V
2.4V > VCS > 1.5V
VFB = 1.5V
VCS when GATE goes high
Minimum VCS
VFB = 0V
VCS = 1.5V
VCOSC = VCS = 2V
TJ = 25°C (Note 1)
TJ = -40 to 125°C
TJ = 25°C (Note 1)
TJ = -40 to 125°C
3.135V ≤ VCC ≤ 3.465
VFB = 0V
(Regulator Threshold Voltage Fault Threshold Voltage)
Input Hysteresis Voltage
2
TYP
MAX
UNIT
240
80.0
200
110
660
83.3
kHz
µA
µA
%
175
40
4
0.70
0.2
9
2.5
264
66
6
0.85
0.3
15
3.1
325
80
10
1.40
0.45
23
4.6
µA
µA
µA
ms
ms
ms
%
0.4
0.725
2.5
2.6
2.4
1.5
0.7
0.866
1.0
1.035
V
V
V
V
V
V
1.250
1.250
1.15
1.15
6
1
100
1.275
1.290
1.17
1.19
15
4
120
V
V
V
V
mV
µA
mV
4
20
mV
1.225
1.210
1.12
1.10
70
PARAMETER
■ Power Stage
GATE DC Low Saturation
Voltage
GATE DC High Saturation
Voltage
Rise Time
Fall Time
■ Current Drain
ICC
IC
TEST CONDITIONS
MIN
TYP
UNIT
VC = 10V; VFB = 1.2V
VCOSC = 1V; 200mA Sink
1.2
1.5
V
VCOSC = 2.7V; 200mA Source; VC = VGATE
1.5
2.1
V
CGATE = 1nF; 1.5V < VGATE < 9V
CGATE = 1nF; 9V > VGATE > 1.5V
25
25
60
60
ns
ns
3.135V < VCC < 3.465V, Gate switching
3V < VC < 16V, Gate non-switching
3.5
2.7
6.0
4.0
mA
mA
Note1: Guaranteed by design not 100% tested in production.
Package Pin Description
PACKAGE PIN #
MAX
PIN SYMBOL
FUNCTION
8L SO Narrow & PDIP
1
VGATE
Driver pin to gate of external PFET.
2
PGnd
Output power stage ground connection.
3
COSC
Oscillator frequency programming capacitor.
4
Gnd
Logic ground.
5
VFB
Feedback voltage input.
6
VCC
Logic supply voltage.
7
CS
Soft start and fault timing capacitor.
8
VC
Driver supply voltage.
3
CS51033
Electrical Characteristics: Specifications apply for 3.135 ≤ VCC ≤ 3.465V, 3V ≤ VC ≤ 16V,
-40°C ≤ TJ ≤ 125°C, unless otherwise specified.
CS51033
Block Diagram
VC
VCC
RG
IC
Oscillator
Comparator
A1
G1
COSC
7IC
VGATE
Flip-Flop
VGATE
Q
R
PGnd
F2
G2
S
VFB
Comparator
Q
VFB
A6
+
2.5V
1.5V
VCC
+
1.25V
0.7V
Hold
Off
Comp
VCC
-
Fault
Comp
+ 1.15V
G4
CS Charge
Sense
Comparator
G3
IT
R
-
+
CS
IT
55
A4
CS
Comparator
A2
2.3V
Q
F1
IT
5
1.5V
G5
2.5V
S
Q
Slow Discharge
Flip-Flop
2.4V
A3
+
Slow Discharge
Comparator
Gnd
Figure 1: Block Diagram for CS51033
Circuit Description
At startup, the voltage on all pins is zero. As VCC rises, the
VC voltage along with the internal resistor RG keeps the
PFET off. As VCC and VC continue to rise, the oscillator
capacitor (COSC ) and the Soft start/Fault Timing capacitor
(CS) charges via internal current sources. COSC gets charged
by the current source IC and CS gets charged by the IT
source combination described by:
Theory of Operation
Control Scheme
The CS51033 monitors the output voltage to determine
when to turn on the PFET. If VFB falls below the internal reference voltage of 1.25V during the oscillator’s charge cycle,
the PFET is turned on and remains on for the duration of the
charge time. The PFET gets turned off and remains off during the oscillator’s discharge cycle time with the maximum
duty cycle to 80%. It requires 7mV typical, and 20mV maximum ripple on the VFB pin is required to operate. This
method of control does not require any loop stability compensation.
ICS = IT -
(
IT IT
+
55
5
)
The internal Holdoff Comparator ensures that the external
PFET is off until VCS > 0.7V preventing the GATE flip-flop
(F2) from being set. This allows the oscillator to reach its
operating frequency before enabling the drive output. Soft
start is obtained by clamping the VFB comparator’s (A6) reference input to approximately 1/2 of the voltage at the CS
pin during startup, permitting the control loop and the output voltage to slowly increase. Once the CS pin charges
above the Holdoff Comparator trip point of 0.7V, the low
Startup
The CS51033 has an externally programmable soft start feature that allows the output voltage to come up slowly, preventing voltage overshoot on the output.
4
feedback to the VFB Comparator sets the GATE flip-flop during COSC ’s charge cycle. Once the GATE flip-flop is set,
VGATE goes low and turns on the PFET. When VCS exceeds
2.4V, the CS charge sense comparator (A4) sets the VFB comparator reference to 1.25V completing the startup cycle.
Buck Regulator Operation
L
Q1
VIN
R1
CIN
Lossless Short Circuit Protection
D1
The CS51033 has “Lossless” short circuit protection since
there is no current sense resistor required. When the voltage
at the CS pin (the fault timing capacitor voltage ) reaches
2.5V, the fault timing circuitry is enabled. During normal
operation the CS voltage is 2.6V. During a short circuit condition or a transient condition, the output voltage moves
lower and the voltage at VFB drops. If VFB drops below
1.15V, the output of the fault comparator goes high and the
CS51033 goes into a fast discharge mode. The fault timing
capacitor, CS, discharges to 2.4V. If the VFB voltage is still
below 1.15V when the CS pin reaches 2.4V, a valid fault condition has been detected. The slow discharge comparator
output goes high and enables gate G5 which sets the slow
discharge flip flop. The Vgate flip flop resets and the output
switch is turned off. The fault timing capacitor is slowly discharged to 1.5V. The CS51033 then enters a normal startup
routine. If the fault is still present when the fault timing
capacitor voltage reaches 2.5V, the fast and slow discharge
cycles repeat as shown in figure 2.
CO
RLOAD
R2
Control
Feedback
Figure 3. Buck regulator block diagram.
A block diagram of a typical buck regulator is shown in
Figure 3. If we assume that the output transistor is initially
off, and the system is in discontinuous operation, the inductor current IL is zero and the output voltage is at its nominal
value. The current drawn by the load is supplied by the output capacitor CO . When the voltage across CO drops below
the threshold established by the feedback resistors R1 and
R2 and the reference voltage VREF, the power transistor Q1
switches on and current flows through the inductor to the
output. The inductor current rises at a rate determined by
(VIN-VOUT)/Load. The duty cycle (or “on” time) for the
CS51033 is limited to 80%. If the output voltage remains
higher than nominal during the entire COSC charge time, the
Q1 does not turn on, skipping the pulse.
If the VFB voltage is above 1.15V when CS reaches 2.4V a
fault condition is not detected, normal operation resumes
and CS charges back to 2.6V. This reduces the chance of
erroneously detecting a load transient as a fault condition.
CHARGE PUMP CIRCUIT
2.6V
VCS
CS51033
Circuit Description: continued
S2
2.4V
S1
S2
2.5V
S2
S3
S1
S1
S3
(Refer to the CS51033 Application Diagram)
S3
S3
1.5V
0V
An external charge pump circuit is necessary when the input
voltage is below 5V to ensure that there is sufficient gate
drive voltage for the external FET. When VIN is applied,
capacitors C1 and C2 will be charged to a diodes drop below
VIN via diodes D2 and D4, respectively. When the PFET
turns on, its drain voltage will be approximately equal to
VIN. Since the voltage across C1 can not change instantaneously, D2 is reverse biased and the anode voltage rises to
approximately 2*3.3V-VD2. C1 transfers some of its stored
charge C2 via D3. After several cycles there is sufficient gate
drive voltage.
0V
TSTART
START
td1
NORMAL OPERATION
tFAULT
tRESTART td2
tFAULT
FAULT
VGATE
1.25V
1.15V
VFB
Figure 2. Voltage on start capacitor (VGS ), the gate (VGATE ), and in the
feedback loop (VFB), during startup, normal and fault conditions.
Applications Information
to 80% min. it is best to estimate the duty cycle for the various input conditions to see that the design will work over
the complete operating range.
The duty cycle for a buck regulator operating in a continuous conduction mode is given by:
Designing a Power Supply with the CS51033
Specifications
VIN = 3.3V +/- 10% (i.e. 3.63V max., 2.97V min.)
VOUT = 1.5V +/- 2%
IOUT = 0.3A to 3A
Output ripple voltage < 33mV.
FSW = 200kHz.
VOUT + VD
D = VIN - VSAT
Where VSAT is Rdson × IOUT Max.
1) Duty Cycle Estimates
In this case we can assume that VD = 0.6V and VSAT = 0.6V
so the equation reduces to:
Since the maximum duty cycle, D, of the CS51033 is limited
5
CS51033
Applications Information: continued
to 50mV peak to peak is:
VOUT
D=
∆V 50 × 10-3
ESR = ∆I =
= 55mΩ
0.6A
VIN
From this, the maximum duty cycle DMAX is 53%, this
occurs when VIN is at its minimum while the minimum
duty cycle DMIN is 0.35%.
The output capacitor should be chosen so that its ESR is at
least half of the calculated value and the capacitance is at
least ten times the calculated value. It is often advisable to
use several capacitors in parallel to reduce the ESR.
Low impedance aluminum electrolytic, tantalum or organic
semiconductor capacitors are a good choice for an output
capacitor. Low impedance aluminum are the cheapest but
are not available in surface mount at present. Solid tantalum
chip capacitors are available from a number of suppliers
and offer the best choice for surface mount applications. The
capacitor working voltage should be greater than the output
voltage in all cases.
2) Switching Frequency and on and off time calculations.
FSW= 200KHz. The switching frequency is determined by
COSC, whose value is determined by :
95
COSC =
Fsw ×
( ( )(
1-
FSW
3 × 10 6
T=
1
FSW
-
30 × 10
3
FSW
))
2
≅ 470pF
5) VFB Divider
= 5µs
VOUT = 1.25V
TON(MAX) = 5µs × 0.53 = 2.65µs
TON(MIN) = 5µs × 0.35 = 1.75µs
TOFF(MAX) = 5µs − 0.7µs = 4.3µs
Pick the inductor value to maintain continuous mode operation down to 0.3 Amps.
The ripple current ∆I = 2 × IOUT(MIN) = 2 × 0.3A = 0.6A.
=
2.1V × 4.3µs
0.6A
≅ 15µH
R1 = R2
The CS51033 will operate with almost any value of inductor.
With larger inductors the ripple current is reduced and the
regulator will remain in a continuous conduction mode for
lower values of load current. A smaller inductor will result
in larger ripple current. The core must not saturate with the
maximum expected current, here given by:
IMAX =
8 × FSW × ∆V
)
R1
+1
R2
(
)
(
1.5V
1.25
)
= 200Ω
Since the feedback resistors divide the output voltage by a
factor of 4, i.e. 5V/1.25V= 4 it follows that the output ripple
is also divided by four. This would require that the output
ripple be at least 60mV (4 × 15mV) to trip the feedback compactor. We use a capacitor Crr to act as an ac short so that
the output ripple is not attenuated by the divider network.
The ripple voltage frequency is equal to the switching frequency so we choose Crr so that:
IOUT + ∆I
= 3A + 0.6A/2 = 3.3A
2
=
(
6) Divider bypass capacitor Crr
XC =
The output capacitor limits the output ripple voltage. The
CS51033 needs a maximum of 15mV of output ripple for the
feedback comparator to change state. If we assume that all
the inductor ripple current flows through the output capacitor and that it is an ideal capacitor (i.e. zero ESR), the minimum capacitance needed to limit the output ripple to 50mV
peak to peak is given by:
CO =
= 1.25V
VOUT
-1 = 1KΩ
1.25
4) Output Capacitor
∆I
)
Rearranging the divider equation gives:
VOUT + VD × ΤOFF(MAX)
∆I
R1 + R2
R2
The input bias current to the comparator is 4µA. The resistor
divider current should be considerably higher than this to
ensure that there is sufficient bias current. If we choose the
divider current to be at least 250 times the bias current this
gives a divider current of 1mA and simplifies the calculations.
1.5V = R1+R2 = 1.5KΩ
1mA
Let R2 = 1K
3) Inductor selection
LMIN =
(
1
2πfC
is negligible at the switching frequency.
In this case FSW is 200kHz if we allow XC = 3Ω then:
C=
1
≅ 0.265µF
2πf3
7) Soft start and Fault timing capacitor CS.
CS performs several important functions. First it provides a
dead time for load transients so that the IC does not enter a
fault mode every time the load changes abruptly. Secondly
it disables the fault circuitry during startup, it also provides
soft start by clamping the reference voltage during startup
0.6A
≅ 11.4µF
8 × (200 × 103 Hz) × (33 × 10-3V)
The minimum ESR needed to limit the output voltage ripple
6
to rise slowly and finally it controls the Hiccup short circuit
protection circuitry. This function reduces the PFET's duty
cycle to 2% of the CS period.
For this circuit
TFAULT = 0.1 × 10-6 × 1.55 × 105 = 0.0155
The most important consideration in calculating CS is that
it’s voltage does not reach 2.5V (the voltage at which the
fault detect circuitry is enabled) before VFB reaches 1.15V
otherwise the power supply will never start.
A larger value of CS will increase the fault time out time but
will also increase the soft start time.
If the VFB pin reaches 1.15V the fault timing comparator will
discharge CS and the supply will not start. For the VFB voltage to reach 1.15V the output voltage must be at least 4 ×
1.15 = 4.6V.
If we choose an arbitrary startup time of 200µs we calculate
the value of CS from:
The input capacitor reduces the peak currents drawn from
the input supply and reduces the noise and ripple voltage
on the VCC and VC pins. This capacitor must also ensure
that the VCC remains above the UVLO voltage in the event
of an output short circuit. CIN should be a low ESR capacitor
of at least 100µf. A ceramic surface mount capacitor should
also be connected between VCC and ground to prevent
spikes.
8) Input Capacitor.
CS × 2.5V
T = ICHARGE
9) MOSFET Selection
200µs × 264µA
CS(min) =
= 0.02µF
2.5V
The CS51033 drive a P-channel MOSFET. The VGATE pin
swings from Gnd to VC. The type of PFET used depends on
the operating conditions but for input voltages below 7V a
logic level FET should be used.
Choose a PFET with a continuous drain current (Id) rating
greater than the maximum output current. RDS(on) should be
less than
Use 0.1µf.
The fault time out time is the sum of the slow discharge
time the fast discharge time and the recharge time and is
obviously dominated by the slow discharge time.
The first parameter is the slow discharge time, it is the time
for the CS capacitor to discharge from 2.4V to 1.5V and is
given by:
CS × (2.4V-1.5V)
TSLOWDISCHARGE =
RDS < =
The Gate-to-Source voltage VGS and the Drain-to Source
Breakdown Voltage should be chosen based on the input
supply voltage.
ΙDISCHARGE
Where IDISCHARGE is 6µA typical.
TSLOWDISCHARGE = CS × 1.5V × 105
The power dissipation due to the conduction losses is given
by:
PD = OUT2 × RDS(on) × D
The fast discharge time occurs when a fault is first detected.
The CS capacitor is discharged from 2.5V to 2.4V.
TFASTDISCHARGE =
0.6V
167mΩ
IOUT(max)
CS × (2.5V - 2.4V)
ΙFASTDISCHARGE
The power dissipation due to the switching losses is given
by:
PD = 0.5 × VIN × IOUT × (TRr + TF) × FSW
Where IFASTDISCHARGE is 66µA typical.
TFASTDISCHARGE = CS × 1515
Where tr =Rise Time and tf= Fall Time.
The recharge time is the time for CS to charge from 1.5V to
2.5V.
TCHARGE =
10) Diode Selection.
CS × (2.5V-1.5V)
ΙCHARGE
The flyback or catch diode should be a Schottky diode
because of it’s fast switching ability and low forward voltage drop. The current rating must be at least equal to the
maximum output current. The breakdown voltage should
be at least 20V for this 12V application.
The diode power dissipation is given by:
Where ICHARGE is 264µA typical.
TCHARGE = CS × 3787
The fault time out time is given by:
PD = IOUT × VD × (1-DMIN)
TFAULT = CS × (3787 + 1515 + 1.5 × 105)
TFAULT = CS × 1.55 × 105
7
CS51033
Applications Information: continued
CS51033
Package Specification
PACKAGE THERMAL DATA
PACKAGE DIMENSIONS IN mm (INCHES)
D
Lead Count
8L SO Narrow
8L PDIP
Metric
Max
Min
5.00
4.80
10.16
9.02
Thermal Data
RΘJC
typ
RΘJA
typ
English
Max Min
.197 .189
.400 .355
8L SO Narrow
45
165
8L PDIP
52
100
˚C/W
˚C/W
Surface Mount Narrow Body (D); 150 mil wide
4.00 (.157)
3.80 (.150)
6.20 (.244)
5.80 (.228)
0.51 (.020)
0.33 (.013)
1.27 (.050) BSC
1.75 (.069) MAX
1.57 (.062)
1.37 (.054)
1.27 (.050)
0.40 (.016)
0.25 (.010)
0.19 (.008)
D
0.25 (0.10)
0.10 (.004)
REF: JEDEC MS-012
Plastic DIP (N); 300 mil wide
7.11 (.280)
6.10 (.240)
8.26 (.325)
7.62 (.300)
1.77 (.070)
1.14 (.045)
2.54 (.100) BSC
3.68 (.145)
2.92 (.115)
.356 (.014)
.203 (.008)
0.39 (.015)
MIN.
.558 (.022)
.356 (.014)
REF: JEDEC MS-001
D
Some 8 and 16 lead
packages may have
1/2 lead at the end
of the package.
All specs are the same.
Ordering Information
Part Number
CS51033YD8
CS51033YDR8
CS51033YN8
Rev. 2/13/98
Description
8L SO Narrow
8L SO Narrow (tape & reel)
8L PDIP
Cherry Semiconductor Corporation reserves the right to
make changes to the specifications without notice. Please
contact Cherry Semiconductor Corporation for the latest
available information.
8
© 1999 Cherry Semiconductor Corporation