ETC CS51227/D

CS51227
Enhanced Voltage Mode
PWM Controller
The CS51227 is a fixed frequency, single output PWM controller
using feed forward voltage mode control. Feed forward control
provides superior line regulation and line transient response. This
PWM controller has been optimized for high frequency primary side
control operation. It has undervoltage lockout with 4.7 V start up
voltage and 75 µA start up current. One external capacitor can
program the switching frequency up to 1.0 MHz. The protection
features include pulse–by–pulse current limit with leading edge
blanking and thermal shutdown. The CS51227 is available in 8 lead
SO narrow surface mount package.
SO–8
D SUFFIX
CASE 751
8
1
PIN CONNECTIONS AND
MARKING DIAGRAM
GATE
ISENSE
FF
CT
A
WL, L
YY, Y
WW, W
1
8
51227
ALYWX
Features
1.0 MHz Frequency Capability
4.7 V Start–Up Voltage
Fixed Frequency Voltage Mode Operation with Feed Forward
Undervoltage Lockout
75 µA Start–Up Current
Thermal Shutdown
1.0 A Sink/Source Gate Drive
Pulse–By–Pulse Current Limit with Leading Edge Blanking
50 ns GATE Rise and Fall Time (1.0 nF Load)
Maximum Duty Cycle Over 85%
Programmable Volt–Second Clamp
•
•
•
•
•
•
•
•
•
•
•
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VCC
GND
COMP
VFB
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
 Semiconductor Components Industries, LLC, 2001
February, 2001 – Rev. 6
1
Device
Package
Shipping
CS51227ED8
SO–8
95 Units/Rail
CS51227EDR8
SO–8
2500 Tape & Reel
Publication Order Number:
CS51227/D
CS51227
5.0 V
6.8 µH
12 V/ 2.0 A
B320DICT
0.1 µF
0.1
FS70VSJ–03
ISENSE
0.025
FF
1.0 k
VCC
CS51227
GATE
GND
+
51 k
2700 pF
CT
VFB
5.6 nF
9.1 k
+
9.31 k
22 µF × 2
1.0 nF
22 µF × 4
COMP
300
100 pF
330 pF
110
GND
GND
Figure 1. Applications Diagram, 5.0 V to 12 V/2.0 A Boost Converter
ABSOLUTE MAXIMUM RATINGS*
Rating
Operating Junction Temperature, TJ
Storage Temperature Range, TS
ESD Susceptibility (Human Body Model)
Lead Temperature Soldering:
Reflow: (SMD styles only) (Note 1.)
Value
Unit
150
°C
–65 to +150
°C
2.0
kV
230 peak
°C
1. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.
ABSOLUTE MAXIMUM RATINGS
Pin Name
Pin Symbol
VMAX
VMIN
ISOURCE
ISINK
Gate Drive Output
GATE
20 V
–0.3 V
1.0 A Peak, 200 mA DC
1.0 A Peak, 200 mA DC
Current Sense Input
ISENSE
6.0 V
–0.3 V
1.0 mA
1.0 mA
Timing Capacitor
CT
6.0 V
–0.3 V
1.0 mA
10 mA
Feed Forward
FF
6.0 V
–0.3 V
1.0 mA
25 mA
Error Amp Output
COMP
6.0 V
–0.3 V
10 mA
20 mA
Feedback Voltage
VFB
6.0 V
–0.3 V
1.0 mA
1.0 mA
Power Supply
VCC
20 V
–0.3 V
10 mA
1.0 A Peak, 200 mA DC
Ground
GND
N/A
N/A
1.0 A Peak, 200 mA DC
N/A
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CS51227
ELECTRICAL CHARACTERISTICS: (–40°C < TA < 85°C, –40°C < TJ < 125°C, 4.7 V < VCC < 18 V
CT = 390 pF; unless otherwise specified.)
Test Conditions
Min
Typ
Max
Unit
Start Threshold
–
4.4
4.5
4.7
V
Stop Threshold
–
3.2
3.8
4.2
V
300
700
1400
mV
Characteristic
Start/Stop Voltages
Hysteresis
Start – Stop
ICC @ Startup
VCC < UVL Start Threshold
–
38
75
µA
No Load
–
10
16
mA
0.27
0.30
0.33
V
Supply Current
ICC Operating
Overcurrent Protection
Overcurrent Threshold
Ramp ISENSE
ISENSE to GATE Delay
VFB = 0.5 V (no blanking)
–
60
125
ns
Reference Voltage
VFB connected to COMP
1.234
1.263
1.285
V
VFB Input Current
VFB = 1.25 V
–
1.3
2.0
µA
Open Loop Gain
Note 2.
60
90
–
dB
Unity Gain Bandwidth
Note 2.
1.5
2.5
–
MHz
COMP Sink Current
COMP = 1.4 V, VFB = 1.45 V
3.0
12
32
mA
COMP Source Current
COMP = 1.4 V, VFB = 1.15 V
1.0
1.7
2.4
mA
COMP High Voltage
VFB = 1.15 V
2.8
3.1
3.4
V
COMP Low Voltage
VFB = 1.45 V
75
150
300
mV
PSRR
Freq = 120 Hz, Note 2.
60
85
–
dB
Error Amp
Oscillator
Frequency Accuracy
–
200
235
270
kHz
Max Duty Cycle
–
85
90
95
%
1.99
2.05
2.11
V
0.90
0.95
1.00
V
0.90
0.95
1.00
V
Peak Voltage
Note 2.
Valley Clamp Voltage
Valley Voltage
–
Note 2.
Discharge Current
–
0.85
1.00
1.15
mA
Charge Current
–
95
115
135
µA
Gate Driver
High Saturation Voltage
VCC – VGATE, VCC = 10 V, ISOURCE = 150 mA
–
1.5
2.0
V
Low Saturation Voltage
VGATE, ISINK = 150 mA
–
1.2
1.5
V
11
13.5
16
V
High Voltage Clamp
–
Output UVL Leakage
VGATE = 0 V
–
1.0
50
µA
Rise Time
1.0 nF Load, VCC = 18 V, 1.0 V < VO < 9.0 V
–
32
50
ns
Fall Time
1.0 nF Load, VCC = 18 V, 9.0 V < VO < 1.0 V
–
25
50
ns
Max GATE Voltage @ UVL
ILOAD = 100 µA
0.4
0.7
1.5
V
2. Guaranteed by design, not 100% tested in production.
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CS51227
ELECTRICAL CHARACTERISTICS: (continued) (–40°C < TA < 85°C, –40°C < TJ < 125°C, 4.7 V < VCC < 18 V
CT = 390 pF; unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
–
0.3
0.7
V
2.0
16
30
mA
50
75
125
ns
1.7
1.8
1.9
V
50
150
250
ns
VFB < 1.0 V
2.8
3.0
3.3
V
Thermal Shutdown
Note 3.
125
150
180
°C
Thermal Hysteresis
Note 3.
5.0
10
15
°C
Feed Forward (FF)
Discharge Voltage
IFF = 2.0 mA
Discharge Current
FF = 1.0 V
FF to GATE Delay
FF Max VOltage
–
VFB = 1.15 V
Blanking
Blanking Time
COMP Blanking Disable Threshold
–
Thermal Shutdown
3. Guaranteed by design, not 100% tested in production.
PACKAGE PIN DESCRIPTION
PACKAGE LEAD #
SO–8
LEAD SYMBOL
1
GATE
External power switch driver with 1.0 A peak capability. Rail–to–rail output
occurs when the capacitive load is between 470 pF and 10 nF.
2
ISENSE
Current sense comparator input.
3
FF
PWM ramp.
4
CT
Timing capacitor CT determines oscillator frequency.
5
VFB
Feedback voltage input. Connected to the error amplifier inverting input.
6
COMP
7
GND
Ground.
8
VCC
Supply voltage.
FUNCTION
Error amplifier output.
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4
CS51227
VCC
4.7 – 18 V
3.3 V
VREF
Thermal
Shutdown
VREF OK
+
+
VREF = 3.3 V
–
3.1 V
Low Sat
Gate Driver
–
+
–
S
UV Lockout
Start/Stop
G1
Q
GATE
13.5 V
G2
PWM
COMP
R
GND
Q
OSC
–
–
+
CT
1.263 V EAMP
+
3.0 V
+
–
VFB
–
1.8 V
Blank
Disable
COMP
FF
FF Discharge
+
ILIM
–
0.3 V
150 ns
Blank
ISENSE
Figure 2. Block Diagram
THEORY OF APPLICATION
VIN
THEORY OF OPERATION
VOUT
Power Stage
Feed Forward Voltage Mode Control
GATE
Latch & Driver
R
Feedback
Network
PWM
Error
Amplifier
C
FB
+
FF
COMP
–
In conventional voltage mode control, the ramp signal is
fixed and often generated by the oscillator. The output
voltage is the only feedback path for regulation against load
and line variations. Feed forward voltage mode uses the
ramp signal driven by the input line, as shown in Figure 3.
Therefore, the ramp signal responds immediately to line
change. At the start of each switch cycle, the FF pin
capacitor is charged up through a resistor connected to the
input line. Meanwhile, the Gate output is turned on to drive
an external power switching device. When the FF pin
voltage reaches the error amplifier output VCOMP , the PWM
comparator turns off the Gate and the FF pin capacitor is
quickly discharged by an internal current source.
+
–
Figure 3. Feed Forward Voltage Mode Control
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CS51227
Powering the IC & UVL
VOUT
The internal logic monitors the supply voltage to ensure
the controller has enough operating headroom. The VREF
block provides power to the controller’s logic. The
VREF(OK) comparator monitors the internal 3.3 V VREF line
and flags a fault if VREF falls below 3.1 V.
The Undervoltage Lockout (UVL) comparator has two
voltage references; the start and stop thresholds. During
power–up, the UVL comparator disables VREF (which
in–turn disables the entire IC) until the controller reaches its
VCC start threshold. During power–down, the UVL
comparator allows the controller to operate until the VCC
stop threshold is reached. The CS51227 requires only 50 µA
during startup. During low VCC and abnormal operation
conditions, the output stage is held at a low level, low
impedance state.
VCOMP
FF
VIN
CT
GATE
Figure 4. Pulse Width Modulated By Output
Current With Constant Input Voltage
Overall, the dynamics of the duty cycle are controlled by
both input and output voltages. As shown in Figure 4, an
elevated output voltage reduces VCOMP through the error
amplifier. This in turn decreases the duty cycle and corrects
the deviation of the output voltage. For line variation, the
ramp signal responds immediately, which provides much
improved line transient response. The delay associated with
the power stage and feedback path has been totally avoided.
As an example, shown in Figure 5, when the input line goes
up, the slope of the ramp signal increases, reducing duty
cycle to counteract the change.
Current Sense and Over Current Protection
The ISENSE pin monitors the switch current for pulse by
pulse current limit. When the ISENSE pin voltage exceeds the
internal threshold (0.3 V typical), the current limit
comparator immediately turns off the Gate signal. The Gate
will then stay off for the remainder of the cycle. Various
techniques, such as using current sensing resistor or current
transformer, are widely adopted to generate the current signal.
The current sense signal is prone to leading edge spikes
caused by switching transitions. A RC low–pass filter can
effectively reduce the spikes and avoid premature triggering.
However, the low pass filter will inevitably change the shape
of the current pulse and also add cost. The CS51227 has
built–in leading edge blanking circuitry that blocks out the
first 150 ns (typ) of each current pulse. This feature removes
the leading edge spikes without altering the current
waveform. Blanking is disabled when the COMP pin voltage
exceeds 3.0 V (typ). This feature reduces the minimum duty
cycle during an output short or overload condition.
VOUT
VCOMP
FF
VIN
DESIGN GUIDELINES
CT
Programming Oscillator Frequency
The switching frequency is set by the capacitor connected
to the CT pin. The CT pin voltage oscillates between 1.0 V
and 2.0 V. The ratio of the charge and discharge currents sets
the maximum duty cycle to be 90%. Use the following
equation to select CT,
GATE
Figure 5. Pulse Width Modulated By Input
Voltage With Constant Output Voltage
The feed forward feature can also be employed to
implement volt–second clamping, which limits the
maximum product of input voltage and turn on time. This
clamp is used in circuits, such as Forward and Flyback
converters, to prevent the transformer from saturating. The
calculation for volt–second clamping is presented in the
Design Guidelines section.
CT 9.027 107
fs
where:
fs = Switching frequency
CT = Capacitance in pF
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CS51227
error amplifier and ramp signal can contribute to DC
regulation.
When CT is less than 100 pF, parasitic capacitance
associated with the CT pin starts to impact frequency accuracy.
Figure 6 shows typical oscillator frequency vs. CT value.
Select Feedback Voltage Divider
As shown in Figure 7, the voltage divider output feeds the
FB pin which connects to the inverting input of the error
amplifier. The non–inverting input of the error amplifier is
connected to a 1.263 V reference voltage. The FB pin has an
input current which has to be taken into account for accurate
output voltage programming. The following equation can be
used to calculate the R1 and R2 value:
1000
Oscillator Frequency (kHz)
900
800
700
600
500
400
R2
VOUT 1.263 ∇
R1 R2
300
where ∇ is the correction factor
200
100
0
∇ Ri R1R2 Ier
0
200
400
CT (pF)
600
800
Ri = DC resistance between the FB pin and the voltage
divider output, as shown in Figure 7.
Ier = FB pin input current, 1.3 µA typical.
Figure 6. Typical Performance Characteristics:
Oscillator Frequency vs. CT
VOUT
Component Selection for Feed Forward Ramp
FF discharge voltage and FF maximum voltage limit the
maximum voltage rise on the FF pin to 1.5 V typical. This
provides the volt–second clamp feature when the FF pin is
driven by the input line. If the line voltage is much greater than
the FF pin voltage, the charge current is approximately equal
to VIN/R where R is the resistor connecting the FF pin and
input line. The voltage second clamp then has the form of:
R1
Ier
–
COMP
Error
Amplifier
FB
Ri
R2
+
VIN TON 1.5 R CFF
1.263 V
One can select RCFF to prevent magnetic devices from
saturating.
In a buck or forward converter, the error amplifier output
VCOMP is equal to:
+
–
Figure 7. The Feedback Voltage Divider Design Has
to Consider the Error Amplifier Input Current
V
TS
VCOMP OUT
0.3V
N R CFF
Thermal Management
where:
N = Transformer turns ratio (use 1 for buck converter)
TS = Switching period
The CS51227 will enter thermal shutdown when the
junction (die surface) temperature exceeds 150°C, typical.
10°C typical thermal hysteresis will prevent part cycling, or
a “chattering” startup near the shutdown temperature.
Junction temperature is a function of the ambient
temperature, thermal resistance of the die and package, and
the power dissipated by the package and leads.
This equation shows that the error amplifier output is
independent of the input voltage. Therefore, the system does
not rely on the error amplifier to respond to line variations.
This excludes the delay associated with the error amplifier.
The line regulation is also greatly improved because both
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CS51227
PACKAGE DIMENSIONS
SO–8
D SUFFIX
CASE 751–07
ISSUE V
–X–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
A
8
5
0.25 (0.010)
S
B
1
M
Y
M
4
K
–Y–
G
C
N
X 45 SEATING
PLANE
–Z–
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
DIM
A
B
C
D
G
H
J
K
M
N
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0
8
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0
8
0.010
0.020
0.228
0.244
PACKAGE THERMAL DATA
Parameter
SO–8
Unit
RΘJC
Typical
45
°C/W
RΘJA
Typical
165
°C/W
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are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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CS51227/D
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8