EDI4164MEV-RP HI-RELIABILITY PRODUCT 4Mx16 EDO (Extended Data Out) Dynamic RAM 3.3V FEATURES ■ 4 Meg x 16 bit CMOS Dynamic RAM ■ RAS - Only, CAS-before-RAS, and HIDDEN refresh capability ■ Package: ■ Low Operating Power Dissipation ■ Access Time: 50, 60 and 70ns ■ Low Standby Power • 50 pin Plastic TSOP ■ Extended Data Out Mode Operation ■ Common I/O ■ Single +3.3V (±0.3V) Supply Operation ■ All Inputs/Outputs TTL Compatible ■ 4096 Cycles Refresh ■ Industrial (-40°C to +85°C) and Military (-55°C to +125°C) Temperature Ranges PIN CONFIGURATION TOP VIEW V CC DQ 1 DQ 2 DQ 3 DQ 4 VCC DQ 5 DQ 6 DQ 7 DQ 8 NC V CC WE RAS NC NC NC NC A0 A1 A2 A3 A4 A5 V CC September 1999 Rev. 2 1 25 PIN DESCRIPTION 50 26 V SS DQ 16 DQ 15 DQ 14 DQ 13 V SS DQ 12 DQ 11 DQ 10 DQ 9 NC V SS LCAS UCAS OE NC NC NC A 11 A 10 A9 A8 A7 A6 V SS 1 A0-11 Address Inputs LCAS / UCAS Column Address Strobes RAS Row Address Strobe WE Write Enable Input OE Output Enable DQ1-16 Data Inputs/Outputs VCC Power (+3.3V±0.3V) VSS Ground NC No Connection White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com EDI4164MEV-RP BLOCK DIAGRAM RAS LCAS UCAS CAS Control Clocks WE Data in Buffer Refresh Timer Refresh Control Memory Array 4096 x 1024 x 16 Cells Refresh Counter Row Address Buffer A0-A11 Sense Amps & IO Row Decoder DQ1 to DQ16 Column Decoder Col. Address Buffer Data Out Buffer OE ABSOLUTE MAXIMUM RATINGS* Voltage on any pin relative to VSS Operating Temperature (Industrial) Operating Temperature (Military) Storage Temperature Power Dissipation Output Current RECOMMENDED DC OPERATING CONDITIONS(1) Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage -0.5V to 4.6V -40°C to +85°C -55°C to +125°C -55°C to +150°C 1 Watt 50 mA Min 3.0 0 2 -0.3 NOTES: 1. All voltage values are with respect to VSS. *Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com Sym VCC VSS VIH VIL 2 Typ 3.3 0 --- Max Units 3.6 V 0 V Vcc +0.3 V 0.8 V EDI4164MEV-RP ELECTRICAL CHARACTERISTICS Parameter Symbol Conditions Operating Current ICC1 Standby Current Min Typ Max Units RAS and UCAS, LCAS, Address cycling @TRC = min. 180 mA ICC2 RAS = UCAS = LCAS = WE = VIH 4 mA RAS-only-Refresh Current ICC3 UCAS = LCAS = VIH, RAS, Addressing cycling @ TRC = min 180 mA EDO Mode Current ICC4 RAS = VIL, UCAS or LCAS Addressing cycling @ TRC = min. 165 mA Standby Current ICC5 RAS = UCAS = LCAS = WE = VCC -0.2V 2 mA CAS-before-RAS Refresh Current ICC6 RAS and UCAS or LCAS cycling @ TRC=min. 180 mA IIL 0V ≤ VIN ≤ Vcc +0.3V All Other Input Pins = 0V 5 µA Output Leakage Current IOL 0V ≤ VOUT ≤ Vcc -5 5 µA Output High Voltage VOH IOH = -2.0mA 2.4 — — V Output Low Voltage VOL IOL = 2.0mA — — 0.4 V Input Leakage Current -5 NOTES: 3. ICC1(av), ICC3(av), ICC4(av), and ICC6 are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. 4. ICC1(av) and ICC4(av) are dependent on output loading. Specified values are obtained with the output open. TRUTH TABLE CAPACITANCE (f = 1.0MHz, TA = 25°C, VCC = 3.3V) Parameter Symbol Max Unit Address Input Capacitance CIN1 5 pF Input Capacitance (CAS, WE, RAS) CIN2 7 pF Output Capacitance (Q) CDQ 7 pF RAS H L L L L L L L L 3 LCAS X H L H L L H L L UCAS X H H L L H L L L WE X X H H H L L L H OE X X L L L H H H H DQ1-8 High Z High Z DQ Out High Z DQ Out DQ In — DQ In High Z DQ9-16 High Z High Z High Z DQ Out DQ Out — DQ In DQ In High Z STATE Standby Refresh Byte Read Byte Read Word Read Byte Write Byte Write Word Write — White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com EDI4164MEV-RP TIMING REQUIREMENTS — READ, WRITE, READ-MODIFY-WRITE, REFRESH, AND PAGE MODE CYCLES (VCC=3.3V±0.3V)Notes1,2,5 50ns Parameter Random Read or Write Cycle Time Read-Modify-Write CycleTime Access Time from CAS Access Time from RAS Access Time From Column Address CAS to output in Low-Z Output buffer turn-off delay Transition Time RAS Precharge Time RAS Low Pulse Width RAS Hold Time after CAS Low CAS Hold Time after RAS Low CAS Low Pulse Width RAS to CAS Delay Time Column Address Delay from RAS Low Delay CAS High to RAS Low Row Address Set Up Time Row Address Hold Time Column Address Set Up Time Column Address Hold Time Column Address Hold Time Referenced RAS Column Address to RAS Setup Read Set Up Time before CAS Low Read Hold Time after CAS High Read Hold Time after RAS High Write Hold Time after CAS Low Write Command Hold Time Referenced to RAS Write Pulse Width RAS Hold Time after Write Low CAS Hold Time after Write Low Data Set up Time Data Hold Time after CAS Low Data Hold Time Referenced to RAS Refresh Cycle (Industrial) Refresh Cycle (Military) Write Setup Time before CAS Low CAS Low to WE Low Delay RAS Low to WE Low Delay Column Address Setup to CAS High OE Low to Output Valid CAS Low to DOUT RAS Low to WE Low Write High to RAS Low Address to WE Low Delay Symbol tRC tRWC tCAC tRAC tAA tCLZ tOFF tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tAR tRAL tRCS tRCH tRRH tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tREF tREF tWCS tCWD tRWD tACH tOE tCOH tWRH tWRP tAWD White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com Min 90 126 60ns Max Min 110 150 13 50 25 0 0 2 30 50 13 38 8 11 9 5 0 9 0 8 40 25 0 0 0 8 40 7 13 8 0 8 40 13 50 10,000 10,000 37 25 0 0 2 40 60 15 45 10 14 12 5 0 10 0 10 45 30 0 0 0 10 45 10 15 10 0 10 45 15 50 10,000 10,000 45 30 13 4 0 0 2 50 70 20 50 15 20 15 5 0 10 0 15 55 35 0 0 0 15 55 15 20 15 0 15 55 20 50 10,000 10,000 50 35 32 16 0 45 94 15 15 3 10 10 55 Max 20 70 35 32 16 0 35 79 15 3 10 10 48 Min 130 180 15 60 30 32 16 0 30 67 15 70ns Max 20 3 10 10 65 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns ns ns ns ns ns ns ns Notes 3,4,5 3,4,10 3,10 6 6,14 2 4 10 8 8 9 9 7 7 7 13 7 EDI4164MEV-RP WRITE CYCLE, EARLY AND DELAYED WRITE (VCC=3.3V±0.3V)Notes1,2,5 50ns Parameter CAS Setup for CAS before RAS Refresh CAS Hold for CAS before RAS Refresh Precharge to CAS Active Access Time from CAS Precharge EDO Page Cycle Time EDO Page Read-Modify-Write Cycle Time CAS precharge time (EDO cycle) RAS pulse width (EDO Cycle) Output Disable Time after OE High Write Low to Next OE Low OE Low to CAS High Setup Time OE High Hold From CAS High OE High Pulse Width OE Setup prior to RAS during Hidden Refresh Cycle OE delay from WE WE pulse to disable at CAS high Symbol tCSR tCHR tRPC tCPA tPC tPRWC tCP tRASP tOD tOEH tOES tOEHC tOEP tORD Min 5 10 5 tWHZ tWPZ 0 10 60ns Max Min 5 10 5 28 20 47 8 50 0 8 4 5 7 0 125K 13 10 Max Min 5 15 5 35 25 56 10 60 0 10 5 10 10 0 0 10 125K 15 13 70ns Max 40 30 71 10 70 0 12 5 10 10 0 0 10 125K 20 15 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 3 6 ns ns NOTES: 1. An initial pause of 200µs is required after power-up followed by any 8 ROR or CBR cycles before proper device operation is achieved, and must be repeated whenever tREF is exceeded. 2. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH (min) and VIL (max) and are assumed to be 3ns for all inputs. 3. Measured with a load equivalent to 1 TTL load and 100pF. 4. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCD ≥ tRCD (max) 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 7. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electric characteristics only. If tWCS ≥ tWCS (min), the cycle is an early write and the data output will remain high impedance for the duration of the cycle. If tCWD ≥ tCWD (min), tRWD > tRWD (min) and tAWD > tAWD (min) then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are referenced to the CAS leading edge in early write cycles and to the WE falling edge in OE controlled write cycle and read-modify-write cycles. 10.Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the specified tRAD (max) limit, then access time is controlled by tAA. 5 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com EDI4164MEV-RP READ CYCLE t RC t RAS t RP VIH RAS VIL t CSH t CRP CAS t RSH t CAS t RCD t RRH VIH VIL t RAD t RAD t ASR A0-A11 t ASC t ACH t CAH VIH VIL ROW t WRP WE t RAL t RAH COLUMN t WRH ROW t RCH t RCS VIH VIL NOTE 1 t AA t RAC NOTE 2 t CAC t CLZ DQ t OFF VOH VOL VALID DATA OPEN t OE OPEN t OD VIH OE VIL DON'T CARE UNDEFINED NOTES : 1. Although WE is a "don't care" at RAS time during an access cycle (Read or Write), the system designer should implement WE high for tWRP and tWRH. 2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last. White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 6 EDI4164MEV-RP WRITE CYCLE, EARLY WRITE t RC t RAS t RP VIH RAS VIL t CSH t CRP CAS t RSH t CAS t RCD VIH VIL t AR t RAD t ASR t RAH t RAL t CAH t ASC t ACH A0-A11 VIH ROW VIL COLUMN ROW t CWL t RWL t WCR t WRP WE t WCS t WRH t WCH t WP VIH VIL NOTE 1 t DHR t DS DQ t DH VOH VALID DATA VOL VIH OE VIL DON'T CARE UNDEFINED READ WRITE CYCLE (Late Write and Read-Modify-Write Cycles) t RWC t RAS t RP VIH RAS VIL t CSH CAS t RSH t CAS t RCD t CRP VIH VIL t AR t RAD t ASR t RAL t ACH t RAH t ASC A0-A11 t CAH VIH ROW VIL COLUMN ROW t RWD t CWD t RCS t WRP WE t CWL t RWL t WRH t AWD t WP VIH VIL t AA NOTE 1 t RAC t CAC t DS t CLZ DQ VOH VALID DOUT OPEN t DH VALID DIN OPEN VOL t OE t OD t OEH VIH OE VIL DON'T CARE UNDEFINED 7 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com EDI4164MEV-RP EDO-PAGE-MODE READ CYCLE t RASP t RP VIH RAS VIL t CSH t CRP CAS t PC t RCD t CAS t RSH t CP t CAS t CP t CAS t CP VIH VIL t AR t RAD t ASR t ACH t CAH t ASC t RAH t ACH t CAH t ASC t ASC t RAL t ACH t CAH VIH A0-A11 ROW VIL COLUMN COLUMN COLUMN ROW t CWL t WRP t WRH t RCH t RCS VIH WE VIL NOTE 1 t AA t AA t RAC t CAC t CAC VOH t CAC t CLZ VALID DATA VALID DATA OPEN t OFF t OEHC t COH VOL VALID DATA t OD t OE t OES VIH OE t CPA t CPA t CLZ DQ t RRH t AA OPEN t OD t OE t OES VIL t OEP DON'T CARE UNDEFINED EDO-PAGE-MODE EARLY WRITE CYCLE t RASP t RP VIH RAS VIL t CSH t CRP CAS t PC t RCD t CAS t RSH t CP t CAS t CP t CAS t CP VIH VIL t AR t RAD t ASR A0-A11 t ACH t CAH t ASC t ACH t CAH t ASC t ACH t RAL t CAH VIH VIL ROW t WRP WE t ASC t RAH t WRH COLUMN t WCS t WP COLUMN t CWL t WCH t WCS t WP t CWL t WCH COLUMN t WCS t WP ROW t CWL t WCH VIH VIL NOTE 1 t WCR t DHR t RWL t DS DQ VOH VOL OE VIH VIL t DH VALID DATA t DS t DH VALID DATA t DS t DH VALID DATA DON'T CARE UNDEFINED White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 8 EDI4164MEV-RP EDO-PAGE-MODE READ-WRITE CYCLE t RASP t RP VIH RAS VIL t CSH t CRP CAS t RCD t PC / t PRWC NOTE 1 t CP t CAS t CAS t RSH t CAS t CP t CP VIH VIL t AR t RAD t RAH t ASR A0-A11 t RAL t ASC t ASC t CAH t CAH t ASC t CAH VIH ROW VIL COLUMN COLUMN COLUMN ROW t RWD t RCS t CWL t WP t AWD t WRP t WRH WE t RWL t CWL t WP t AWD t CWD t CWD VIH VIL NOTE 2 t AA t AA t DH t CPA t DS t CAC t DS t CAC t CLZ t CLZ VALID DOUT OPEN VOL t DH t CPA t DS t CAC t CLZ VOH t AA t DH t RAC DQ t CWL t WP t AWD t CWD VALID DIN VALID DOUT t OD VALID DIN VALID DOUT VALID DIN t OD t OE t OE OPEN t OD t OEH t OE VIH OE VIL DON'T CARE UNDEFINED NOTE: 1. TPC is for Late Write Cycles Only EDO-PAGE-MODE READ-EARLY-WRITE CYCLE t RASP t RP VIH RAS VIL t CSH t CRP CAS t RCD t CAS t PC t CP t RSH t CAS t PC t CAS t CP t CP VIH VIL t AR t ASR A0-A11 t RAD t RAH t CAH t ASC VIL ROW COLUMN (A) t ASC COLUMN (B) t CAH COLUMN (N) t RCH t RCS t CWS ROW t WCH VIH VIL t AA NOTE 1 t AA t CPA t RAC t CAC t COH t CAC DQ t CAH VIH t WRP t WRH WE t RAL t ACH t ASC VOH VOL OPEN VALID DATA (A) t DS t DH t WHZ VALID DATA (B) VALID DATA IN t OE VIH OE VIL DON'T CARE UNDEFINED 9 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com EDI4164MEV-RP READ CYCLE WITH WE CONTROLLED DISABLE VIH RAS VIL t CSH t CRP CAS t RCD t CAS t CP VIH VIL t AR t RAD t ASR A0-A11 t RAH ROW VIL t WRP WE t ASC t CAH t ASC VIH COLUMN t WRH COLUMN t RCS t RCH t WPZ t RCS VIH VIL NOTE 1 t AA t RAC t CAC t CLZ DQ t CLZ t WHZ VOH VALID DATA OPEN VOL t OE OPEN t OD VIH OE VIL DON'T CARE UNDEFINED RAS - ONLY REFRESH CYCLE (WE and OE=Don't Care) t RC t RP t RAS VIH RAS VIL t RPC t CRP CAS VIH VIL t ASR A0-A11 DQ t RAH VIH ROW VIL ROW VOH OPEN VOL t WRP t WRH t WRP t WRH VIH WE VIL NOTE 1 DON'T CARE UNDEFINED White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 10 EDI4164MEV-RP CBR REFRESH CYCLE (A0-A11 and OE=Don't Care) t RP t RP t RAS t RAS VIH RAS VIL t RPC t CP t CSR t RPC t CHR t CSR t CHR VIH CAS VIL DQ VOH OPEN VOL t WRP t WRH t WRP t WRH VIH WE NOTE 1 VIL DON'T CARE UNDEFINED HIDDEN REFRESH CYCLE (WE=High, OE=Low) NOTE 1 t RC VIH RAS t RAS t CRP CAS t RP t RAS VIL t RCD t RSH t CHR VIH VIL t AR t RAD t ASR A0-A11 t RAH t ASC t CAH VIH VIL ROW COLUMN t AA t RAC t CAC t CLZ DQ t OFF VOH VOL VALID DATA OPEN t ORD VIH OE OPEN t OD t OE VIL DON'T CARE UNDEFINED NOTE: 1. A hidden Refresh may also be performed after a Write Cycle. In this case, WE = Low and OE = High 11 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com EDI4164MEV-RP PACKAGE DESCRIPTION 50 PIN PLASTIC TSOP PACKAGE NO. 372 0.830 0.820 0.471 0.455 0.405 0.395 SEE DETAIL A 0.008 0.005 0.032 TYP 0.018 0.012 0.047 MAX 0.006 0.002 0.024 0.016 DETAIL A ALL DIMENSIONS ARE IN INCHES ORDERING INFORMATION MILITARY (-55 °C TO +125 °C) Part No. EDI4164MEV50SM EDI4164MEV60SM EDI4164MEV70SM INDUSTRIAL (-40 °C TO +85 °C) Speed (ns) Package No. 50 60 70 372 372 372 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com Part No. EDI4164MEV50SI EDI4164MEV60SI EDI4164MEV70SI 12 Speed (ns) Package No. 50 60 70 372 372 372