HA16150T/P High-Speed Current Mode Push-Pull PWM Control IC ADE-204-071 (Z) Rev.0 Aug. 2002 Description The HA16150 is a high-speed current mode PWM control IC with push-pull dual outputs, suitable for highreliability, high-efficiency, high-mounting-density isolated DC-DC converter and high-output AC-DC converter control. The HA16150 can be used in various applications, including push-pull converters and half-bridge, doubleforward, and single-forward applications. The HA16150 incorporates 180-degree phase-inverted push-pull dual outputs, and directly drives a power MOS FET. Operation at a maximum of 1 MHz is possible on an oscillator reference frequency basis. The package lineup comprises an ultra-thin surface-mount TSSOP-16 suitable for slim communication system modules, and a general-purpose insertion DILP-6 suitable for characteristics evaluation. Features <Maximum Ratings> • Supply voltage Vcc: 20 V • Peak output current Ipk-out: ±1.0 A • Operating junction temperature Tjopr: –40°C to +125°C <Electrical Characteristics> • VREF output voltage VREF: 5.0 V ± 1% • UVLO start threshold VH: 9.3 V ± 0.7 V • UVLO shutdown threshold VL: 8.3 V ± 0.7 V • Operating current Icc: 4 mA typ. • Standby current Is: 150 µA typ. <Functions> • Soft start (one external timing capacitance) • Remote on/off control • Independent dead band time adjustment • Current limiter adjustment (set drooping characteristic adjustment) • Push-pull/single-end output switching • Package lineup: TSSOP-16/DILP-16 HA16150T/P Pin Arrangement INP 1 16 VREF INM 2 15 REMOTE EOUT 3 14 VCC CSLIM 4 13 OUT2 CS 5 12 PGND RT 6 11 OUT1 CT 7 10 TDB SS 8 9 SGND (Top view) Pin Functions Pin No. Pin Name Pin Function 1 INP Error amplifier non-inverted (+) input 2 INM Error amplifier inverted (-) input 3 EOUT Error amplifier output 4 CSLIM Current limiter level adjustment 5 CS Current sense signal input 6 RT Operating frequency setting timing resistance connection 7 CT Operating frequency setting timing capacitance connection 8 SS Soft start time setting timing capacitance connection 9 SGND Small signal system ground 10 TDB Dead band time setting timing capacitance connection 11 OUT1 Power MOS FET driver output 1 12 PGND Power system ground 13 OUT2 Power MOS FET driver output 2 14 VCC Supply voltage 15 REMOTE Remote on/off control 16 VREF Reference voltage Rev.0, Aug. 2002, page 2 of 23 HA16150T/P Block Diagram VREF 16 − + REMOTE 15 3.0V Vref REMOTE Vrefgood Vref Comp. Good − + 5µA SS 8 VCC 14 Vrefgood UVL Vref Generator 9.3V 8.3V 10 TDB tdb Adjust SS Comp. SS Ramp. 22.2V UVL Driver SS Ramp. CT 11 OUT1 12 PGND Vref RT 6 D Q Vref 13 OUT2 CK Q 1/2 Driver CT 7 Vrefgood PGND R Oscillator Q CS Latch S Vref − INP 1 + − + INM 2 Vcc 400µA 2R R Blanking Time 65ns 5 CS CS Comp. E-amp. (VEOUT–2VF)/3 1.4V 9 SGND − + Blanking Enable Comp. 3 4 EOUT CSLIM Rev.0, Aug. 2002, page 3 of 23 HA16150T/P Absolute Maximum Ratings (Ta = 25°C) Item Symbol Ratings Unit Power supply voltage Vcc 20 V OUT1 output current (peak) Ipk-out1 ±1.0 A 3 OUT2 output current (peak) Ipk-out2 ±1.0 A 3 OUT1 output current (DC) Idc-out1 ±0.1 A OUT2 output current (DC) Idc-out2 ±0.1 A OUT1 output voltage Vout1 –0.3 to Vcc V OUT2 output voltage Vout2 –0.3 to Vcc V INM pin voltage Vinm –0.3 to Vcc V REMOTE pin voltage Vremote –0.3 to Vcc V REMOTE pin current Iremote +0.2 mA INP pin voltage Vinp –0.3 to Vcc V SS pin voltage Vss –0.3 to Vref V RT pin voltage Vrt –0.3 to Vref V RT pin current Irt –0.2 mA CT pin voltage Vct –0.3 to Vref V CSLIM pin voltage Vcslim –0.3 to Vref V EOUT pin voltage Veout –0.3 to Vref V VREF pin voltage Vref –0.3 to Vref V TDB pin voltage Vtdb –0.3 to Vref V CS pin voltage Vcs –0.3 to Vref V Operating junction temperature Tj-opr –40 to +125 °C Storage temperature Tstg –55 to +150 °C Notes: 1. 2. 3. 4. Note 4 Rated voltages are with reference to the GND (SGND, PGND) pin. For rated currents, inflow to the IC is indicated by (+), and outflow by (–). Shows the transient current when driving a capacitive load. HA16150T (TSSOP): θja = 250°C/W This value is based on actual measurements on a 10% wiring density glass epoxy circuit board (55 mm × 45 mm × 1.6 mm). HA16150P (DILP): θja = 120°C/W Rev.0, Aug. 2002, page 4 of 23 HA16150T/P Electrical Characteristics (Ta = 25°C, Vcc = 12 V, Fosc = 100 kHz) Item Supply VREF Oscillator PWM Comparator Error amplifier Current sense Remote Soft start Symbol Min Typ Max Unit Test Conditions Start threshold VH 8.6 9.3 10.0 V Shutdown threshold VL 7.6 8.3 9.0 V UVLO hysteresis dVUVL 0.7 1.0 1.3 V Start-up current Is 100 150 250 µA Vcc = 8V Operating current Icc — 4 6 mA Vinm = 1.0V, Vinp = 1.25V, Vcs = 0V Vcc zenner shunt voltage Vz 21.2 22.2 23.2 V Icc = 10mA Vz temperature stability dVz/dTa — 4.5 — mV/°C Icc = 10mA *1 Output voltage Vref 4.95 5.0 5.05 V Iref = –1mA Line regulation Vref-line — 5 20 mV Vcc = 11V to 18V Load regulation Vref-load — 5 20 mV Iref = –1mA to –20mA Temperature stability dVref/dTa — 80 — ppm/°C Ta = –40 to 125°C Oscillator frequency fosc 88 100 112 kHz Measured at OUT1 and OUT2 RT = 27kΩ, CT = 1000pF Temperature stability dfosc/dTa — ±0.1 — %/°C Ta = –40 to 125°C *1 High voltage Vth — 3.0 — V DC *1 Low voltage Vtl — 2.0 — V DC *1 Differential voltage dVt — 1.0 — V DC *1 Input bias current Ifb –1 — +1 µA Open loop gain Av — 70 — dB f = 1.0kHz *1 EOUT sink current Isnk-eout — 3.0 — mA Veout = 1.1V *1 EOUT source current Isrc-eout — –0.4 — mA Veout = 3.0V *1 Low voltage Vol-eout — 0.8 1.1 V EOUT : Open High voltage Voh-eout 4.7 5.0 — V EOUT : Open Voltage gain Avcs 2.85 3.00 3.15 V/V Delay to output td-cs — 150 230 ns Leading edge blanking time tbl — 65 — ns *1 Leading edge blanking disable voltage Vbl-off 1.3 1.4 1.5 V Measured pin : EOUT On threshold voltage Von 1.40 — — V *1 Off threshold voltage Voff — — 3.00 V *1 Sink current Iremote 60 90 120 µA Vremote = 4V Source current Iss –7.0 –5.0 –3.0 µA Vss = 1V Notes: 1. Reference values for design. Rev.0, Aug. 2002, page 5 of 23 HA16150T/P Electrical Characteristics (cont.) (Ta = 25°C, Vcc = 12 V, Fosc = 100 kHz) Item OUT1 Symbol Min Typ Max Unit Test Conditions Minimum duty cycle Dmin-out1 — — 0 % Veout = 0V Maximum duty cycle Dmax-out1 48 49 — % TDB : OPEN Rise time tr-out1 — 30 65 ns CL = 1000pF Fall time tf-out1 — 30 65 ns CL = 1000pF Low voltage Vol1-out1 — 0.05 0.2 V Iout = 20mA Vol2-out1 — 0.5 2.0 V Iout = 200mA (pulse) Voh1-out1 11.5 11.9 — V Iout = –20mA Voh2-out1 10.0 11.0 — V Iout = –200mA (pulse) Minimum duty cycle Dmin-out2 — — 0 % Veout = 0V Maximum duty cycle Dmax-out2 48 49 — % TDB : OPEN Rise time tr-out2 — 30 65 ns CL = 1000pF Fall time tf-out2 — 30 65 ns CL = 1000pF Low voltage Vol1-out2 — 0.05 0.2 V Iout = 20mA Vol2-out2 — 0.5 2.0 V Iout = 200mA (pulse) Voh1-out2 11.5 11.9 — V Iout = –20mA Voh2-out2 10.0 11.0 — V Iout = –200mA (pulse) tdb0 — 60 — ns TDB : OPEN *1 tdb — 140 — ns Ctdb = 47pF *1 High voltage OUT2 High voltage Dead-band time Dead-band time Notes: 1. Reference values for design. Rev.0, Aug. 2002, page 6 of 23 HA16150T/P Timing Diagram 1. Start-up Timing 9.3V 8.3V VCC VREF 3V V_CT 2V RESET (internal signal) Q (internal signal) Q (internal signal) V_TDB term. V_TDB comp. out (internal signal) tdb tdb Dead-band pulse (internal signal) OUT1 OFF ON OFF ON OFF ON OFF ON OFF ON OUT2 ON OFF ON OFF ON OFF ON OFF ON OFF ON Rev.0, Aug. 2002, page 7 of 23 HA16150T/P 2. Current Sense VREF 3V V_CT 2V RESET (internal signal) Dead-band pulse (internal signal) Q (internal signal) Q (internal signal) V_EOUT V_CS V_CS comp.(–) OUT1 OUT2 Rev.0, Aug. 2002, page 8 of 23 V_CS comp.(–) = (V_EOUT – 2VF) / 3 HA16150T/P 3. Soft Start VREF 3V V_CT 2V RESET (internal signal) V_TDB term. Dead-band pulse (internal signal) V_SS SS comp. IN+ (internal signal) SS comp. out (internal signal) OUT1 OUT2 Rev.0, Aug. 2002, page 9 of 23 HA16150T/P 4. Leading Edge Blanking 3V V_CT 2V RESET (internal signal) Dead-band pulse (internal signal) Q (internal signal) Q (internal signal) V_EOUT 1.4V V_CS V_CS comp.(–) (internal signal) Blanking pulse (internal signal) V_CS comp.(+) (internal signal) OUT1 OUT2 Rev.0, Aug. 2002, page 10 of 23 Blanking Time reset HA16150T/P 5. Push-Pull/Single-End Switching (1) Push-pull operation: Leave the TDB pin open or connect a capacitance to GND 3V V_CT 2V RESET (internal signal) V_TDB term. Dead-band pulse (internal signal) OUT1 OUT2 (2) Single-end operation: Perform pull-up connection of the TDB pin to the VREF pin 3V V_CT 2V RESET (internal signal) 5V V_TDB term. Dead-band pulse (internal signal) 0V OUT1 OUT2 0V Rev.0, Aug. 2002, page 11 of 23 HA16150T/P Functional Description 1. UVL Circuit The UVL circuit monitors the Vcc voltage and halts operation of the IC in the event of a low voltage. The voltage for detecting Vcc has a hysteresis characteristic, with 9.3 V as the start threshold and 8.3 V as the shutdown threshold. When the IC has been halted by the UVL circuit, control is performed to fix driver circuit output low, halt VREF output and the oscillator, and reset the soft start circuit. VCC VREF 9.3V 8.3V 4.5V 4.5V 3V V_CT 2V V_SS OUT1 OUT2 Figure 1 2. Remote ON/OFF Circuit A remote on/off control function is incorporated, enabling the IC to be halted without cutting the supply voltage by pulling the REMOTE pin up to 3.0 V or higher. This function halts VREF output and driver output. At this time the IC enters standby mode and IC current dissipation can be decreased. This function can thus be used for power management, etc. When remote off control is performed, the soft start circuit is also reset, and therefore a soft start is effected when restarting, preventing overshoot. If the remote on/off control function is not used, the REMOTE pin should be permanently pulled down to GND with a resistance of about 100 kΩ. Rev.0, Aug. 2002, page 12 of 23 HA16150T/P 3. Soft Start Circuit This function gradually increases the pulse width of the OUT pin from 0% duty at start-up to prevent a sudden increase in the pulse width that may cause problems such as transient stress on external parts or overshoot of the secondary-side output voltage. The soft start time can easily be set with a single external capacitance. V_CT V_SS SS comp. IN+ (internal signal) 1.1V SS comp. out OUT1 OUT2 Figure 2 Soft start time tss is determined by SS pin connection capacitance Css and an internal constant, and can be estimated using the equation shown below. Soft start time tss is the time until the first pulse is output to the driver output OUT pin after VREF starts up following UVLO release. This is equivalent to the time until the SS pin voltage reaches IC-internal SS comparator reference voltage VTL (1.1 V), and can be calculated using the approximate equation shown below. Soft start time tss when Css is 1000pF is given by the following equation. tss = Css × VTL = Iss 1000 [pF] × 1.1 [V] 5 [µA] ≈ 220 [µs] * Iss: SS pin source current, 5 µA typ. Rev.0, Aug. 2002, page 13 of 23 HA16150T/P 4. Dead Band Generation Circuit "Dead band" refers to the time when both push-pull dual outputs are off. By setting the dead band time arbitrarily, it is possible to configure a system in which the dual outputs are never on simultaneously with respect to input and load variations. V_CT 0.5V V_TDB SS comp. out (internal signal) OUT1 OUT2 Figure 3 Dead band time tdb is determined by TDB pin connection capacitance Cdb and an internal constant, and can be estimated using the equation shown below. Even when the TDB pin is open, the dead band time does not become zero due to floating capacitance of the IC package, etc. This dead band time is designated tdb0. Dead band time tdb when Cdb is 47 pF is given by the following equation. tdb = tdb0 + 47 [pF] × 0.5 [V] Cdb × Vth = 300 [µA] Idb = 60 [ns] + 78 [ns] = 138 [ns] * Idb: TDB pin source current, 300 µA typ. * Vth: IC-internal TDB comparator reference voltage Rev.0, Aug. 2002, page 14 of 23 HA16150T/P 5. Operating Frequency The operating frequency is adjusted by means of CT and RT. Adjustment examples are shown in the graph below. This graph shows driver output operating frequencies. The reference operating frequency generated at the CT pin is twice the driver output frequency. The driver output operating frequency can be estimated using the approximate equation shown below. This is only an approximate equation, and the higher the frequency, the greater will be the degree of error of the approximate equation due to the effects of CT pin voltage overshoot, undershoot, and so forth. When the operating frequency is adjusted, it is essential to confirm operation using the actual system. 8 8 = 3 × C6 × R7 3 × CT × RT 8 = 3 × 470 [pF] × 27 [kΩ] fosc = = 210 [kHz] 10000 fosc (RT = 5.1kΩ) fosc (RT = 10kΩ) fosc (RT = 27kΩ) fosc (RT = 75kΩ) fosc (kHz) 1000 100 0 100 1000 10000 CT (pF) Figure 4 Rev.0, Aug. 2002, page 15 of 23 HA16150T/P 6. Current Limiter Level The drooping characteristic of the power supply output can be adjusted by adjusting the CSLIM pin voltage. For example, the drooping characteristic can easily be adjusted, as shown in the figure below, by setting VREF to a divided value with resistances R1 and R2 and connecting adjustment resistance Rx in parallel to R2. R1 15k Rx Vref 16 Vcc − + VREF 5 CS CS Comp. − + R2 12k E-amp. 2R R 3 EOUT 4 CSLIM Figure 5 CSLIM Peripheral Circuit The graph below shows examples of power supply output drooping characteristic adjustment in a push-pull converter. As shown in this graph, the point at which the power supply output current limit begins to be applied can be adjusted by adjustment of the CSLIM pin voltage. 3.60 Rx: 24k (VCSLIM = 1.75V) 3.40 Rx: 33k (VCSLIM = 1.85V) Rx: open (VCSLIM = 2.22V) Vout (V) 3.20 3.00 2.80 Rx: 47k (VCSLIM = 1.95V) Rx: 15k (VCSLIM = 1.55V) 2.60 2.40 2.20 2.00 0.0 2.0 4.0 6.0 8.0 10.0 Iout (A) Figure 6 Adjustment of Power Supply Output Drooping Characteristic Rev.0, Aug. 2002, page 16 of 23 HA16150T/P Characteristic Curves Power Supply Current vs. Power Supply Voltage Characteristics 6.0 Ta = 25°C fosc = 100kHz 5.0 Icc (mA) 4.0 3.0 2.0 1.0 0.0 7.0 7.5 8.0 8.5 9.0 9.5 10.0 Vcc (V) Standby Current vs. Power Supply Voltage Characteristics 1.0 Ta = 25°C fosc = 100kHz Is (mA) 0.8 0.6 0.4 0.2 0.0 0 1 2 3 4 5 6 7 8 9 10 Vcc (V) Rev.0, Aug. 2002, page 17 of 23 HA16150T/P Power Supply Current vs. Power Supply Voltage (Clamp Zener Voltage) Characteristics 18.0 Ta = 25°C 16.0 fosc = 100kHz Icc (mA) 14.0 12.0 10.0 8.0 6.0 4.0 20.0 20.5 21.0 21.5 22.0 22.5 23.0 Vcc (V) Power Supply Current vs. REMOTE Pin Voltage Characteristics 6.0 Ta = 25°C 5.0 VREF (V) 4.0 3.0 2.0 1.0 0.0 0.0 0.5 1.0 1.5 2.0 VREMOTE (V) Rev.0, Aug. 2002, page 18 of 23 2.5 3.0 3.5 4.0 HA16150T/P VREF Output Voltage vs. Ambient Temperature Characteristics 5.20 Iref = 1mA 5.15 VREF (V) 5.10 5.05 5.00 4.95 4.90 4.85 4.80 –50 –25 0 25 50 75 100 125 Ta (°C) Operating Frequency vs. Ambient Temperature Characteristics 120 RT = 27kΩ CT = 1000pF fosc (kHz) 110 100 90 80 –50 –25 0 25 50 75 100 125 Ta (°C) Rev.0, Aug. 2002, page 19 of 23 HA16150T/P UVL Start-up Voltage vs. Ambient Temperature Characteristics 10.0 9.8 9.6 VH (V) 9.4 9.2 9.0 8.8 8.6 8.4 8.2 8.0 –50 –25 0 25 50 75 100 125 Ta (°C) 9.0 UVL Shutdown Voltage vs. Ambient Temperature Characteristics 8.8 8.6 VL (V) 8.4 8.2 8.0 7.8 7.6 7.4 7.2 7.0 –50 –25 0 25 50 Ta (°C) Rev.0, Aug. 2002, page 20 of 23 75 100 125 HA16150T/P ApplicationCircuit Example The following diagram shows a sample application circuit for a push-pull converter with a 48 V input voltage, 3.3 V output voltage, and 10 A output current. L2 1.5µH Core : PQ20/16 Bobin : BPQ20/16-1114CP + Vin 48V C2 47µ/100V 10T 2T 10T 2T R15 R19 2k 1k C12 R17 0.033µ 3.3k R10 15k C3 0.1µ OUT(+) R14 R18 680 390 + C13 470µ/10V R16 5.1k HA17431VP OUT(–) D3 20V C10+ 0.1µ R8 120k L1 100µ D2 IS2076A C9+ 4.7µ VREF 16 REMOTE R9 120k 3.0V Vref SS REMOTE Comp. 5µA 8 7T VCC 14 − + 15 UVL Vref Generator 8.3V Vref Good SS Comp. SS Ramp. Vrefgood R7 27k CT 11 Vref 13 CK Q 1/2 Driver 7 Vrefgood 12 R CS Latch Vcc − + R3 5.1k − OUT1 400µA 2R OUT2 10 PGND Q S 2 H5N2001LS R11 Vref Q D Vref INM R12 10 PGND Oscillator VREF TDB Driver 6 C7 1000p 10 tdb Adjust SS Ramp. CT RT 22.2V UVL 9.3V − + Vrefgood C7 1000p D1 IS2076A R Blanking Time 65ns 5 R4 1k CS C5 680p CS Comp. R13 0.15/2W + E-amp. R6 5.1k (VEOUT–2VF)/3 INP 1 1.4V VREF 3 EOUT 4 CSLIM R5 5.1k C4 0.01µ R1 15k 9 − + SGND Blanking Enable Comp. VREF R2 12k C14 6800p Photo Coupler Rev.0, Aug. 2002, page 21 of 23 HA16150T/P Package Dimensions As of January, 2002 19.20 20.00 Max 1 7.40 Max 9 6.30 16 Unit: mm 8 1.3 0.48 ± 0.10 7.62 2.54 Min 5.06 Max 2.54 ± 0.25 0.51 Min 1.11 Max + 0.13 0.25 – 0.05 0˚ – 15˚ Hitachi Code JEDEC JEITA Mass (reference value) DP-16 Conforms Conforms 1.07 g As of January, 2002 Unit: mm 4.40 5.00 5.30 Max 16 9 1 8 0.65 0.08 *0.22 +– 0.07 0.20 ± 0.06 1.0 0.13 M *Dimension including the plating thickness Base material dimension Rev.0, Aug. 2002, page 22 of 23 *0.17 ± 0.05 0.15 ± 0.04 1.10 Max 0.10 0.07 +0.03 –0.04 6.40 ± 0.20 0.65 Max 0˚ – 8˚ 0.50 ± 0.10 Hitachi Code JEDEC JEITA Mass (reference value) TTP-16DA — — 0.05 g HA16150T/P Disclaimer 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. 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(Taipei Branch Office) 4/F, No. 167, Tun Hwa North Road Hung-Kuo Building Taipei (105), Taiwan Tel : <886>-(2)-2718-3666 Fax : <886>-(2)-2718-8180 Telex : 23222 HAS-TP URL : http://www.hitachi.com.tw Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel : <852>-2735-9218 Fax : <852>-2730-0281 URL : http://semiconductor.hitachi.com.hk Copyright © Hitachi, Ltd., 2002. All rights reserved. Printed in Japan. Colophon 6.0 Rev.0, Aug. 2002, page 23 of 23