ETC ACT361

ACT361
Rev PrD, 28-May-09
Preliminary Product Information―All Information Subject to Change
High Performance ActivePSRTM Primary Switching Regulator
FEATURES
• Patented Primary Side Regulation
Technology
• No Opto-Coupler
• Best-in-Class Constant Voltage, Constant
Current Accuracy
•
•
•
•
Low EMI
Proprietary Fast Startup Circuit
Built-in Soft-Start Circuit
Integrated Line and Primary Inductance
Compensation
• Integrated Programmable Output Cord
Resistance Compensation
• Line Under-Voltage, Output Over-Voltage,
Output Short-Circuit and Over-Temperature
Protection
• Complies with all Global Energy Efficiency
and CEC Average Efficiency Standards
• Adjustable power from 2W to 7W
• Minimum External Components
• Tiny SOT23-6 Package
The ACT361 ensures safe operation with complete
protection against all fault conditions. Built-in
protection circuitry is provided for output shortcircuit, output over-voltage, line under-voltage, and
over temperature conditions.
The ACT361 ActivePSRTM is optimized for high
performance, cost-sensitive applications, and
utilizes Active-Semi’s proprietary primary-side
feedback architecture to provide accurate constant
voltage, constant current (CV/CC) regulation
without the need of an opto-coupler or reference
device. Integrated line and primary inductance
compensation circuitry provides accurate constant
current operation despite wide variations in line
voltage and primary inductance. Integrated output
cord resistance compensation further enhances
output accuracy. The ACT361 achieves excellent
regulation and transient response, yet requires less
than 150mW of standby power.
The ACT361 is optimized for 2W to 7W
applications. It is available in space-saving 6 pin
SOT23-6 package.
Figure 1:
Simplified Application Circuit
APPLICATIONS
• Chargers for Cell Phones, PDAs, MP3,
Portable Media Players, DSCs, and Other
Portable Devices and Appliances
• RCC Adapter Replacements
VDD
• Linear Adapter Replacements
• Standby and Auxiliary Supplies
BD
ACT361
SW
GENERAL DESCRIPTION
The ACT361 belongs to the high performance
patented ActivePSRTM Family of Universal-input
AC/DC off-line controllers for battery charger and
adapter applications. It is designed for flyback
topology working in discontinuous conduction mode
(DCM). The ACT361 meets all of the global energy
efficiency regulations (CEC, European Blue Angel,
and US Energy Star standards) while using very
few external components.
CS
FB
G
ACT361
Rev PrD, 28-May-09
ORDERING INFORMATION
PART NUMBER
TEMPERATURE RANGE
PACKAGE
PINS
PACKING
METHOD
TOP MARK
ACT361US-T
-40°C to 85°C
SOT23-6
6
TAPE & REEL
DZLW
PIN CONFIGURATION
1
G
2
BD
3
DZLW
SW
6
CS
5
FB
4
VDD
SOT23-6
ACT361US-T
PIN DESCRIPTIONS
PIN
NAME
DESCRIPTION
1
SW
2
G
3
BD
4
VDD
5
FB
Feedback Pin. Connect this pin to a resistor divider network from the auxiliary winding.
6
CS
Current Sense Pin. Connect an external resistor (RCS) between this pin and ground to set peak
current limit for the primary switch. The peak current limit is set by (0.4V × 0.9) / RCS. For more
detailed information, see Application Information.
Switch Drive. Switch node for the external NPN transistor. Connect this pin to the external power
NPN’s emitter. This pin also supplies current to VDD during startup.
Ground.
Base Drive. Base driver for the external NPN transistor.
Power Supply. This pin provides bias power for the IC during startup and steady state operation.
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ACT361
Rev PrD, 28-May-09
ABSOLUTE MAXIMUM RATINGSc
PARAMETER
VALUE
UNIT
-0.3 to +30
V
100
mA
-0.3 to +6
V
Internally limited
A
Maximum Power Dissipation (derate 4.5mW/˚C above TA = 50˚C)
0.45
W
Junction to Ambient Thermal Resistance (θJA)
220
˚C/W
Operating Junction Temperature
-40 to 150
˚C
Storage Junction
-55 to 150
˚C
300
˚C
VDD, BD, SW to G
Maximum Continuous VDD Current
FB, CS to G
Continuous SW Current
Lead Temperature (Soldering, 10 sec)
c: Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for long periods may
affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 14V, VOUT = 5V, LP = 2.7mH, NP = 168, NS = 12, NA = 30, TA = 25°C, unless otherwise specified.)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply
VDD Turn-On Voltage
VDDON
VDD Rising from 0
17.5
18.5
20
V
VDD Turn-Off Voltage
VDDOFF
VDD Falling after Turn-on
5.25
5.5
5.75
V
IDD
VDD = 14V, after Turn-on
1
2
mA
VDD = 14V, before Turn-on
25
45
µA
2
µA
Supply Current
Start Up Supply Current
IDDST
BD Current during Startup
IBDST
Internal Soft Startup Time
10
ms
Oscillator
Switching Frequency
Clamp Switching Frequency
Minimum Switching Frequency
Maximum Duty Cycle
fSW
100% VOUTCV @ full load
42
25% VOUTCV @ full load
21
fCLAMP
45
fMIN
TBD
DMAX
VFB
kHz
55
kHz
1.5
TBD
kHz
70
75
80
%
2.188
2.210
2.232
V
100
nA
Feedback
Effective FB Voltage
FB Leakage Current
Output Cable Resistance
Compensation
Innovative PowerTM
DVCOMP
No RCORD between VDD and SW
0
RCORD = 330k
3
RCORD = 160k
6
RCORD = 82k
9
RCORD = 39k
12
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%
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ACT361
Rev PrD, 28-May-09
ELECTRICAL CHARACTERISTICS CONT’D
(VDD = 14V, VOUT = 5V, LP = 2.7mH, NP = 168, NS = 12, NA = 30, TA = 25°C, unless otherwise specified.)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
600
mA
412
mV
Current Limit
SW Current Limit Range
CS Current Limit Threshold
100
VCSLIM
Leading Edge Blanking Time
388
400
200
300
ns
Driver Outputs
Switch ON-Resistance
RON
SW Off Leakage Current
ISW = 50mA
1.2
2
Ω
VSW = 22V
0
1
µA
VDDON
+3
VDDON
+4
V
Protection
VDD Latch-Off Voltage
VDDON
+2
VDDOVP
Thermal Shutdown Temperature
150
˚C
Thermal Hysteresis
20
˚C
0.15
mA
Line UVLO
Innovative PowerTM
IFBUVLO
RFB1 = 53.6kΩ
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ACT361
Rev PrD, 28-May-09
FUNCTIONAL BLOCK DIAGRAM
FUNCTIONAL DESCRIPTION
As shown in the Functional Block Diagram, to
regulate the output voltage in CV (constant voltage)
mode, the ACT361 compares the feedback voltage
at FB pin to the internal reference and generates an
error signal to the pre-amplifier. The error signal,
after filtering out the switching transients and
compensated with the internal compensation
network, modulates the external NPN transistor
peak current at CS pin with current mode PFWM
(Pulse Frequency and Width Modulation) control.
To regulate the output current in CC (constant
current) mode, the oscillator frequency is modulated
by the output voltage.
ACT361 internal circuitry and the NPN base drive
until the output voltage is high enough to sustain
VDD through the auxiliary winding. The VDDOFF
threshold is 5.5V; therefore, the voltage on the VDD
capacitor must remain above 5.5V while the output
is charging up.
Constant Voltage (CV) Mode Operation
In constant voltage operation, the ACT361 captures
the auxiliary flyback signal at FB pin through a
resistor divider network R8 and R9 in Figure 2. The
signal at FB pin is pre-amplified against the internal
reference voltage, and the secondary side output
voltage is extracted based on Active-Semi's
proprietary filter architecture.
SW is a driver output that drives the emitter of an
external high voltage NPN transistor. This baseemitter-drive method makes the drive circuit the
most efficient.
This error signal is then amplified by the internal
error amplifier. When the secondary output voltage
is above regulation, the error amplifier output
voltage decreases to reduce the switch current.
When the secondary output voltage is below
regulation, the error amplifier output voltage
increases to ramp up the switch current to bring the
secondary output back to regulation. The output
regulation voltage is determined by the following
relationship:
Fast Startup
VDD is the power supply terminal for the ACT361.
During startup, the ACT361 typically draws only
20μA supply current. The startup resistor from the
rectified high voltage DC rail supplies current to the
base of the NPN transistor. This results in an
amplified emitter current to VDD through the SW
pin via Active-Semi's proprietary fast-startup
circuitry until it exceeds the VDDON threshold 19V. At
this point, the ACT361 enters internal startup mode
with the peak current limit ramping up in 10ms.
After switching starts, the output voltage begins to
rise. The VDD bypass capacitor must supply the
Innovative PowerTM
⎛
R
VOUTCV = 2 .21V × ⎜⎜1 + FB1
R FB 2
⎝
(1)
where RFB1 (R8) and RFB2 (R9) are top and bottom
feedback resistor, NS and NA are numbers of
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⎞ NS
⎟⎟ ×
− VD
⎠ NA
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ACT361
Rev PrD, 28-May-09
FUNCTIONAL DESCRIPTION CONT’D
2
transformer secondary and auxiliary turns, and VD
is the rectifier diode forward drop voltage at
approximately 0.1A bias.
IOUTCC =
⎛ 0.4V × 0.9 ⎞ ⎛ η × fSW
1
⎟⎟ × ⎜⎜
× LP × ⎜⎜
2
⎝ RCS
⎠ ⎝ VOUTCV
⎞
⎟⎟
⎠
(2)
The constant current operation typically extends
down to lower than 40% of nominal output voltage
regulation.
Standby (No Load) Mode
In no load standby mode, the ACT361 oscillator
frequency is further reduced to a minimum
frequency while the current pulse is reduced to a
minimum level to minimize standby power. The
actual minimum switching frequency is
programmable with an output preload resistor.
Primary Inductance Compensation
The ACT361 integrates a built-in proprietary
(patent-pending) primary inductance compensation
circuit to maintain constant current regulation
despite variations in transformer manufacturing.
The compensated range is ±7%.
Loop Compensation
The ACT361 integrates loop compensation circuitry
for simplified application design, optimized transient
response, and minimal external components.
Primary Inductor Current Limit Compensation
The ACT361 integrates a primary inductor peak
current limit compensation circuit to achieve
constant input power over line and load ranges.
Output Cable Resistance Compensation
The ACT361 provides programmable output cable
resistance compensation during constant voltage
regulation, monotonically adding an output voltage
correction up to predetermined percentage at full
power. There are four levels to program the output
cable compensation by connecting a resistor (R4 in
Figure 2) from the SW pin to VDD pin. The
percentage at full power is programmable to be 3%,
6%, 9% or 12%, and by using a resistor value of
330k, 160k, 82k or 39k respectively. If there is no
resistor connection, there is no cord compensation.
Protection
The ACT361 incorporates multiple protection
functions including over-voltage, over-current and
over-temperature.
Output Short Circuit Protection
When the secondary side output is short circuited,
the ACT361 enters hiccup mode operation. In this
condition, the VDD voltage drops below the VDDOFF
threshold and the auxiliary supply voltage
collapses. This turns off the ACT361 and causes it
to restart. This hiccup behavior continues until the
short circuit is removed.
This feature allows for better output voltage
accuracy by compensating for the output voltage
droop due to the output cable resistance.
Constant Current (CC) Mode Operation
Output Over Voltage Protection
The ACT361 includes output over-voltage
protection circuitry, which shuts down the IC when
the output voltage is 40% above the normal
regulation voltage for 4 consecutive switching
cycles. The ACT361 enters hiccup mode when an
output over voltage fault is detected.
When the secondary output current reaches a level
set by the internal current limiting circuit, the
ACT361 enters current limit condition and causes
the secondary output voltage to drop. As the output
voltage decreases, so does the flyback voltage in a
proportional manner. An internal current shaping
circuitry adjusts the switching frequency based on
the flyback voltage so that the transferred power
remains proportional to the output voltage, resulting
in a constant secondary side output current profile.
The energy transferred to the output during each
switching cycle is ½(LP × ILIM2) × η, where LP is the
transformer primary inductance, ILIM is the primary
peak current, and η is the conversion efficiency.
From this formula, the constant output current can
be derived:
Over Temperature Shutdown
The thermal shutdown circuitry detects the ACT361
die temperature. The typical over temperature
threshold is 150°C with 20°C hysteresis. When the
die temperature rises above this threshold the
ACT361 is disabled and remains disabled until the
die temperature falls by 20°C, at which point the
ACT361 is re-enabled.
where fSW is the switching frequency and VOUTCV is
the nominal secondary output voltage.
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ACT361
Rev PrD, 28-May-09
When the transistor is turned off, the voltage on the
transistor’s collector consists of the input voltage
and the reflected voltage from the transformer’s
secondary winding. There is a ringing on the rising
top edge of the flyback voltage due to the leakage
inductance of the transformer. This ringing is
clamped by a RCD network if it is used. Design this
clamped voltage as 50V below the breakdown of
the NPN transistor. The flyback voltage has to be
considered with selection of the maximum reverse
voltage rating of secondary rectifier diode. If a 40V
Schottky diode is used, then the flyback voltage can
be calculated:
TYPICAL APPLICATION
Design Example
The design example below gives the procedure for
a DCM flyback converter using the ACT361. Refer
to Application Circuit in Figure 2, the design for a
charger application starts with the following
specification:
Input Voltage Range
85VAC − 265VAC, 50/60Hz
Output Power
3.5W
Output Voltage
5.0V
OCP Current
0.78A
VRO =
The operation for the circuit shown in Figure 2 is as
follows: the rectifier bridge D1−D4 and the capacitor
C1/C2 convert the AC line voltage to DC. This
voltage supplies the primary winding of the
transformer T1 and the startup resistor R1/R2. The
primary power current path is formed by the
transformer’s primary winding, the NPN transistor,
the ACT361 internal MOSFET and the current
sense resistor R7. The resistor R6 and capacitor C4
create a snubber clamping network that protects Q1
from voltage spikes due to the transformer primary
winding leakage inductance. The network
consisting of capacitor C3 and diode D5 provides a
VDD supply voltage for ACT361 from the auxiliary
winding of the transformer. C3 is the decoupling
capacitor of the supply voltage and energy storage
component for startup. The diode D7 and the
capacitor C7 rectifies and filters the output voltage.
The resistor divider consisting of R8 and R9
programs the output voltage.
where VD is the Schottky diode forward voltage,
VDREV is the maximum reverse voltage rating of the
diode and VOUTCV is the output voltage.
The maximum duty cycle is set to be 40% at low
line voltage 85VAC and the circuit efficiency is
estimated to be 72%. Then the maximum average
input current is:
IIN =
I PK =
= 2 × 85 2 −
1
− 3.5 ms )
2 × 50
≈ 90V
75% × 2 × 4.7 μF
VINDCMAX = 2 × VACMAX = 2 × 265 = 375V
LP =
(7)
VINDCMAX × DMAX
90 × 40%
= 2.8 mH
=
I PK × fSW
300 mA × 42 kHz
(8)
The primary to secondary turns ratio NP/NS:
VRO
NP
75
=
=
= 14
NS VOUTCV + VD 5 + 0.37
(9)
The auxiliary to secondary turns ratio NA/NS:
(10)
An EE16 transformer gapped core with an effective
inductance ALE of 100nH/T2 is selected. The
number of turns of the primary winding is:
(3)
NP =
(4)
LP
2.8 mH
=
= 168
ALE
100 nH / T 2
(11)
The number of turns of secondary and auxiliary
windings can be derived accordingly:
NS =
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(6)
The primary inductance of the transformer:
where η is the estimated circuit efficiency, fL is the
line frequency, tC is the estimated rectifier
conduction time, CIN is empirically selected to be
2 × 4.7µF electrolytic capacitors based on the
3µF/W rule of thumb.
Innovative PowerTM
2 × I IN 2 × 60
=
= 300 mA
DMAX
40 %
NA
VDD + VD
14 + 0.37
=
=
= 2.53
NS VOUTCV + VD + VCODE 5 + 0.37 + 0.3
1
− tC )
2fL
η × CIN
2POUT (
2 × 3.5(
VOUTCV × IOUTCC
5 × 0.78
= 60 mA
=
VINDCMIN × η
90 × 72 %
The maximum input primary peak current:
The minimum and maximum DC input voltages can
be calculated:
2
−
VINDCMIN = 2VACMIN
VINDCMAX × (VOUTCV + VD ) 375 × ( 5 + 0.37 )
= 74.6V (5)
=
VDREV − VOUTCV
40 × 0.8 − 5
NS
1
× NP =
× 168 = 12
NP
14
(12)
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ACT361
Rev PrD, 28-May-09
TYPICAL APPLICATION CONT’D
NA =
NA
× N S = 2 .53 × 12 = 30
NS
(13)
The current sense resistance (R7) determines the
current limit value based on the following equation:
RCS =
VCSLIM × 0.9 0.4V × 0.9
=
= 1 .2 Ω
I PK
300 mA
(14)
The voltage feedback resistors are selected
according to the design. The upper feedback
resistor is a fixed value determined by the ACT361
design as 53.6k. The lower feedback resistor is
selected as:
RFB2 =
=
VFB
(VOUTCV + VD )
NA
− VFB
NS
RFB1
2.21
× 53.6 = 10.5 k
( 5 + 0.37 ) × 2.53 − 2.21
(15)
When selecting the output capacitor, a low ESR
electrolytic capacitor is recommended to minimize
ripple from the current ripple. The approximate
equation for the output capacitance value is given
by:
COUT =
IOUTCC
0.7
=
= 310 μF
FSW ×VRIPPLE 45 kHz × 50mV
(16)
A 470µF electrolytic capacitors are used to keep
the ripple small.
PCB Layout Guideline
Good PCB layout is critical to have optimal
performance. Decoupling capacitor (C3), current
sense resistor (R7) and feedback resistor (R8/R9)
should be placed close to VDD, CS and FB pins
respectively. There are two main power path loops.
One is formed by C1/C2, primary winding, NPN
transistor and the ACT361. The other is the
secondary winding, rectifier D7 and output
capacitors (C7/C8). Keep these loop areas as small
as possible. Connect high current ground returns,
the input capacitor ground lead, and the ACT361 G
pin to a single point (star ground configuration).
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ACT361
Rev PrD, 28-May-09
Figure 2:
Universal VAC Input, 5V/0.7A Output Charger
L1
FR1
L
T1
R1
D4
D1
VO
R2
D3
D2
+
C1
+
C2
R10
D7
D5
R11
C7
+
Q1
N
GND
R4
R8
BD
R5
VDD
SW
ACT361
G
FB
CS
R7
C3
R9
Table 1:
ACT361 Bill of Materials
ITEM
REFERENCE
1
U1
2
C1, C2
3
DESCRIPTION
QTY
MANUFACTURER
IC, ACT361US-T, SOT23-6
1
Active-Semi
Capacitor, Electrolytic, 4.7µF/400V, 8 × 12mm
2
KSC
C3
Capacitor, Ceramic, 2.2µF/35V, 1206, SMD
1
POE
4
C7
Capacitor, Electrolytic, 470µF/10V, 8 × 12mm
1
KSC
5
D1-D4
Diode, Rectifier, 1000V/1A, 1N4007, DO-41
4
Good-Ark
6
D5
Diode, Ultra Fast, FR102,100V/1.0A, DO-41
1
Good-Ark
7
D7
Diode, Schottky, 40V/2A, SB240, DO-15
1
Good-Ark
8
L1
Axial Inductor, 1.5mH, 0410, Dip
1
Amode Tech
9
Q1
Transistor, NPN, 700V,1.5A, KSB13003AR, TO-92
1
Semi How
10
RF1
Fusible Resistor, 1W, 10Ω, 5%
1
TY-OHM
11
R1, R2
Chip Resistor, 10MΩ, 1206, 5%
2
TY-OHM
12
R4
Chip Resistor, 162k, 0805, 5%
1
TY-OHM
13
R5
Chip Resistor, 22Ω, 0603, 5%
1
TY-OHM
14
R7
Chip Resistor, 1.18Ω, 1206, 5%
1
TY-OHM
15
R8
Chip Resistor, 53.6k, 0805, 1%
1
TY-OHM
16
R9
Chip Resistor, 143k, 10.5k, 1%
1
TY-OHM
17
R10
Chip Resistor, 10Ω, 0805, 5%
1
TY-OHM
18
R11
Chip Resistor, 1.1k, 0805, 5%
1
TY-OHM
19
T1
Transformer, LP = 2.8mH±7%, EE16
1
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ACT361
Rev PrD, 28-May-09
PACKAGE OUTLINE
SOT23-6 PACKAGE OUTLINE AND DIMENSIONS
D
θ
0.2
SYMBOL
E
E1
c
e
A
A1
A2
e1
DIMENSION IN
MILLIMETERS
DIMENSION IN
INCHES
MIN
MAX
MIN
MAX
A
1.050
1.250
0.041
0.049
A1
0.000
0.100
0.000
0.004
A2
1.050
1.150
0.041
0.045
b
0.300
0.500
0.012
0.020
c
0.100
0.200
0.004
0.008
D
2.820
3.020
0.111
0.119
E
1.500
1.700
0.059
0.067
E1
2.650
2.950
0.104
0.116
L
b
e
e1
L
0.950 TYP
1.800
2.000
0.700 REF
0.037 TYP
0.071
0.079
0.028 REF
L1
0.300
0.600
0.012
0.024
θ
0°
8°
0°
8°
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product to make sure that it is suitable for their applications. Active-Semi products are not intended or authorized for use
as critical components in life-support devices or systems. Active-Semi, Inc. does not assume any liability arising out of
the use of any product or circuit described in this datasheet, nor does it convey any patent license.
Active-Semi and its logo are trademarks of Active-Semi, Inc. For more information on this and other products, contact
sales@active-semi.com or visit http://www.active-semi.com. For other inquiries, please send to:
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ActivePSRTM is a trademark of Active-Semi.