To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Renesas Technology Home Page: http://www.renesas.com Renesas Technology Corp. Customer Support Dept. April 1, 2003 Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein. HM66AQB36104/HM66AQB18204 HM66AQB9404/HM66AQB8404 TM 36-Mbit QDR II SRAM 4-word Burst ADE-203-1331B (Z) Preliminary Rev. 0.2 Jan. 14, 2003 Description The HM66AQB36104 is a 1,048,576-word by 36-bit, the HM66AQB18204 is a 2,097,152-word by 18-bit, the HM66AQB9404 is a 4,194,304-word by 9-bit, and the HM66AQB8404 is a 4,194,304-word by 8-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS sixtransistor memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and K) and are latched on the positive edge of K and K. These products are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration. These products are packaged in 165-pin plastic FBGA package. Note: QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, Micron Technology, Inc., NEC, Samsung, and Hitachi. Preliminary: The specifications of this device are subject to change without notice. Please contact your nearest Hitachi’s Sales Dept. regarding specifications. HM66AQB36104/18204/9404/8404 Features • 1.8 V ± 0.1 V power supply for core (VDD) • 1.4 V to VDD power supply for I/O (VDDQ) • DLL circuitry for wide output data valid window and future frequency scaling • Separate independent read and write data ports with concurrent transactions • 100% bus utilization DDR read and write operation • Four-tick burst for reduced address frequency • Two input clocks (K and K) for precise DDR timing at clock rising edges only • Two output clocks (C and C) for precise flight time and clock skew matching-clock and data delivered together to receiving device • Internally self-timed write control • Clock-stop capability with µs restart • User programmable impedance output • Fast clock cycle time: 3.0 ns (333 MHz)/3.3 ns (300 MHz)/4.0 ns (250 MHz)/ 5.0 ns (200 MHz)/6.0 ns (167 MHz) • Simple control logic for easy depth expansion • JTAG boundary scan Ordering Information Type No. Organization Cycle time Clock frequency Package HM66AQB36104BP-30 HM66AQB36104BP-33 HM66AQB36104BP-40 HM66AQB36104BP-50 HM66AQB36104BP-60 1-M word × 36-bit 3.0 ns 3.3 ns 4.0 ns 5.0 ns 6.0 ns 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz Plastic FBGA 165-pin (BP-165A) HM66AQB18204BP-30 HM66AQB18204BP-33 HM66AQB18204BP-40 HM66AQB18204BP-50 HM66AQB18204BP-60 2-M word × 18-bit 3.0 ns 3.3 ns 4.0 ns 5.0 ns 6.0 ns 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz HM66AQB9404BP-30 HM66AQB9404BP-33 HM66AQB9404BP-40 HM66AQB9404BP-50 HM66AQB9404BP-60 4-M word × 9-bit 3.0 ns 3.3 ns 4.0 ns 5.0 ns 6.0 ns 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz HM66AQB8404BP-30 HM66AQB8404BP-33 HM66AQB8404BP-40 HM66AQB8404BP-50 HM66AQB8404BP-60 4-M word × 8-bit 3.0 ns 3.3 ns 4.0 ns 5.0 ns 6.0 ns 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz Rev.0.2, Jan. 2003, page 2 of 31 HM66AQB36104/18204/9404/8404 Pin Arrangement (HM66AQB36104) 165PIN-BGA 1 2 3 4 5 6 7 8 9 10 11 A CQ VSS NC W BW2 K BW1 R SA NC CQ B Q27 Q18 D18 SA BW3 K BW0 SA D17 Q17 Q8 C D27 Q28 D19 VSS SA NC SA VSS D16 Q7 D8 D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7 E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6 F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5 G D30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5 H DOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J D31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4 K Q32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3 L Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2 M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2 N D34 D26 Q25 VSS SA SA SA VSS Q10 D9 D1 P Q35 D35 Q26 SA SA C SA SA Q9 D0 Q0 R TDO TCK SA SA SA C SA SA SA TMS TDI 7 8 9 10 11 (Top view) Pin Arrangement (HM66AQB18204) 165PIN-BGA 1 2 3 4 5 6 A CQ VSS B NC Q9 SA W BW1 K NC R SA NC CQ D9 SA NC K BW0 SA NC NC Q8 C NC NC D10 VSS SA NC SA VSS NC Q7 D8 D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7 E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6 F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5 G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5 H DOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4 K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3 L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2 M NC NC D16 VSS VSS VSS VSS VSS NC Q1 D2 N NC D17 Q16 VSS SA SA SA VSS NC NC D1 P NC NC Q17 SA SA C SA SA NC D0 Q0 R TDO TCK SA SA SA C SA SA SA TMS TDI (Top view) Rev.0.2, Jan. 2003, page 3 of 31 HM66AQB36104/18204/9404/8404 Pin Arrangement (HM66AQB9404) 165PIN-BGA 1 2 3 4 5 6 A CQ VSS B NC NC C NC NC NC VSS SA D NC D4 NC VSS VSS E NC NC Q4 VDDQ VSS VSS F NC NC NC VDDQ VDD VSS 7 8 9 10 11 SA W NC K NC R NC SA NC K BW SA SA SA CQ NC NC Q3 NC SA VSS NC NC D3 VSS VSS VSS NC NC NC VSS VDDQ NC D2 Q2 VDD VDDQ NC NC NC G NC D5 Q5 VDDQ VDD VSS VDD VDDQ NC NC NC H DOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC NC VDDQ VDD VSS VDD VDDQ NC Q1 D1 K NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC L NC Q6 D6 VDDQ VSS VSS VSS VDDQ NC NC Q0 M NC NC NC VSS VSS VSS VSS VSS NC NC D0 N NC D7 NC VSS SA SA SA VSS NC NC NC P NC NC Q7 SA SA C SA SA NC D8 Q8 R TDO TCK SA SA SA C SA SA SA TMS TDI (Top view) Pin Arrangement (HM66AQB8404) 165PIN-BGA 1 2 3 4 5 6 7 8 9 10 11 A CQ VSS SA W NW1 K NC R SA SA CQ B NC NC NC SA NC K NW0 SA NC NC Q3 C NC NC NC VSS SA NC SA VSS NC NC D3 D NC D4 NC VSS VSS VSS VSS VSS NC NC NC E NC NC Q4 VDDQ VSS VSS VSS VDDQ NC D2 Q2 F NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC G NC D5 Q5 VDDQ VDD VSS VDD VDDQ NC NC NC H DOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC NC VDDQ VDD VSS VDD VDDQ NC Q1 D1 K NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC L NC Q6 D6 VDDQ VSS VSS VSS VDDQ NC NC Q0 M NC NC NC VSS VSS VSS VSS VSS NC NC D0 N NC D7 NC VSS SA SA SA VSS NC NC NC P NC NC Q7 SA SA C SA SA NC NC NC R TDO TCK SA SA SA C SA SA SA TMS TDI (Top view) Rev.0.2, Jan. 2003, page 4 of 31 HM66AQB36104/18204/9404/8404 Pin Descriptions Name I/O type Descriptions SAn Input Synchronous address inputs: These inputs are registered and must meet the setup and hold times around the rising edge of K. Ball 2A is reserved for the next higher-order address input on future devices. All transactions operate on burst-of-four words (two clock periods of bus activity). These inputs are ignored when device is deselected. R Input Synchronous read: When low, this input causes the address inputs to be registered and a READ cycle to be initiated. This input must meet setup and hold times around the rising edge of K, and is ignored on the subsequent rising edge of K. W Input Synchronous write: When low, this input causes the address inputs to be registered and a WRITE cycle to be initiated. This input must meet setup and hold times around the rising edge of K, and is ignored on the subsequent rising edge of K. NWn BW BWn Input Synchronous byte writes (nibble writes on ×8): When low, these inputs cause their respective byte or nibble to be registered and written during WRITE cycles. These signals must meet setup and hold times around the rising edges of K and K for each of two rising edges comprising the WRITE cycle. See Byte Write Truth Table for signal to data relationship. K, K Input Input clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data on the rising edge of K and the rising edge of K. K is ideally 180 degrees out of phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges. C, C Input Output clock: This clock pair provides a user-controlled means of tuning device output data. The rising edge of C is used as the output timing reference for second and fourth output data. The rising edge of C is used as the output reference for first and third output data. Ideally, C is 180 degrees out of phase with C. C and C may be tied high to force the use of K and K as the output reference clocks instead of having to provide C and C clocks. If tied high, C and C must remain high and not to be toggled during device operation. DOFF Input DLL disable: When low, this input causes the DLL to be bypassed for stable, low frequency operation. ZQ Input Output impedance matching input: This input is used to tune the device outputs to the system data bus impedance. Q and CQ output impedance are set to 0.2 × RQ, where RQ is a resistor from this ball to ground. Alternately, this ball can be connected directly to VDDQ, which enables the minimum impedance mode. This ball cannot be connected directly to VSS or left unconnected. TMS TDI Input IEEE1149.1 test inputs: 1.8 V I/O levels. These balls may be left not connected if the JTAG function is not used in the circuit. TCK Input IEEE1149.1 clock input: 1.8 V I/O levels. This ball must be tied to VSS if the JTAG function is not used in the circuit. Rev.0.2, Jan. 2003, page 5 of 31 HM66AQB36104/18204/9404/8404 Name I/O type Descriptions D0 to Dn Input Synchronous data inputs: Input data must meet setup and hold times around the rising edges of K and K during WRITE operations. See Pin Arrangement figures for ball site location of individual signals. The ×8 device uses D0 to D7. Remaining signals are NC. The ×9 device uses D0 to D8. Remaining signals are NC. The ×18 device uses D0 to D17. Remaining signals are NC. The ×36 device uses D0 to D35. NC signals are read in the JTAG scan chain as the logic level applied to the ball site. CQ, CQ Output Synchronous echo clock outputs: The edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. These signals run freely and do not stop when Q tri-states. TDO Output IEEE 1149.1 test output: 1.8 V I/O level. Q0 to Qn Output Synchronous data outputs: Output data is synchronized to the respective C and C, or to the respective K and K rising edges if C and C are tied high. This bus operates in response to R commands. See Pin Arrangement figures for ball site location of individual signals. The ×8 device uses Q0 to Q7. Remaining signals are NC. The ×9 device uses Q0 to Q8. Remaining signals are NC. The ×18 device uses Q0 to Q17. Remaining signals are NC. The ×36 device uses Q0 to Q35. NC signals are read in the JTAG scan chain as the logic level applied to the ball site. VDD Supply Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions for range. VDDQ Supply Power supply: Isolated output buffer supply. Nominally 1.5 V. 1.8 V is also permissible. See DC Characteristics and Operating Conditions for range. VSS Supply Power supply: Ground VREF HSTL input reference voltage: Nominally VDDQ/2. Provides a reference voltage for the input buffers. NC No connect: These signals are internally connected and appear in the JTAG scan chain as the logic level applied to the ball sites. These signals may be connected to ground to improve package heat dissipation. Note: 1. All power supply and ground balls must be connected for proper operation of the device. Rev.0.2, Jan. 2003, page 6 of 31 HM66AQB36104/18204/9404/8404 Block Diagram (HM66AQB36104) Address 18 R Address registry and logic W 18 K W BW0 MUX BW1 72 Output buffer 144 Output select 72 36 Output register 72 Memory array Sense amps 36 72 Write driver BW3 D0 to D35 Data registry and logic Write register BW2 2 Q0 to Q35 CQ, CQ R MUX K K C K C, C or K, K Block Diagram (HM66AQB18204) Address 19 R Address registry and logic W 19 K W BW0 MUX 36 Output buffer 36 18 72 Output select 36 Memory array Sense amps R 36 Write driver D0 to D17 Data registry and logic Write register 18 Output register BW1 2 Q0 to Q17 CQ, CQ MUX K K K C C, C or K, K Rev.0.2, Jan. 2003, page 7 of 31 HM66AQB36104/18204/9404/8404 Block Diagram (HM66AQB9404) Address 20 R Address registry and logic W 20 K W BW MUX 18 Output buffer 18 36 Output select Memory array 9 Output register 18 Sense amps R 18 Write driver D0 to D8 Data registry and logic Write register 9 2 K K CQ, CQ MUX K Q0 to Q8 C, C or K, K C Block Diagram (HM66AQB8404) Address 20 R Address registry and logic W 20 K W NW0 MUX 16 Output buffer 16 8 32 Output select 16 Memory array Sense amps R 16 Write driver D0 to D7 Data registry and logic Write register 8 Output register NW1 2 Q0 to Q7 CQ, CQ MUX K K K Rev.0.2, Jan. 2003, page 8 of 31 C C, C or K, K HM66AQB36104/18204/9404/8404 Truth Table Operation WRITE cycle K L→H R *7 H W L *8 Load address, input write data on two consecutive K and K rising edges READ cycle L→H L *8 × Load address, read data on two consecutive C and C rising edges D or Q Data in Input data DA(A+0) DA(A+1) DA(A+2) DA(A+3) Input clock K(t+1)↑ K(t+1)↑ K(t+2)↑ K(t+2)↑ Output QA(A+0) data QA(A+1) QA(A+2) QA(A+3) Output C(t+1)↑ clock C(t+2)↑ C(t+2)↑ C(t+3)↑ Data out NOP (No operation) L→H H H D = × or Q = High-Z STANDBY (Clock stopped) Stopped × × Previous state Notes: 1. H: high level, L: low level, ×: don’t care, ↑: rising edge. 2. Data inputs are registered at K and K rising edges. Data outputs are delivered at C and C rising edges, except if C and C are high, then data outputs are delivered at K and K rising edges. 3. R and W must meet setup/hold times around the rising edges (low to high) of K and are registered at the rising edge of K. 4. This device contains circuitry that will ensure the outputs will be in high-Z during power-up. 5. Refer to state diagram and timing diagrams for clarification. 6. It is recommended that (K) = /(K) = (C) = /(C) when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 7. If this signal was low to initiate the previous cycle, this signal becomes a “don’t care” for this operation; however, it is strongly recommended that this signal be brought high, as shown in the truth table. 8. This signal was high on previous K clock rising edge. Initiating consecutive READ or WRITE operations on consecutive K clock rising edges is not permitted. The device will ignore the second request. Rev.0.2, Jan. 2003, page 9 of 31 HM66AQB36104/18204/9404/8404 Byte Write Truth Table (HM66AQB36104) Operation K K BW0 BW1 BW2 BW3 Write D0 to D35 L→H 0 0 0 0 L→H 0 0 0 0 L→H 0 1 1 1 L→H 0 1 1 1 Write D0 to D8 Write D9 to D17 Write D18 to D26 Write D27 to D35 Write nothing L→H 1 0 1 1 L→H 1 0 1 1 L→H 1 1 0 1 L→H 1 1 0 1 L→H 1 1 1 0 L→H 1 1 1 0 L→H 1 1 1 1 L→H 1 1 1 1 Notes: 1. H: high level, L: low level, →: rising edge. 2. Assumes a WRITE cycle was initiated. BW0 to BW3 can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied. (HM66AQB18204) Operation K K BW0 BW1 Write D0 to D17 L→H 0 0 L→H 0 0 L→H 0 1 L→H 0 1 L→H 1 0 L→H 1 0 L→H 1 1 L→H 1 1 Write D0 to D8 Write D9 to D17 Write nothing Notes: 1. H: high level, L: low level, →: rising edge. 2. Assumes a WRITE cycle was initiated. BW0 and BW1 can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied. Rev.0.2, Jan. 2003, page 10 of 31 HM66AQB36104/18204/9404/8404 (HM66AQB9404) Operation K K BW Write D0 to D8 L→H 0 L→H 0 L→H 1 L→H 1 Write nothing Notes: 1. H: high level, L: low level, →: rising edge. 2. Assumes a WRITE cycle was initiated. BW can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied. (HM66AQB8404) Operation K K NW0 NW1 Write D0 to D7 L→H 0 0 L→H 0 0 L→H 0 1 L→H 0 1 L→H 1 0 L→H 1 0 L→H 1 1 L→H 1 1 Write D0 to D3 Write D4 to D7 Write nothing Notes: 1. H: high level, L: low level, →: rising edge. 2. Assumes a WRITE cycle was initiated. NW0 and NW1 can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied. Rev.0.2, Jan. 2003, page 11 of 31 HM66AQB36104/18204/9404/8404 Bus Cycle State Diagram R=L Always LOAD NEW READ ADDRESS; R_Count = 0; R_Init = 1 R=H Always INCREMENT READ ADDRESS BY TWO *1 R_Init = 0 READ DOUBLE; R_Count = R_Count+2 R = L & R_Count = 4 READ PORT NOP R_Init = 0 R_Count = 2 Supply voltage provided R = H & R_Count = 4 POWER UP W = H & W_Count = 4 Supply voltage provided W = L & W_Count = 4 LOAD NEW WRITE ADDRESS; W_Count = 0 WRITE DOUBLE; W_Count = W_Count+2 Always W=H Always INCREMENT WRITE ADDRESS BY TWO *1 WRITE PORT NOP W_Count = 2 W=L R_Init = 0 Notes: 1. The address is concatenated with two additional internal LSBs to facilitate burst operation. The address order is always fixed as: xxx…xxx+0, xxx…xxx+1, xxx…xxx+2, xxx…xxx+3. Bus cycle is terminated at the end of this sequence (burst count = 4). 2. Read and write state machines can be active simultaneously. Read and write cannot be simultaneously initiated. Read takes precedence. 3. State machine control timing is controlled by K. Rev.0.2, Jan. 2003, page 12 of 31 HM66AQB36104/18204/9404/8404 Absolute Maximum Ratings Parameter Symbol Rating Unit Notes Input voltage on any ball VIN −0.5 to VDD + 0.5 (2.9 V max.) V 1, 4 Input/output voltage VI/O −0.5 to VDDQ + 0.5 (2.9 V max.) V 1, 4 Core supply voltage VDD −0.5 to 2.9 V 1, 4 Output supply voltage VDDQ −0.5 to VDD V 1, 4 Junction temperature Tj +125 (max) °C Storage temperature TSTG −55 to +125 °C Notes: 1. All voltage is referenced to VSS. 2. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted the Operation Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. 3. These CMOS memory circuits have been designed to meet the DC and AC specifications shown in the tables after thermal equilibrium has been established. 4. The following supply voltage application sequence is recommended: VSS, VDD, VDDQ, VREF then VIN. Remember, according to the Absolute Maximum Ratings table, VDDQ is not to exceed 2.9 V, whatever the instantaneous value of VDDQ. Recommended DC Operating Conditions (Ta = 0 to +70°C) Parameter Symbol Min Typ Max Unit Notes Power supply voltage -- core VDD 1.7 1.8 1.9 V Power supply voltage -- I/O VDDQ 1.4 1.5 VDD V Input reference voltage -- I/O VREF 0.68 0.75 0.95 V Input high voltage VIH (DC) VREF + 0.1 VDDQ + 0.3 V 2, 3 Input low voltage VIL (DC) −0.3 VREF − 0.1 V 2, 3 1 Notes: 1. Peak to peak AC component superimposed on VREF may not exceed 5% of VREF. 2. VREF = 0.75 V (typ). 3. Overshoot: VIH (AC) ≤ VDD + 0.7 V for t ≤ tKHKH/2 Undershoot: VIL (AC) ≥ −0.5 V for t ≤ tKHKH/2 Power-up: VIH ≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms During normal operation, VDDQ must not exceed VDD. Control input signals may not have pulse widths less than tKHKL (min) or operate at cycle rates less than tKHKH (min). Rev.0.2, Jan. 2003, page 13 of 31 HM66AQB36104/18204/9404/8404 DC Characteristics (Ta = 0 to +70°C, VDD = 1.8 V ± 0.1 V) HM66AQB36104/HM66AQB18204 HM66AQB9404/HM66AQB8404 -30 Parameter Symbol Typ Operating supply current (READ / WRITE) Standby supply current (NOP) Notes: 1. 2. 3. 4. 5. -33 -40 -50 -60 Max Unit Notes (×8 / ×9 / ×18) IDD TBD 525 475 400 330 280 mA (×36) IDD TBD 710 640 545 445 380 mA (×8 / ×9 / ×18) ISB1 TBD 255 235 200 170 145 mA (×36) TBD 265 245 210 180 155 mA ISB1 All inputs (except ZQ, VREF) are held at either VIH or VIL. IOUT = 0 mA. VDD = VDD max, tKHKH = tKHKH min. Typical values are measured at VDD = 1.8 V, VDDQ = 1.5 V, Ta = +25°C, and tKHKH = 6 ns. Operating supply currents are measured at 100% bus utilization. NOP currents are valid when entering NOP after all pending READ and WRITE cycles are completed. Parameter Symbol Min Input leakage current Max Unit Test conditions Notes ILI −2 2 µA 8 Output leakage current ILO −2 2 µA 9 Output high voltage VOH (Low) VDDQ − 0.2 VDDQ V |IOH| ≤ 0.1 mA 3, 4 VOH VDDQ/2 − 0.08 VDDQ/2 + 0.08 V Notes1 3, 4 VOL (Low) VSS 0.2 V IOL ≤ 0.1 mA 3, 4 VOL VDDQ/2 − 0.08 VDDQ/2 + 0.08 V Notes2 3, 4 Output “High” current IOH (VDDQ/2)/(RQ/5 + 10%) (VDDQ/2)/(RQ/5 − 10%) mA 5, 7 Output “Low” current IOL (VDDQ/2)/(RQ/5 − 10%) (VDDQ/2)/(RQ/5 + 10%) mA 6, 7 Output low voltage Rev.0.2, Jan. 2003, page 14 of 31 HM66AQB36104/18204/9404/8404 Outputs are impedance-controlled. |IOH| = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω. AC load current is higher than the shown DC values. AC I/O curves are available upon request. HSTL outputs meet JEDEC HSTL Class I and Class II standards. Measured at VOH = VDDQ/2 Measured at VOL = VDDQ/2 Output buffer impedance can be programmed by terminating the ZQ ball to VSS through a precision resistor (RQ). The value of RQ is five times the output impedance desired. The allowable range of RQ to guarantee impedance matching with a tolerance of 10% is 250 Ω typical. The total external capacitance of ZQ ball must be less than 7.5 pF. 8. 0 ≤ VIN ≤ VDDQ for all input balls (except VREF, ZQ ball) 9. 0 ≤ VOUT ≤ VDDQ, output disabled. 10. VDDQ = 1.5 V ± 0.1 V Notes: 1. 2. 3. 4. 5. 6. 7. Capacitance (Ta = +25°C, f = 1.0 MHz, VDD = 1.8 V) Parameter Symbol Min Typ Max Unit Test conditions Input capacitance CIN 4 5 pF VIN = 0 V Clock input capacitance CCLK 5 6 pF VCLK = 0 V Input/output capacitance (D, Q) CI/O 6 7 pF VI/O = 0 V Notes: 1. These parameters are sampled and not 100% tested. 2. Parameters tested with RQ = 250 Ω and VDDQ = 1.5 V. Rev.0.2, Jan. 2003, page 15 of 31 HM66AQB36104/18204/9404/8404 AC Characteristics (Ta = 0 to +70°C, VDD = 1.8 V ± 0.1 V) Test Conditions Input waveform (Rise/fall time ≤ 0.3 ns) 1.25 V 0.75 V Test points 0.75 V 0.25 V Output waveform VDDQ/2 Test points VDDQ/2 Output load condition VDDQ/2 0.75 V 50 Ω VREF Zo = 50 Ω SRAM Q 250 Ω ZQ Rev.0.2, Jan. 2003, page 16 of 31 HM66AQB36104/18204/9404/8404 Operating Conditions Parameter Symbol Min Typ Max Unit Notes Input high voltage VIH (AC) VREF + 0.2 V 1, 2, 3 Input low voltage VIL (AC) VREF – 0.2 V 1, 2, 3 Notes: 1. 2. 3. All voltages referenced to VSS (GND). Overshoot: VIH (AC) ≤ VDD + 0.7 V for t ≤ tKHKH/2 Undershoot: VIL (AC) ≥ −0.5 V for t ≤ tKHKH/2 Power-up: VIH ≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms During normal operation, VDDQ must not exceed VDD. R and W signals may not have pulse widths less than tKHKL (min) or operate at cycle rates less than tKHKH (min). To maintain a valid level, the transitioning edge of the input must: a. Sustain a constant slew rate from the current AC level through the target AC level, VIL (AC) or VIH (AC). b. Reach at least the target AC level. c. After the AC target level is reached, continue to maintain at least the target DC level, VIL (DC) or VIH (DC). Rev.0.2, Jan. 2003, page 17 of 31 HM66AQB36104/18204/9404/8404 HM66AQB36104/HM66AQB18204 HM66AQB9404/HM66AQB8404 -30 Parameter Symbol Min -33 -40 -50 -60 Max Min Max Min Max Min Max Min Max Unit Notes Average clock tKHKH cycle time (K, K, C, C) 3.00 3.47 3.30 4.20 4.00 5.25 5.00 6.30 6.00 7.88 ns Clock phase jitter (K, K, C, C) 0.20 0.20 0.20 0.20 0.20 ns Clock high time tKHKL (K, K, C, C) 1.20 1.32 1.60 2.00 2.40 ns Clock low time tKLKH (K, K, C, C) 1.20 1.32 1.60 2.00 2.40 ns Clock to clock tKH/KH (K to K, C to C) 1.35 1.49 1.80 2.20 2.70 ns Clock to clock t/KHKH (K to K, C to C) 1.35 1.49 1.80 2.20 2.70 ns Clock to data tKHCH clock (K to C, K to C) 0 1.30 0 1.45 0 1.80 0 2.30 0 2.80 ns DLL lock time (K, C) tKC var tKC lock 1,024 1,024 1,024 1,024 1,024 Cycle 2 K static to DLL tKC reset 30 reset 30 30 30 30 ns C, C high to output valid tCHQV 0.45 0.45 0.45 0.45 0.50 ns C, C high to output hold tCHQX −0.45 −0.45 −0.45 −0.45 −0.50 ns C, C high to echo clock valid tCHCQV ns 0.45 0.45 0.45 0.45 0.50 3 C, C high to tCHCQX echo clock hold −0.45 −0.45 −0.45 −0.45 −0.50 ns CQ, CQ high to tCQHQV output valid ns 4 CQ, CQ high to tCQHQX output hold −0.25 −0.27 −0.30 −0.35 −0.40 ns 4 C high to output high-Z tCHQZ ns 5 C high to output low-Z tCHQX1 −0.45 ns 5 0.25 0.45 Rev.0.2, Jan. 2003, page 18 of 31 0.27 0.45 −0.45 0.30 0.45 −0.45 0.35 0.45 −0.45 0.40 0.50 −0.50 HM66AQB36104/18204/9404/8404 HM66AQB36104/HM66AQB18204 HM66AQB9404/HM66AQB8404 -30 Parameter Symbol Min -33 -40 -50 -60 Max Min Max Min Max Min Max Min Max Unit Notes Address valid tAVKH to K rising edge 0.40 0.40 0.50 0.60 0.70 ns 1 Control inputs tIVKH valid to K rising edge 0.40 0.40 0.50 0.60 0.70 ns 1 Data-in valid to tDVKH K, K rising edge 0.28 0.30 0.35 0.40 0.50 ns 1 K rising edge to tKHAX address hold 0.40 0.40 0.50 0.60 0.70 ns 1 K rising edge to tKHIX control inputs hold 0.40 0.40 0.50 0.60 0.70 ns 1 tKHDX K, K rising edge to data-in hold 0.28 0.30 0.35 0.40 0.50 ns 1 Notes: 1. This is a synchronous device. All addresses, data and control lines must meet the specified setup and hold times for all latching clock edges. 2. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable. It is recommended that the device is kept inactive during these cycles. 3. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 4. Echo clock is very tightly controlled to data valid / data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guardbands and test setup variations. 5. Transitions are measured ±100 mV from steady-state voltage. 6. At any given voltage and temperature tCHQZ is less than tCHQX1 and tCHQZ less than tCHQV. Remarks: 1. This parameter is sampled. 2. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise noted. 3. Control input signals may not be operated with pulse widths less than tKHKL (min). 4. If C, C are tied high, K, K become the references for C, C timing parameters. 5. VDDQ is +1.5 V DC. Rev.0.2, Jan. 2003, page 19 of 31 HM66AQB36104/18204/9404/8404 Timing Waveforms Read and Write Timing 1 NOP READ 2 3 WRITE READ 4 WRITE 5 NOP 6 7 K tKHKL tKLKH K tKHKH tKH/KH t/KHKH R tIVKH tIVKH tKHIX tKHIX W A0 Address tAVKH A1 tKHAX Data in Data out Qx2 Qx3 tCHQX1 A2 tDVKH tKHDX A3 D10 D11 D12 D13 D30 D31 D32 D33 Q00 Q01 Q02 Q03 Q20 Q21 Q22 Q23 tCHQX tCHQX tDVKH tKHDX tCQHQV tCQHQX tCHQV tCHQV CQ tCHQZ tCHCQX tCHCQV CQ tKHCH tCHCQX tCHCQV C tKHKL tKLKH C tKHKH tKH/KH t/KHKH tKHCH Notes: 1. Q00 refers to output from address A0 + 0. Q01 refers to output from the next internal burst address following A0, i.e., A0 + 1. 2. Outputs are disable (high-Z) one clock cycle after a NOP. 3. In this example, if address A2 = A1, then data Q20 = D10, Q21 = D11. Write data is forwarded immediately as read results. Rev.0.2, Jan. 2003, page 20 of 31 HM66AQB36104/18204/9404/8404 JTAG Specification These products support a limited set of JTAG functions as in IEEE standard 1149.1. Disabling the Test Access Port It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfering with normal operation of the device, TCK must be tied to VSS to preclude mid level inputs. TDI and TMS are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be tied to VDD through a 1kΩ resistor. TDO should be left unconnected. Test Access Port (TAP) Pins Symbol I/O Pin assignments Description TCK 2R Test clock input. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS 10R Test mode select. This is the command input for the TAP controller state machine. TDI 11R Test data input. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction. TDO 1R Test data output. Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. Note: The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high for five rising edges of TCK. The TAP controller state is also reset on SRAM POWER-UP. Rev.0.2, Jan. 2003, page 21 of 31 HM66AQB36104/18204/9404/8404 TAP DC Operating Characteristics (Ta = 0 to +70°C, VDD = 1.8 V ± 0.1 V) Parameter Symbol Min Max Unit Input high voltage VIH 1.3 VDD + 0.3 V Input low voltage VIL −0.3 +0.5 V Conditions Input leakage current ILI −5.0 +5.0 µA 0 V ≤ VIN ≤ VDD Output leakage current ILO −5.0 +5.0 µA 0 V ≤ VIN ≤ VDD, output disabled Output low voltage VOL1 0.2 V IOLC = 100 µA VOL2 0.4 V IOLT = 2 mA VOH1 1.6 V |IOHC| = 100 µA VOH2 1.4 V |IOHT| = 2 mA Output high voltage Notes: 1. All voltages referenced to VSS (GND). 2. Power-up: VIH ≤ VDDQ + 0.3 V and VDD ≤ +1.7 V and VDDQ ≤ +1.4 V for t ≤ 200 ms 3. In “EXTEST” mode and “SAMPLE” mode, VDDQ is nominally 1.5 V. Rev.0.2, Jan. 2003, page 22 of 31 HM66AQB36104/18204/9404/8404 TAP AC Test Condition • Temperature 0°C ≤ Ta ≤ +70°C • Input timing measurement reference levels 0.9 V • Input pulse levels 0 V to 1.8 V • Input rise/fall time ≤ 1.0 ns • Output timing measurement reference levels 0.9 V • Test load termination supply voltage (VTT) 0.9 V • Output load See figures Input waveform 1.8 V 0.9 V Test points 0.9 V 0V Output waveform 0.9 V Test points 0.9 V Output load VTT = 0.9 V 50 Ω Zo = 50 Ω TDO 20 pF External load at test Rev.0.2, Jan. 2003, page 23 of 31 HM66AQB36104/18204/9404/8404 TAP AC Operating Characteristics (Ta = 0 to +70°C, VDD = 1.8 V ± 0.1 V) Parameter Symbol Min Max Unit Test clock cycle time tTHTH 100 ns Test clock high pulse width tTHTL 40 ns Test clock low pulse width tTLTH 40 ns Test mode select setup tMVTH 10 ns Test mode select hold tTHMX 10 ns Capture setup tCS 10 ns 1 Capture hold tCH 10 ns 1 TDI valid to TCK high tDVTH 10 ns TCK high to TDI invalid tTHDX 10 ns TCK low to TDO unknown tTLQX 0 ns TCK low to TDO valid tTLQV 20 ns Note: Note 1. tCS + tCH defines the minimum pause in RAM I/O pad transitions to assure pad data capture. TAP Controller Timing Diagram tTHTH TCK tMVTH tTHTL tTLTH TMS tTHMX tDVTH TDI tTLQV tTHDX TDO tCS tCH tTLQX RAM ADDRESS Test Access Port Registers Register name Length Symbol Instruction register 3 bits IR [2:0] Bypass register 1 bit BP ID register 32 bits ID [31:0] Boundary scan register 109 bits BS [109:1] Rev.0.2, Jan. 2003, page 24 of 31 HM66AQB36104/18204/9404/8404 TAP Controller Instruction Set IR2 IR1 IR0 Instruction Description Notes 0 0 0 EXTEST The EXTEST instruction allows circuitry external to the component package to be tested. Boundary scan register cells at output balls are used to apply test vectors, while those at input balls capture test results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the boundary scan register using the PRELOAD instruction. Thus, during the Update-IR state of EXTEST, the output drive is turned on and the PRELOAD data is driven onto the output balls. 0 0 1 IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in capture-DR mode and places the ID register between the TDI and TDO balls in shiftDR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. 0 1 0 SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z, except CQ, CQ ball) and the boundary register is connected between TDI and TDO when the TAP controller is moved to the shift-DR state. 0 1 1 RESERVED These instructions are not implemented but are reserved for future use. Do not use these instructions. 1 0 0 SAMPLE (-PRELOAD) When the SAMPLE instruction is loaded in the instruction register, moving the TAP controller into the capture-DR state loads the data in the RAMs input and I/O buffers into the boundary scan register. Because the RAM clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state). Although allowing the TAP to SAMPLE metastable input will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the boundary scan register. Moving the controller to shift-DR state then places the boundary scan register between the TDI and TDO balls. 1 0 1 RESERVED 1 1 0 RESERVED 1 1 1 BYPASS 1, 2 The BYPASS instruction is loaded in the instruction register when the bypass register is placed between TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. Notes: 1. Data in output register is not guaranteed if EXTEST instruction is loaded. 2. After performing EXTEST, power-up conditions are required in order to return part to normal operation. Rev.0.2, Jan. 2003, page 25 of 31 HM66AQB36104/18204/9404/8404 ID Register Part Revision number (31:29) Type number (28:12) Vendor JEDEC code (11:1) Start bit (0) HM66AQB36104 000 00010011010101010 00000000111 1 HM66AQB18204 000 00010010010101010 00000000111 1 HM66AQB9404 000 00010000010101010 00000000111 1 HM66AQB8404 000 00010001010101010 00000000111 1 Rev.0.2, Jan. 2003, page 26 of 31 HM66AQB36104/18204/9404/8404 Boundary Scan Order Signal names Signal names Bit # Ball ID ×8 ×9 ×18 ×36 Bit # Ball ID ×8 ×9 ×18 1 6R C C C C 36 10E D2 D2 D6 ×36 D6 2 6P C C C C 37 10D NC NC NC D15 3 6N SA SA SA SA 38 9E NC NC NC Q15 4 7P SA SA SA SA 39 10C NC NC Q7 Q7 5 7N SA SA SA SA 40 11D NC NC D7 D7 6 7R SA SA SA SA 41 9C NC NC NC D16 7 8R SA SA SA SA 42 9D NC NC NC Q16 8 8P SA SA SA SA 43 11B Q3 Q3 Q8 Q8 9 9R SA SA SA SA 44 11C D3 D3 D8 D8 10 11P NC Q8 Q0 Q0 45 9B NC NC NC D17 11 10P NC D8 D0 D0 46 10B NC NC NC Q17 12 10N NC NC NC D9 47 11A CQ CQ CQ CQ 13 9P NC NC NC Q9 48 10A SA SA NC NC 14 10M NC NC Q1 Q1 49 9A SA SA SA SA 15 11N NC NC D1 D1 50 8B SA SA SA SA 16 9M NC NC NC D10 51 7C SA SA SA SA 17 9N NC NC NC Q10 52 6C NC NC NC NC 18 11L Q0 Q0 Q2 Q2 53 8A R R R R 19 11M D0 D0 D2 D2 54 7A NC NC NC BW1 20 9L NC NC NC D11 55 7B NW0 BW BW0 BW0 21 10L NC NC NC Q11 56 6B K K K K 22 11K NC NC Q3 Q3 57 6A K K K K 23 10K NC NC D3 D3 58 5B NC NC NC BW3 24 9J NC NC NC D12 59 5A NW1 NC BW1 BW2 25 9K NC NC NC Q12 60 4A W W W W 26 10J Q1 Q1 Q4 Q4 61 5C SA SA SA SA 27 11J D1 D1 D4 D4 62 4B SA SA SA SA 28 11H ZQ ZQ ZQ ZQ 63 3A SA SA SA NC 29 10G NC NC NC D13 64 2A VSS VSS VSS VSS 30 9G NC NC NC Q13 65 1A CQ CQ CQ CQ 31 11F NC NC Q5 Q5 66 2B NC NC Q9 Q18 32 11G NC NC D5 D5 67 3B NC NC D9 D18 33 9F NC NC NC D14 68 1C NC NC NC D27 34 10F NC NC NC Q14 69 1B NC NC NC Q27 35 11E Q2 Q2 Q6 Q6 70 3D NC NC Q10 Q19 Rev.0.2, Jan. 2003, page 27 of 31 HM66AQB36104/18204/9404/8404 Signal names Signal names Bit # Ball ID ×8 ×9 ×18 ×36 Bit # Ball ID ×8 ×9 ×18 ×36 71 3C NC NC D10 D19 91 2L Q6 Q6 Q15 Q24 72 1D NC NC NC D28 92 3L D6 D6 D15 D24 73 2C NC NC NC Q28 93 1M NC NC NC D33 74 3E Q4 Q4 Q11 Q20 94 1L NC NC NC Q33 75 2D D4 D4 D11 D20 95 3N NC NC Q16 Q25 76 2E NC NC NC D29 96 3M NC NC D16 D25 77 1E NC NC NC Q29 97 1N NC NC NC D34 78 2F NC NC Q12 Q21 98 2M NC NC NC Q34 79 3F NC NC D12 D21 99 3P Q7 Q7 Q17 Q26 80 1G NC NC NC D30 100 2N D7 D7 D17 D26 81 1F NC NC NC Q30 101 2P NC NC NC D35 82 3G Q5 Q5 Q13 Q22 102 1P NC NC NC Q35 83 2G D5 D5 D13 D22 103 3R SA SA SA SA 84 1H DOFF DOFF DOFF DOFF 104 4R SA SA SA SA 85 1J NC NC NC D31 105 4P SA SA SA SA 86 2J NC NC NC Q31 106 5P SA SA SA SA 87 3K NC NC Q14 Q23 107 5N SA SA SA SA 88 3J NC NC D14 D23 108 5R SA SA SA SA 89 2K NC NC NC D32 109 INTER- INTER- INTER- INTERNAL NAL NAL NAL 90 1K NC NC NC Q32 Note: In boundary scan mode, 1. Clock balls (K / K, C / C) are referenced to each other and must be at opposite logic levels for reliable operation. 2. CQ and CQ data are synchronized to the respective C and C. 3. If C and C tied high, CQ is generated with respect to K and CQ is generated with respect to K. Rev.0.2, Jan. 2003, page 28 of 31 HM66AQB36104/18204/9404/8404 TAP Controller State Diagram 1 Test-LogicReset 0 0 Run-Test/ Idle 1 1 SelectDR-Scan 0 1 0 1 Capture-DR Capture-IR 0 0 Shift-DR Shift-IR 0 1 1 1 Exit1-IR 0 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 1 0 1 Exit1-DR 0 1 SelectIR-Scan Update-IR 0 1 0 Notes: The value adjacent to each state transition in this figure represents the signal present at TMS at the time of a rising edge at TCK. No matter what the original state of the controller, it will enter Test-Logic-Reset when TMS is held high for at least five rising edges of TCK. Rev.0.2, Jan. 2003, page 29 of 31 HM66AQB36104/18204/9404/8404 Package Dimensions HM66AQB36104/18204/9404/8404BP (BP-165A) Unit: mm 14 × 1.00 Preliminary 15.00 ± 0.20 165 × φ0.50 ± 0.05 11 10 9 8 7 6 5 4 3 2 1 17.00 ± 0.20 A B C D E F G H J K L M N P R 10 × 1.00 Rev.0.2, Jan. 2003, page 30 of 31 C 0.40 ± 0.06 0.10 C 1.44 ± 0.10 0.25 C Hitachi Code JEDEC JEITA Mass (reference value) BP-165A – – – HM66AQB36104/18204/9404/8404 Disclaimer 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Sales Offices Hitachi, Ltd. Semiconductor & Integrated Circuits Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: (03) 3270-2111 Fax: (03) 3270-5109 URL http://www.hitachisemiconductor.com/ For further information write to: Hitachi Semiconductor (America) Inc. 179 East Tasman Drive San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe Ltd. Electronic Components Group Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Ltd. Hitachi Tower 16 Collyer Quay #20-00 Singapore 049318 Tel : <65>-6538-6533/6538-8577 Fax : <65>-6538-6933/6538-3877 URL : http://semiconductor.hitachi.com.sg Hitachi Europe GmbH Electronic Components Group Dornacher Str 3 D-85622 Feldkirchen Postfach 201, D-85619 Feldkirchen Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Asia Ltd. (Taipei Branch Office) 4/F, No. 167, Tun Hwa North Road Hung-Kuo Building Taipei (105), Taiwan Tel : <886>-(2)-2718-3666 Fax : <886>-(2)-2718-8180 Telex : 23222 HAS-TP URL : http://semiconductor.hitachi.com.tw Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel : <852>-2735-9218 Fax : <852>-2730-0281 URL : http://semiconductor.hitachi.com.hk Copyright © Hitachi, Ltd., 2002. All rights reserved. Printed in Japan. Colophon 7.0 Rev.0.2, Jan. 2003, page 31 of 31