ETC NTMD2P01R2

NTMD2P01R2
Product Preview
Power MOSFET
-2.3 Amps, -16 Volts
Dual SO–8 Package
Features
•
•
•
•
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High Efficiency Components in a Single SO–8 Package
High Density Power MOSFET with Low RDS(on)
Logic Level Gate Drive
SO–8 Surface Mount Package,
Mounting Information for SO–8 Package Provided
–2.3 AMPERES
–16 VOLTS
100 m @ VGS = –4.5 V
Applications
• Power Management in Portable and Battery–Powered Products, i.e.:
P–Channel
Computers, Printers, PCMCIA Cards, Cellular and Cordless Telephones
D
MOSFET MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
VDSS
–16
V
Gate–to–Source Voltage – Continuous
VGS
10
V
Thermal Resistance – Junction–to–Ambient
(Note 1)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ TA = 25°C
Continuous Drain Current @ TA = 100°C
Pulsed Drain Current (Note 4)
RθJA
PD
ID
ID
IDM
175
0.71
–2.3
–1.45
–9.0
°C/W
W
A
A
A
Thermal Resistance – Junction–to–Ambient
(Note 2)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ TA = 25°C
Continuous Drain Current @ TA = 100°C
Pulsed Drain Current (Note 4)
RθJA
PD
ID
ID
IDM
105
1.19
–2.97
–1.88
–12
°C/W
W
A
A
A
Thermal Resistance – Junction–to–Ambient
(Note 3)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ TA = 25°C
Continuous Drain Current @ TA = 100°C
Pulsed Drain Current (Note 4)
RθJA
PD
ID
ID
IDM
62.5
2.0
–3.85
–2.43
–15
°C/W
W
A
A
A
TJ, Tstg
–55 to
+150
°C
EAS
350
mJ
Operating and Storage
Temperature Range
Single Pulse Drain–to–Source Avalanche
Energy – Starting TJ = 25°C
(VDD = –16 Vdc, VGS = –4.5 Vdc, Peak IL
= –5.0 Apk, L = 28 mH, RG = 25 Ω)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
TL
°C
260
1. Minimum FR–4 or G–10 PCB, Steady State.
2. Mounted onto a 2″ square FR–4 Board (1″ sq. 2 oz Cu 0.06″ thick single
sided), Steady State.
3. Mounted onto a 2″ square FR–4 Board (1″ sq. 2 oz Cu 0.06″ thick single
sided), t ≤ 10 seconds.
4. Pulse Test: Pulse Width = 300 s, Duty Cycle = 2%.
G
S
MARKING
DIAGRAM
SO–8
CASE 751
STYLE 11
8
ED2P01
AYWW
1
ED2P01
A
Y
WW
= Device Code
= Assembly Location
= Year
= Work Week
PIN ASSIGNMENT
Source–1
1
8
Drain–1
Gate–1
2
7
Drain–1
Source–2
3
6
Drain–2
Gate–2
4
5
Drain–2
Top View
ORDERING INFORMATION
Device
NTMD2P01R2
Package
Shipping
SO–8
2500/Tape & Reel
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
 Semiconductor Components Industries, LLC, 2001
October, 2001 – Rev. 0
1
Publication Order Number:
NTMD2P01R2/D
NTMD2P01R2
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) (Note 5)
Symbol
Characteristic
Min
Typ
Max
–16
–
–
–12.7
–
–
–
–
–
–
–1.0
–10
–
–
–100
–
–
100
–0.5
–
–0.90
2.5
–1.5
–
–
–
–
0.070
0.100
0.110
0.100
0.130
0.150
–
4.2
–
Ciss
–
540
750
Coss
–
215
325
Crss
–
100
175
td(on)
–
10
20
tr
–
35
65
td(off)
–
33
60
tf
–
29
55
td(on)
–
15
–
Unit
OFF CHARACTERISTICS
V(BR)DSS
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = –250 µAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(VDS = –16 Vdc, VGS = 0 Vdc, TJ = 25°C)
(VDS = –16 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS
Gate–Body Leakage Current
(VGS = –10 Vdc, VDS = 0 Vdc)
IGSS
Gate–Body Leakage Current
(VGS = +10 Vdc, VDS = 0 Vdc)
IGSS
Vdc
mV/°C
µAdc
nAdc
nAdc
ON CHARACTERISTICS
Gate Threshold Voltage
(VDS = VGS, ID = –250 µAdc)
Temperature Coefficient (Negative)
VGS(th)
Static Drain–to–Source On–State Resistance
(VGS = –4.5 Vdc, ID = –2.4 Adc)
(VGS = –2.7 Vdc, ID = –1.2 Adc)
(VGS = –2.5 Vdc, ID = –1.2 Adc)
RDS(on)
Forward Transconductance
(VDS = –10 Vdc, ID = –1.2 Adc)
Vdc
mV/°C
Ω
gFS
Mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = –16
16 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)
Output Capacitance
Reverse Transfer Capacitance
pF
SWITCHING CHARACTERISTICS (Notes 6 and 7)
Turn–On Delay Time
(VDD = –10 Vdc, ID = –2.4 Adc,
VGS = –4.5
–4 5 Vdc,
Vdc
RG = 6.0 Ω)
Rise Time
Turn–Off Delay Time
Fall Time
Turn–On Delay Time
(VDD = –10 Vdc, ID = –1.2 Adc,
VGS = –2.7
–2 7 Vdc,
Vdc
RG = 6.0 Ω)
Rise Time
Turn–Off Delay Time
Fall Time
Total Gate Charge
(VDS = –16 Vdc,
VGS = –4.5 Vdc,
ID = –2.4
2 4 Adc)
Ad )
Gate–Source Charge
Gate–Drain Charge
ns
ns
tr
–
40
–
td(off)
–
35
–
tf
–
35
–
Qtot
–
10
18
Qgs
–
1.5
–
Qgd
–
5.0
–
VSD
–
–
–0.88
–0.75
–1.0
–
Vdc
trr
–
37
–
ns
ta
–
16
–
tb
–
21
–
QRR
–
0.025
–
nC
BODY–DRAIN DIODE RATINGS (Note 6)
Diode Forward On–Voltage
(IS = –2.4 Adc, VGS = 0 Vdc)
(IS = –2.4 Adc, VGS = 0 Vdc, TJ = 125°C)
Reverse Recovery Time
(IS = –2.4
2 4 Adc,
Ad VGS = 0 Vdc,
Vd
dIS/dt = 100 A/µs)
Reverse Recovery Stored Charge
5. Handling precautions to protect against electrostatic discharge is mandatory.
6. Indicates Pulse Test: Pulse Width = 300 µs max, Duty Cycle = 2%.
7. Switching characteristics are independent of operating junction temperature.
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2
µC
NTMD2P01R2
5
4
VGS = –10 V
VGS = –4.5 V
VGS = –2.5 V
3
TJ = 25°C
–ID, DRAIN CURRENT (AMPS)
–ID, DRAIN CURRENT (AMPS)
VGS = –2.1 V
VGS = –1.9 V
2
VGS = –1.7 V
1
VGS = –1.5 V
4
3
2
TJ = 25°C
1
TJ = 100°C
0
2
4
6
8
1
10
3
2.5
Figure 2. Transfer Characteristics.
RDS(on), DRAIN–TO–SOURCE RESISTANCE ()
Figure 1. On–Region Characteristics.
0.15
0.1
0.05
0
2
4
6
8
–VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
0.12
TJ = 25°C
0.1
VGS = –2.7 V
0.08
VGS = –4.5 V
0.06
0.04
1
1.5
2
2.5
3
3.5
4
4.5
–ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance vs. Gate–to–Source
Voltage.
Figure 4. On–Resistance vs. Drain Current and
Gate Voltage.
1.6
1000
VGS = 0 V
ID = –2.4 A
VGS = –4.5 V
TJ = 125°C
–IDSS, LEAKAGE (nA)
100
1.2
1
0.8
0.6
–50
2
–VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
TJ = 25°C
1.4
1.5
–VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
0.2
RDS(on), DRAIN–TO–SOURCE
RESISTANCE (NORMALIZED)
TJ = 55°C
0
0
RDS(on), DRAIN–TO–SOURCE RESISTANCE ()
VDS > = –10 V
TJ = 100°C
10
TJ = 25°C
1
0.1
0.01
–25
0
25
75
50
100
125
TJ, JUNCTION TEMPERATURE (°C)
150
0
Figure 5. On–Resistance Variation with
Temperature.
4
8
12
16
–VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 6. Drain–to–Source Leakage Current
vs. Voltage.
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3
20
C, CAPACITANCE (pF)
VDS = 0 V
1200
VGS = 0 V
Ciss
TJ = 25°C
900
Crss
Ciss
600
300
Coss
Crss
0
10
5
0
–VGS –VDS
5
10
15
20
5
20
18
QT
16
4
14
3
12
VGS
Q1
10
Q2
8
2
6
1
ID = –2.4 A
TJ = 25°C
VDS
4
2
0
0
0
2
4
6
8
12
10
14
Qg, TOTAL GATE CHARGE (nC)
GATE–TO–SOURCE OR DRAIN–TO–SOURCE
VOLTAGE (VOLTS)
–VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
1500
–VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
NTMD2P01R2
Figure 8. Gate–to–Source and
Drain–to–Source Voltage versus Total Charge
Figure 7. Capacitance Variation
1000
100
td (off)
tr
t, TIME (ns)
t, TIME (ns)
VDD = –10 V
ID = –1.2 A
VGS = –2.7 V
100
tr
td
(on)
10
tf
td (off)
VDD = –10 V
ID = –2.4 A
VGS = –4.5 V
td (on)
1.0
10
10
1.0
tf
100
RG, GATE RESISTANCE (OHMS)
1.0
10
RG, GATE RESISTANCE (OHMS)
100
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
Figure 10. Resistive Switching Time Variation
versus Gate Resistance
–IS, SOURCE CURRENT (AMPS)
2
1.6
VGS = 0 V
TJ = 25°C
di/dt
IS
trr
1.2
ta
tb
TIME
0.8
0.25 IS
tp
IS
0.4
0
0.4
0.5
0.6
0.7
0.8
0.9
1
Figure 12. Diode Reverse Recovery Waveform
–VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 11. Diode Forward Voltage
versus Current
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4
NTMD2P01R2
Rthja(t), EFFECTIVE TRANSIENT THERMAL RESPONSE
1
D = 0.5
0.2
0.1
Normalized to R∅ja at Steady State (1 inch pad)
0.1
0.0125 Ω 0.0563 Ω
0.110 Ω
0.273 Ω
0.113 Ω
0.436 Ω
2.93 F
152 F
261 F
0.05
0.02
0.01
0.021 F
0.137 F
1.15 F
Single Pulse
0.01
1E–03
1E–02
1E–01
1E+00
1E+03
t, TIME (s)
Figure 13. FET Thermal Response
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5
1E+02
1E+03
NTMD2P01R2
INFORMATION FOR USING THE SO–8 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self–align when
subjected to a solder reflow process.
0.060
1.52
0.275
7.0
0.155
4.0
inches
mm
0.024
0.6
0.050
1.270
SOLDERING PRECAUTIONS
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied
during cooling.
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and
soldering should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
* * Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
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NTMD2P01R2
TYPICAL SOLDER HEATING PROFILE
temperature versus time. The line on the graph shows the
actual temperature that might be experienced on the surface
of a test board at or near a central solder joint. The two
profiles are based on a high density and a low density
board. The Vitronics SMD310 convection/infrared reflow
soldering system was used to generate this profile. The type
of solder used was 62/36/2 Tin Lead Silver with a melting
point between 177–189°C. When this type of furnace is
used for solder reflow work, the circuit boards and solder
joints tend to heat first. The components on the board are
then heated by conduction. The circuit board, because it has
a large surface area, absorbs the thermal energy more
efficiently, then distributes this energy to the components.
Because of this effect, the main body of a component may
be up to 30 degrees cooler than the adjacent solder joints.
For any given circuit board, there will be a group of
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones
and a figure for belt speed. Taken together, these control
settings make up a heating “profile” for that particular
circuit board. On machines controlled by a computer, the
computer remembers these profiles from one operating
session to the next. Figure 14 shows a typical heating
profile for use when soldering a surface mount device to a
printed circuit board. This profile will vary among
soldering systems, but it is a good starting point. Factors
that can affect the profile include the type of soldering
system in use, density and types of components on the
board, type of solder used, and the type of board or
substrate material being used. This profile shows
STEP 1
PREHEAT
ZONE 1
“RAMP”
200°C
STEP 2
STEP 3
VENT
HEATING
“SOAK” ZONES 2 & 5
“RAMP”
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
STEP 4
HEATING
ZONES 3 & 6
“SOAK”
160°C
STEP 5
STEP 6
STEP 7
HEATING
VENT
COOLING
ZONES 4 & 7
205° TO 219°C
“SPIKE”
PEAK AT
170°C
SOLDER
JOINT
150°C
150°C
100°C
140°C
100°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
5°C
TIME (3 TO 7 MINUTES TOTAL)
TMAX
Figure 14. Typical Solder Heating Profile
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NTMD2P01R2
PACKAGE DIMENSIONS
SO–8
CASE 751–07
ISSUE W
–X–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
A
8
5
0.25 (0.010)
S
B
1
M
Y
M
4
K
–Y–
G
C
N
X 45 SEATING
PLANE
–Z–
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
S
J
DIM
A
B
C
D
G
H
J
K
M
N
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0
8
0.25
0.50
5.80
6.20
STYLE 11:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0
8
0.010
0.020
0.228
0.244
SOURCE 1
GATE 1
SOURCE 2
GATE 2
DRAIN 2
DRAIN 2
DRAIN 1
DRAIN 1
ON Semiconductor and
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NTMD2P01R2/D