ETC NTMS10P02R2/D

NTMS10P02R2
Product Preview
HDTMOS3e Single SO-8
P–Channel Enhancement–Mode
Power MOSFET
Features
•
•
•
•
•
•
•
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Ultra Low RDS(on)
Higher Efficiency Extending Battery Life
Logic Level Gate Drive
Miniature SO–8 Surface Mount Package
Diode Exhibits High Speed, Soft Recovery
Avalanche Energy Specified
SO–8 Mounting Information Provided
P–Channel
D
G
Applications
• Power Management in Portable and Battery–Powered Products, i.e.:
S
Cellular and Cordless Telephones and PCMCIA Cards
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
VDSS
–20
Vdc
Gate–to–Source Voltage — Continuous
VGS
12
Vdc
Thermal Resistance —
Junction–to–Ambient (1.)
Total Power Dissipation @ TA = 25°C (1.)
Continuous Drain Current @ 25°C (1.)
Continuous Drain Current @ 70°C (1.)
Maximum Operating Power Dissipation (2.)
Maximum Operating Drain Current (2.)
Pulsed Drain Current (5.)
RθJA
PD
ID
ID
PD
ID
IDM
50
2.5
–10
–8.0
0.6
–5.5
–50
°C/W
W
A
A
W
A
A
Thermal Resistance —
Junction–to–Ambient (4.)
Total Power Dissipation @ TA = 25°C (3.)
Continuous Drain Current @ 25°C (3.)
Continuous Drain Current @ 70°C (3.)
Maximum Operating Power Dissipation (4.)
Maximum Operating Drain Current (4.)
Pulsed Drain Current (5.)
RθJA
PD
ID
ID
PD
ID
IDM
80
1.6
–8.8
–6.4
0.4
–4.5
–44
°C/W
W
A
A
W
A
A
TJ, Tstg
–55 to
+150
°C
Single Pulse Drain–to–Source Avalanche
Energy — Starting TJ = 25°C
(VDD = –20 Vdc, VGS = –4.5 Vdc,
Peak IL = 5.0 Apk, L = 40 mH,
RG = 25 Ω)
EAS
500
mJ
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
TL
Operating and Storage
Temperature Range
°C
260
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
August, 2000 – Rev. 1
1
SO–8
CASE 751
STYLE 12
MARKING DIAGRAM
E10P02
LYWW
E10P02= Device Code
L
= Assembly Location
Y
= Year
WW
= Work Week
PIN ASSIGNMENT
1
Source
1. Mounted onto a 2″ square FR–4 Board (1″ sq. Cu 0.06″ thick single sided),
t = 10 seconds.
2. Mounted onto a 2″ square FR–4 Board (1″ sq. Cu 0.06″ thick single sided),
t = steady state.
3. Minimum FR–4 or G–10 PCB, t = 10 seconds.
4. Minimum FR–4 or G–10 PCB, t = steady state.
5. Pulse Test: Pulse Width < 300 s, Duty Cycle < 2%.
 Semiconductor Components Industries, LLC, 2000
8
1
8
Drain
Source
2
7
Drain
Source
3
6
Drain
Gate
4
5
Drain
Top View
ORDERING INFORMATION
Device
Package
Shipping
NTMS10P02R2
SO–8
2500/Tape & Reel
Publication Order Number:
NTMS10P02R2/D
NTMS10P02R2
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) *
Symbol
Characteristic
Min
Typ
Max
Unit
–20
—
—
–12.1
—
—
—
—
—
—
–1.0
–5.0
—
—
–100
—
—
100
–0.6
—
–0.88
2.8
–1.20
—
—
—
0.012
0.017
0.014
0.020
gFS
—
30
—
Mhos
Ciss
—
3100
3640
pF
Coss
—
1100
1670
Crss
—
475
1010
td(on)
—
25
35
tr
—
40
65
td(off)
—
110
190
tf
—
110
190
td(on)
—
25
—
OFF CHARACTERISTICS
V(BR)DSS
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = –250 µAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(VDS = –20 Vdc, VGS = 0 Vdc, TJ = 25°C)
(VDS = –20 Vdc, VGS = 0 Vdc, TJ = 70°C)
IDSS
Gate–Body Leakage Current
(VGS = –12 Vdc, VDS = 0 Vdc)
IGSS
Gate–Body Leakage Current
(VGS = +12 Vdc, VDS = 0 Vdc)
IGSS
Vdc
mV/°C
µAdc
nAdc
nAdc
ON CHARACTERISTICS
Gate Threshold Voltage
(VDS = VGS, ID = –250 µAdc)
Temperature Coefficient (Negative)
VGS(th)
Static Drain–to–Source On–State Resistance
(VGS = –4.5 Vdc, ID = –10 Adc)
(VGS = –2.5 Vdc, ID = –8.8 Adc)
RDS(on)
Forward Transconductance (VDS = –10 Vdc, ID = –10 Adc)
Vdc
mV/°C
Ω
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = –16
16 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS
(6.)(7.)
Turn–On Delay Time
(VDD = –10 Vdc, ID = –1.0 Adc,
VGS = –4.5
–4 5 Vdc,
Vdc
RG = 6.0 Ω)
Rise Time
Turn–Off Delay Time
Fall Time
Turn–On Delay Time
(VDD = –10 Vdc, ID = –10 Adc,
–4 5 Vdc,
Vdc
VGS = –4.5
RG = 6.0 Ω)
Rise Time
Turn–Off Delay Time
Fall Time
Total Gate Charge
(VDS = –10 Vdc,
VGS = –4.5 Vdc,
ID = –10
10 Adc)
Ad )
Gate–Source Charge
Gate–Drain Charge
BODY–DRAIN DIODE RATINGS
tr
—
100
—
td(off)
—
100
—
tf
—
125
—
Qtot
—
48
70
Qgs
—
6.5
—
Qgd
—
17
—
ns
ns
nC
(6.)
Diode Forward On–Voltage
(IS = –2.1 Adc, VGS = 0 Vdc)
(IS = –2.1 Adc, VGS = 0 Vdc, TJ = 125°C)
VSD
—
—
–0.72
–0.60
–1.2
—
Vdc
Diode Forward On–Voltage
(IS = –10 Adc, VGS = 0 Vdc)
(IS = –10 Adc, VGS = 0 Vdc, TJ = 125°C)
VSD
—
—
–0.90
–0.75
—
—
Vdc
trr
—
65
100
ns
ta
—
25
—
tb
—
40
—
QRR
—
0.075
—
Reverse Recovery Time
(IS = –2.1
2 1 Adc,
Ad VGS = 0 Vdc,
Vd
dIS/dt = 100 A/µs)
Reverse Recovery Stored Charge
6. Indicates Pulse Test: Pulse Width = 300 µs max, Duty Cycle = 2%.
7. Switching characteristics are independent of operating junction temperature.
* Handling precautions to protect against electrostatic discharge is mandatory.
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2
µC
NTMS10P02R2
–2.3 V
15
–10 V
–3.1 V
10
–2.1 V
VDS ≥ –10 V
-I D , DRAIN CURRENT (AMPS)
-I D , DRAIN CURRENT (AMPS)
20
TJ = 25°C
–1.9 V
10
VGS = –1.7 V
5.0
0
0
0.25 0.50 0.75 1.00 1.25 1.50 1.75
–VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
8.0
6.0
100°C
2.0
0
2.00
25°C
4.0
0
0.5
1.0
1.5
2.0
2.5
–VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
0.100
ID = –10 A
TJ = 25°C
0.075
0.050
0.025
0
2.0
4.0
6.0
8.0
–VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
10
R DS(on), DRAIN-TO-SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
0.020
VGS = –2.5 V
TJ = 25°C
0.016
VGS = –4.5 V
0.012
0.008
6.0
Figure 3. On–Resistance versus
Gate–To–Source Voltage
10
14
–ID, DRAIN CURRENT (AMPS)
18
Figure 4. On-Resistance versus Drain Current
and Gate Voltage
1.6
10,000
VGS = 0 V
ID = –10 A
VGS = –4.5 V
1.4
-I DSS , LEAKAGE (nA)
R DS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)
R DS(on), DRAIN-TO-SOURCE RESISTANCE (OHMS)
Figure 1. On–Region Characteristics
0
TJ = –55°C
1.2
1.0
TJ = 125°C
1000
TJ = 100°C
100
0.8
0.6
–50
–25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
10
150
2.0
Figure 5. On–Resistance Variation with
Temperature
6.0
10
14
18
–VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 6. Drain–To–Source Leakage Current
versus Voltage
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3
NTMS10P02R2
10,000
C, CAPACITANCE (pF)
VGS = 0 V
8000
VDS = 0 V
TJ = 25°C
Ciss
6000
Crss
4000
Ciss
2000
Coss
Crss
0
10
5.0
0
5.0
–VGS –VDS
10
15
20
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
5.0
10
QT
4.0
8.0
VGS
VDS
3.0
6.0
Q1
Q2
4.0
2.0
1.0
ID = –10 A
TJ = 25°C
Q3
2.0
0
0
0
10
30
20
40
50
Qg, TOTAL GATE CHARGE (nC)
–VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
–VGS , GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
1000
1000
td(off)
VDD = –10 V
ID = –10 A
VGS = –4.5 V
tf
t, TIME (ns)
t, TIME (ns)
VDD = –10 V
ID = –1.0 A
VGS = –4.5 V
tr
100
td(on)
10
td(off)
tr
tf
100
td(on)
10
1.0
10
100
1.0
10
100
RG, GATE RESISTANCE (OHMS)
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
Figure 10. Resistive Switching Time Variation
versus Gate Resistance
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4
NTMS10P02R2
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
2.0
VGS = 0 V
TJ = 25°C
–ID , DRAIN CURRENT (AMPS)
–IS, SOURCE CURRENT (AMPS)
100
1.6
1.2
0.8
0.4
0
100 s
0.55
0.60
0.65
0.70
10 ms
VGS = 2.5 V
SINGLE PULSE
TC = 25°C
1.0
0.1
0.50
1.0 ms
10
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1.0
0.1
–VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
dc
10
100
–VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 11. Diode Forward Voltage versus Current
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 13. Diode Reverse Recovery Waveform
TYPICAL ELECTRICAL CHARACTERISTICS
Rthja(t)
, EFFECTIVE TRANSIENT
THERMAL RESISTANCE
10
1.0
0.1
D = 0.5
0.2
0.1
0.05
Normalized to θja at 10s.
Chip
0.02
0.01
0.0163 Ω
0.0652 Ω
0.1988 Ω
0.0307 F
0.1668 F
0.5541 F
0.6411 Ω
0.9502 Ω
0.01
1.9437 F
72.416 F
SINGLE PULSE
Ambient
0.001
1.0E–05
1.0E–04
1.0E–03
1.0E–02
1.0E–01
1.0E+00
t, TIME (s)
Figure 14. Thermal Response
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5
1.0E+01
1.0E+02
1.0E+03
NTMS10P02R2
INFORMATION FOR USING THE SO–8 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self–align when
subjected to a solder reflow process.
0.060
1.52
0.275
7.0
0.155
4.0
0.024
0.6
0.050
1.270
inches
mm
SOLDERING PRECAUTIONS
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied
during cooling.
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and
soldering should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
* Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
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6
NTMS10P02R2
TYPICAL SOLDER HEATING PROFILE
temperature versus time. The line on the graph shows the
actual temperature that might be experienced on the surface
of a test board at or near a central solder joint. The two
profiles are based on a high density and a low density
board. The Vitronics SMD310 convection/infrared reflow
soldering system was used to generate this profile. The type
of solder used was 62/36/2 Tin Lead Silver with a melting
point between 177–189°C. When this type of furnace is
used for solder reflow work, the circuit boards and solder
joints tend to heat first. The components on the board are
then heated by conduction. The circuit board, because it has
a large surface area, absorbs the thermal energy more
efficiently, then distributes this energy to the components.
Because of this effect, the main body of a component may
be up to 30 degrees cooler than the adjacent solder joints.
For any given circuit board, there will be a group of
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones
and a figure for belt speed. Taken together, these control
settings make up a heating “profile” for that particular
circuit board. On machines controlled by a computer, the
computer remembers these profiles from one operating
session to the next. Figure 15 shows a typical heating
profile for use when soldering a surface mount device to a
printed circuit board. This profile will vary among
soldering systems, but it is a good starting point. Factors
that can affect the profile include the type of soldering
system in use, density and types of components on the
board, type of solder used, and the type of board or
substrate material being used. This profile shows
STEP 1
PREHEAT
ZONE 1
RAMP"
200°C
150°C
STEP 2
STEP 3
VENT
HEATING
SOAK" ZONES 2 & 5
RAMP"
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
STEP 5
STEP 4
HEATING
HEATING
ZONES 3 & 6 ZONES 4 & 7
SPIKE"
SOAK"
170°C
160°C
140°C
100°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
TIME (3 TO 7 MINUTES TOTAL)
TMAX
Figure 15. Typical Solder Heating Profile
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7
STEP 7
COOLING
205° TO 219°C
PEAK AT
SOLDER JOINT
150°C
100°C
50°C
STEP 6
VENT
NTMS10P02R2
PACKAGE DIMENSIONS
SO–8
CASE 751–06
PLASTIC
ISSUE T
D
A
8
E
5
0.25
H
1
M
B
M
4
h
B
X 45 e
A
C
SEATING
PLANE
L
0.10
A1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETER.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
C
B
0.25
M
C B
S
A
S
DIM
A
A1
B
C
D
E
e
H
h
L
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.35
0.49
0.19
0.25
4.80
5.00
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0
7
STYLE 12:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
SOURCE
SOURCE
SOURCE
GATE
DRAIN
DRAIN
DRAIN
DRAIN
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
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NTMS10P02R2/D