ETC NTD60N03

NTD60N03
Advance Information
Power MOSFET
60 Amps, 28 Volts
N–Channel DPAK
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Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
60 AMPERES
28 VOLTS
RDS(on) = 6.1 mΩ (Typ.)
Typical Applications
•
•
•
•
Power Supplies
Converters
Power Motor Controls
Bridge Circuits
N–Channel
D
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
VDSS
28
Vdc
Gate–to–Source Voltage – Continuous
VGS
±20
Vdc
Drain Current – Continuous @ TA = 25°C
Drain Current – Single Pulse (tp = 10 µs)
ID
IDM
60*
120
Adc
Total Power Dissipation @ TA = 25°C
PD
75
Watts
TJ, Tstg
–55 to
150
°C
EAS
733
mJ
Operating and Storage
Temperature Range
Single Pulse Drain–to–Source Avalanche
Energy – Starting TJ = 25°C
(VDD = 28 Vdc, VGS = 10 Vdc,
IL = 17 Apk, L = 5.0 mH, RG = 25 Ω)
Thermal Resistance
– Junction–to–Case
– Junction–to–Ambient (Note 1)
– Junction–to–Ambient (Note 2)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
G
1 2
3
1.65
67
120
TL
260
3
CASE 369
DPAK
(Straight Lead)
STYLE 2
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
°C
1. When surface mounted to an FR4 board using 1″ pad size,
(Cu Area 1.127 in2).
2. When surface mounted to an FR4 board using the minimum recommended
pad size, (Cu Area 0.412 in2).
*Chip current capability limited by package.
12
CASE 369A
DPAK
(Bend Lead)
STYLE 2
°C/W
RθJC
RθJA
RθJA
4
S
4
YWW
T
4228
YWW
T
4228
1
Gate
2
Drain
Y
WW
T
4228
3
Source
1
Gate
= Year
= Work Week
= MOSFET
= Device Code
2
Drain
3
Source
ORDERING INFORMATION
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
 Semiconductor Components Industries, LLC, 2001
November, 2001 – Rev. 3
1
Device
Package
Shipping
NTD60N03
DPAK
75 Units/Rail
NTD60N03T4
DPAK
2500 Tape & Reel
NTD60N03–1
DPAK
Straight Lead
75 Units/Rail
Publication Order Number:
NTD60N03/D
NTD60N03
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
28
–
30.6
25
–
–
–
–
–
–
1.0
10
–
–
±100
1.0
–
1.9
–3.8
3.0
–
–
–
–
6.1
9.2
6.4
7.5
–
–
gFS
–
20
–
Mhos
Ciss
–
2150
–
pF
Coss
–
680
–
Crss
–
260
–
td(on)
–
10
–
tr
–
18
–
td(off)
–
32
–
tf
–
15
–
QT
–
31
–
Q1
–
8.0
–
Q2
–
18
–
–
–
–
0.75
1.2
0.65
1.0
–
–
trr
–
39
–
ta
–
21
–
tb
–
18
–
Qrr
–
0.043
–
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage (Note 3)
(VGS = 0 Vdc, ID = 250 µAdc)
Positive Temperature Coefficient
V(BR)DSS
Zero Gate Voltage Drain Current
(VGS = 0 Vdc, VDS = 28 Vdc)
(VGS = 0 Vdc, VDS = 28 Vdc, TJ = 150°C)
IDSS
Gate–Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc)
IGSS
Vdc
mV/°C
µAdc
nAdc
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3)
(VDS = VGS, ID = 250 µAdc)
Negative Threshold Temperature Coefficient
VGS(th)
Static Drain–to–Source On–Resistance (Note 3)
(VGS = 10 Vdc, ID = 30 Adc)
(VGS = 4.5 Vdc, ID = 30 Adc)
(VGS = 10 Vdc, ID = 10 Adc)
RDS(on)
Forward Transconductance (VDS = 15 Vdc, ID = 10 Adc) (Note 3)
Vdc
mV/°C
mΩ
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 24 Vdc,
Vd VGS = 0 Vdc,
Vd
f=1
1.0
0 MHz)
Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 4)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
(VDD = 15 Vdc, ID = 15 Adc,
VGS = 10 Vdc,
Vdc
RG = 3.3 Ω)
Fall Time
Gate
Ga
eC
Charge
a ge
(VDS = 24 Vdc,
Vd ID = 15 Adc,
Ad
VGS = 4.5
4 5 Vdc) (Note 3)
ns
nC
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 2.3 Adc, VGS = 0 Vdc) (Note 3)
(IS = 30 Adc, VGS = 0 Vdc)
(IS = 2.3 Adc, VGS = 0 Vdc, TJ = 150°C)
VSD
Reverse
e e se Recovery
eco e y Time
e
(IS = 2.3
2 3 Adc,
Ad VGS = 0 Vdc,
Vd
dIS/dt = 100 A/µs) (Note 3)
Reverse Recovery Stored Charge
3. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
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2
Vdc
nss
µC
NTD60N03
3.8 V
40
10 V
8V
6V
30
5V
4.5 V
4V
60
TJ = 25°C
VDS ≥ 10 V
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
50
3.6 V
3.4 V
20
3.2 V
10
3V
VGS = 2.8 V
TJ = 25°C
30
20
TJ = 125°C
10
TJ = –55°C
1
0.5
1.5
2
2.5
3
3.5
4
4.5
5
2
3
5
6
VGS, GATE–TO–SOURCE VOLTAGE (V)
Figure 1. On–Region Characteristics
Figure 2. Transfer Characteristics
0.07
ID = 10 A
TJ = 25°C
0.06
0.05
0.04
0.03
0.02
0.01
0
0
2
4
6
8
10
0.015
TJ = 25°C
0.01
VGS = 4.5 V
VGS = 10 V
0.005
0
10
5
15
20
25
30
VGS, GATE–TO–SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
Figure 3. On–Resistance versus
Gate–To–Source Voltage
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
0.01
1000
VGS = 0 V
ID = 30 A
VDS = 10 V
TJ = 125°C
IDSS, LEAKAGE (nA)
0.0075
0.005
0.0025
0
–50
4
VDS, DRAIN–TO–SOURCE VOLTAGE (V)
RDS(on), DRAIN–TO–SOURCE RESISTANCE (Ω)
0
RDS(on), DRAIN–TO–SOURCE RESISTANCE (Ω)
40
0
0
RDS(on), DRAIN–TO–SOURCE RESISTANCE (NORMALIZED)
50
100
TJ = 100°C
10
1
–25
0
25
50
75
100
125
150
4
8
12
16
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN–TO–SOURCE VOLTAGE (V)
Figure 5. On–Resistance Variation with
Temperature
Figure 6. Drain–To–Source Leakage
Current versus Voltage
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3
20
C, CAPACITANCE (pF)
VGS = 0 V
Ciss
TJ = 25°C
4000
3500
3000 Crss
2500
Ciss
2000
1500
1000
Crss
500
0
–15
Coss
–10
–5
VGS
0
VDS
5
10
15
20
25
10
28
QT
8
20
VGS
6
VD
16
Q1
4
Q2
12
8
2
ID = 15 A
TJ = 25°C
0
0
10
20
30
4
0
40
50
Qg, TOTAL GATE CHARGE (nC)
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (V)
Figure 7. Capacitance Variation
Figure 8. Gate–to–Source and
Drain–to–Source Voltage versus Total Charge
1000
5
IS, SOURCE CURRENT (AMPS)
VDD = 24 V
ID = 20 A
VGS = 10 V
t, TIME (ns)
24
100
tf
td(off)
tr
td(on)
10
VGS = 0 V
TJ = 25°C
4
3
2
1
0
1
1
10
0.1
100
0.3
0.5
0.7
0.9
RG, GATE RESISTANCE (Ω)
VSD, SOURCE–TO–DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
Figure 10. Diode Forward Voltage versus
Current
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–VDS, DRAIN–TO–SOURCE VOLTAGE (V)
5000
4500
VGS, GATE–TO–SOURCE VOLTAGE (V)
NTD60N03
NTD60N03
ID , DRAIN CURRENT (AMPS)
100
100 s
di/dt
1
1 ms
VGS = 10 V
SINGLE PULSE
TC = 25°C
10
trr
ta
tb
10 ms
TIME
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.25 IS
tp
IS
1
0.1
IS
10
100
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 12. Diode Reverse Recovery Waveform
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Rthja(t), EFFECTIVE TRANSIENT
THERMAL RESISTANCE
1000
MOUNTED TO MINIMUM RECOMMENDED FOOTPRINT
DUTY CYCLE
100
D = 0.5
0.2
0.1
0.05
0.02
0.01
10
1
P(pk)
t1
0.1
0.01
t2
DUTY CYCLE, D = t1/t2
SINGLE PULSE
1E-05
1E-04
1E-03
1E-02
1E-01
t, TIME (seconds)
1E+00
Figure 13. Thermal Response – Various Duty Cycles
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RθJA(t) = r(t) RθJA
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) - TA = P(pk) RθJA(t)
1E+01
1E+02
1E+03
NTD60N03
INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to ensure proper solder connection
0.165
4.191
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.100
2.54
0.118
3.0
0.063
1.6
0.190
4.826
0.243
6.172
inches
mm
SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads.
Solder stencils are used to screen the optimum amount.
These stencils are typically 0.008 inches thick and may be
made of brass or stainless steel. For packages such as the
SC–59, SC–70/SOT–323, SOD–123, SOT–23, SOT–143,
SOT–223, SO–8, SO–14, SO–16, and SMB/SMC diode
packages, the stencil opening should be the same as the pad
size or a 1:1 registration. This is not the case with the DPAK
and D2PAK packages. If one uses a 1:1 opening to screen
solder onto the drain pad, misalignment and/or
“tombstoning” may occur due to an excess of solder. For
these two packages, the opening in the stencil for the paste
should be approximately 50% of the tab area. The opening
for the leads is still a 1:1 registration. Figure 14 shows a
typical stencil for the DPAK and D2PAK packages. The
pattern of the opening in the stencil for the drain pad is not
critical as long as it allows approximately 50% of the pad to
be covered with paste.
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇÇ
ÇÇÇ
ÇÇ
ÇÇÇ
ÇÇÇ
ÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
SOLDER PASTE
OPENINGS
STENCIL
Figure 14. Typical Stencil for DPAK and
D2PAK Packages
SOLDERING PRECAUTIONS
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied
during cooling.
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and
soldering should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.
* Due to shadowing and the inability to set the wave height
to incorporate other surface mount components, the D2PAK
is not recommended for wave soldering.
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6
NTD60N03
TYPICAL SOLDER HEATING PROFILE
temperature versus time. The line on the graph shows the
actual temperature that might be experienced on the surface
of a test board at or near a central solder joint. The two
profiles are based on a high density and a low density
board. The Vitronics SMD310 convection/infrared reflow
soldering system was used to generate this profile. The type
of solder used was 62/36/2 Tin Lead Silver with a melting
point between 177–189°C. When this type of furnace is
used for solder reflow work, the circuit boards and solder
joints tend to heat first. The components on the board are
then heated by conduction. The circuit board, because it has
a large surface area, absorbs the thermal energy more
efficiently, then distributes this energy to the components.
Because of this effect, the main body of a component may
be up to 30 degrees cooler than the adjacent solder joints.
For any given circuit board, there will be a group of
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones
and a figure for belt speed. Taken together, these control
settings make up a heating “profile” for that particular
circuit board. On machines controlled by a computer, the
computer remembers these profiles from one operating
session to the next. Figure 15 shows a typical heating
profile for use when soldering a surface mount device to a
printed circuit board. This profile will vary among
soldering systems, but it is a good starting point. Factors
that can affect the profile include the type of soldering
system in use, density and types of components on the
board, type of solder used, and the type of board or
substrate material being used. This profile shows
STEP 1
PREHEAT
ZONE 1
“RAMP”
200°C
STEP 2
STEP 3
VENT
HEATING
“SOAK” ZONES 2 & 5
“RAMP”
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
STEP 4
HEATING
ZONES 3 & 6
“SOAK”
160°C
STEP 5
STEP 6
STEP 7
HEATING
VENT
COOLING
ZONES 4 & 7
205° TO 219°C
“SPIKE”
PEAK AT
170°C
SOLDER
JOINT
150°C
150°C
100°C
140°C
100°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
5°C
TIME (3 TO 7 MINUTES TOTAL)
TMAX
Figure 15. Typical Solder Heating Profile
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7
NTD60N03
PACKAGE DIMENSIONS
DPAK, STRAIGHT LEAD
CASE 369–07
ISSUE M
C
B
V
E
R
4
A
1
2
3
S
–T–
SEATING
PLANE
K
J
F
H
D
G
3 PL
0.13 (0.005)
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
DIM
A
B
C
D
E
F
G
H
J
K
R
S
V
INCHES
MIN
MAX
0.235
0.250
0.250
0.265
0.086
0.094
0.027
0.035
0.033
0.040
0.037
0.047
0.090 BSC
0.034
0.040
0.018
0.023
0.350
0.380
0.175
0.215
0.050
0.090
0.030
0.050
STYLE 2:
PIN 1.
2.
3.
4.
T
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8
GATE
DRAIN
SOURCE
DRAIN
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.84
1.01
0.94
1.19
2.29 BSC
0.87
1.01
0.46
0.58
8.89
9.65
4.45
5.46
1.27
2.28
0.77
1.27
NTD60N03
PACKAGE DIMENSIONS
DPAK
CASE 369A–13
ISSUE AB
–T–
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
SEATING
PLANE
E
R
4
Z
A
S
1
2
3
U
K
F
J
L
H
D
G
2 PL
0.13 (0.005)
M
T
DIM
A
B
C
D
E
F
G
H
J
K
L
R
S
U
V
Z
INCHES
MIN
MAX
0.235
0.250
0.250
0.265
0.086
0.094
0.027
0.035
0.033
0.040
0.037
0.047
0.180 BSC
0.034
0.040
0.018
0.023
0.102
0.114
0.090 BSC
0.175
0.215
0.020
0.050
0.020
--0.030
0.050
0.138
---
STYLE 2:
PIN 1.
2.
3.
4.
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9
GATE
DRAIN
SOURCE
DRAIN
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.84
1.01
0.94
1.19
4.58 BSC
0.87
1.01
0.46
0.58
2.60
2.89
2.29 BSC
4.45
5.46
0.51
1.27
0.51
--0.77
1.27
3.51
---
NTD60N03
Notes
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NTD60N03
Notes
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NTD60N03
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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NTD60N03/D