ETC STEL-1109/CR

STEL-1109
Data Sheet
STEL-1109/CR
5 - 65 MHz
Burst Transmitter
R
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TABLE OF CONTENTS
TRADEMARKS................................................................................................................................................................
KEY FEATURES................................................................................................................................................................
INTRODUCTION............................................................................................................................................................
PIN CONFIGURATION .................................................................................................................................................
POWER SUPPLY PINS....................................................................................................................................................
FUNCTIONAL BLOCK DIAGRAM DESCRIPTIONS............................................................................................
Overview ........................................................................................................................................................................
Data Path Description ...................................................................................................................................................
Bit Sync Block .............................................................................................................................................................
Bit Encoder Block.......................................................................................................................................................
Data Path Control (Multiplexers)........................................................................................................................
Scrambler ................................................................................................................................................................
Reed-Solomon Encoder.........................................................................................................................................
Symbol Mapper Block...............................................................................................................................................
Bit Mapper..............................................................................................................................................................
Differential Encoder ..............................................................................................................................................
Symbol Mapper......................................................................................................................................................
Nyquist Fir Filter .......................................................................................................................................................
Interpolating Filter ....................................................................................................................................................
Modulator ...................................................................................................................................................................
10-Bit DAC..................................................................................................................................................................
Control Unit Description..............................................................................................................................................
Bus Interface Unit ......................................................................................................................................................
Clock Generator .........................................................................................................................................................
NCO.............................................................................................................................................................................
TIMING DIAGRAMS.....................................................................................................................................................
Clock Timing..................................................................................................................................................................
Pulse Width ....................................................................................................................................................................
Bit Clock Synchronization............................................................................................................................................
Input Data and Clock Timing......................................................................................................................................
Write Timing ..................................................................................................................................................................
Read Timing ...................................................................................................................................................................
NCO Loading (User Controlled) .................................................................................................................................
NCO Loading (Automatic) ..........................................................................................................................................
Digital Output Timing ..................................................................................................................................................
DATAEN to DATAENO Timing ................................................................................................................................
BURST TIMING EXAMPLES........................................................................................................................................
Burst Timing: Full Burst (Slave Mode, QPSK) ..........................................................................................................
Master Mode, BPSK Burst Timing Signal Relationships .........................................................................................
Slave Mode, BPSK Burst Timing Signal Relationships ............................................................................................
Master Mode, QPSK Burst Timing Signal Relationships ........................................................................................
Slave Mode, QPSK Burst Timing Signal Relationships ...........................................................................................
Master Mode, 16QAM Burst Timing Signal Relationships ....................................................................................
Slave Mode, 16QAM Burst Timing Signal Relationships........................................................................................
ELECTRICAL SPECIFICATIONS ................................................................................................................................
RECOMMENDED INTERFACE CIRCUITS ..............................................................................................................
Slave Mode Interface.....................................................................................................................................................
Master Mode Interface..................................................................................................................................................
EXAMPLE OUTPUT LOAD SCHEMATIC ................................................................................................................
MECHANICAL SPECIFICATIONS .............................................................................................................................
STEL-1109
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PRELIMINARY PRODUCT INFORMATION
LIST OF ILLUSTRATIONS
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
STEL-1109 Block Diagram....................................................................................................................
Bit Encoder Functional Diagram ........................................................................................................
Scrambler Block Diagram ....................................................................................................................
DAVIC Scrambler..................................................................................................................................
Mapping Block Functional Diagram ..................................................................................................
BPSK Constellation ...............................................................................................................................
QPSK Constellation ..............................................................................................................................
Natural Mapping Constellation..........................................................................................................
Gray Coded Constellation ...................................................................................................................
Left Coded Constellation .....................................................................................................................
DAVIC Coded Constellation ...............................................................................................................
Right Coded Constellation ..................................................................................................................
Nyquist FIR Filter..................................................................................................................................
Interpolation Filter Block Diagram.....................................................................................................
Duty Cycle Derating Versus Temperature (@3.3v)..........................................................................
STEL-1109 Mechanical Characteristics ..............................................................................................
PRELIMINARY PRODUCT INFORMATION
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STEL-1109
LIST OF TABLES
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
STEL-1109 Features ..............................................................................................................................
I/O Signal Pin Assignments................................................................................................................
STEL -1109 Configuration Register Data Fields...............................................................................
Data Latching Options .........................................................................................................................
Bit Encoding Data Path Options.........................................................................................................
Scrambler Parameters ..........................................................................................................................
Sample Scramble Register Values ......................................................................................................
Reed-Solomon Encoder Parameters...................................................................................................
Bit Mapping Options............................................................................................................................
Differential Encoder Control...............................................................................................................
Qpsk Differential Encoding and Phase Shift ....................................................................................
Symbol Mapping Selections................................................................................................................
Symbol Mapping ..................................................................................................................................
FIR Filter Configuration Options .......................................................................................................
FIR Filter Coefficient Storage..............................................................................................................
Interpolation Filter Bypass Control....................................................................................................
Interpolation Filter Signal Level Control ..........................................................................................
Signal Inversion Control......................................................................................................................
FCW Selection .......................................................................................................................................
Clock Timing AC Characteristics .......................................................................................................
Pulse Width AC Characteristics .........................................................................................................
Bit Clock Synchronization AC Characteristics .................................................................................
Input Data and Clock AC Characteristics .........................................................................................
Write Timing AC Characteristics .......................................................................................................
Read Timing AC Characteristics ........................................................................................................
NCO Loading AC Characteristics ......................................................................................................
Digital Output Timing AC Characteristics .......................................................................................
DATAEN to DATAENO Timing AC Characteristics......................................................................
Absolute Maximum Ratings ...............................................................................................................
Recommended Operating Conditions ...............................................................................................
DC Characteristics ................................................................................................................................
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TRADEMARKS


Stanford Telecom and STEL are registered trademarks of Stanford Telecommunications, Incorporated.
STEL-1109
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PRELIMINARY PRODUCT INFORMATION
KEY FEATURES
n Complete BPSK/QPSK/16QAM modulator in
n
n
n
n
n
n
a CMOS ASIC
Programmable over a wide range of data
rates
NCO modulator provides fine frequency
resolution
165 MHz maximum clock rate generates a
modulated carrier at frequencies
programmable from 5 to 65 MHz
Operates in continuous and burst modes
Differential Encoder, Programmable
Scrambler, and Programmable
Reed-Solomon FEC Encoder
Feature
n
n
n
n
n
Programmable 32-tap FIR Filter for signal
shaping before modulation
10-bit DAC implemented on chip
Complete upstream modulator solution –
serial data in and RF signal out
Compatible with DAVIC, IEEE 802.14
(preliminary), Intelsat IESS-308, ITU J.83
Annex A, MCNS Standards
Supports low data rates for voice
applications and high data rates for
wideband applications
Small Footprint, Surface Mount 80-Pin
MQFP Package
Table 1. STEL-1109 Features
Characteristic
Carrier frequency:
5 to 65 MHz (maximum of approximately 40% of master clock)
Symbol rate:
From Master clock divided by 16 down to Master clock divided by
16384 (in steps of 4) yielding a maximum symbol rate of 10Msps with a
160 MHz clock.
FIR filter tap coefficients:
32 programmable taps (10 bits each), symmetric response
Modulation:
BPSK, QPSK, or 16QAM
16QAM constellation:
Eight selectable bit-to-symbol mappings
Five selectable symbol-to-constellation mappings
I and Q modulator signs / Spectral
Inversion
Signs of I and Q plus the mapping to Sine and Cosine carriers is
programmable.
Reed-Solomon encoder:
Selectable on/off
Two selectable generator polynomials
Block length shortened any amount
Error correction capability T = 1 to 10
Scrambler:
Selectable on/off
Self-synchronizing or frame synchronized (sidestream)
Location before or after RS Encoder
Programmable generator polynomial
Programmable length up to 224 - 1
Programmable initial seed
Differential encoder:
Selectable on/off
PRELIMINARY PRODUCT INFORMATION
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STEL-1109
INTRODUCTION
The STEL-11091 is a highly integrated, maximally
flexible, burst transmitter targeted to the cable modem
market. It receives serial data, randomizes the data,
performs FEC and differential encoding, maps the data
to a constellation before modulation, and outputs an
analog RF signal.
designed to have a symmetrical (mirror image)
polynomial transfer function, thereby making the phase
response of the filter linear. This also eliminates the
inter-symbol interference that results from group delay
distortion. In this way, it is possible to change the
carrier frequency over a wide frequency range without
having to change filters, thus providing the ability to
operate a single system in many channels.
The STEL-1109 is the latest in a series of modulator
chips that comprise the STEL-1103 through STEL-1108
modulators. Several key components (e.g., a 10-bit
DAC, FECs, etc.) have been incorporated in the
STEL-1109 and the enhancements have resulted in
significant changes to the chipÕs electrical and software
interfaces.
The STEL-1109 can operate with very short gaps
between transmitted bursts to increase the efficiency of
TDMA systems. The STEL-1109 (as well as the STEL1103 and STEL-1108) operates properly even when the
interburst gap is less than four (4) symbols (half the
length of the FIR filter response). In this case the
postcursor of the previous burst overlaps and is
superimposed on the precursor of the following burst.
The STEL-1109 is capable of operating at data rates of
up to 10 Mbps in BPSK mode, 20 Mbps in QPSK mode,
and 40 Mbps in 16QAM mode. It operates at clock
frequencies of up to 165 MHz, which allows its internal,
10-bit Digital-to-Analog Converter (DAC) to generate
RF carrier frequencies of 5 to 65 MHz.
Signal level scaling is provided after the FIR filter to
allow the STEL-1109Õs maximum arithmetic dynamic
range to be utilized. Signal levels can be changed over
a wide range depending on how the device is
programmed.
The STEL-1109 also uses digital FIR filtering to
optimally shape the spectrum of the modulating data
prior to modulation. This optimizes the spectrum of
the modulated signal, and minimizes the analog
filtering required after the modulator. The filters are
1
In addition, the STEL-1109 is designed to operate from
a 3.3 Vdc power supply and the chip can be interfaced
with logic that operates at 5 Vdc.
The STEL-1109 utilizes advanced signal processing
techniques which are covered by U.S. Patent Number
5,412,352.
STEL-1109
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PRELIMINARY PRODUCT INFORMATION
PIN CONFIGURATION
The STEL-1109 input and output signal pin
assignments are listed in Table 2. The location of the
pin numbers is shown by Figure 16 (page 39). The
STEL-1109 power supply pins are described in the
following paragraph.
Table 2. I/O Signal Pin Assignments
1
VDD
[7]
(S)
21
FCWSEL1
[21]
(I)
41
VDD
[7]
(S)
61
VSS
[7]
(T)
2
DATA4
[20]
(B)
22
VSS
[7]
(T)
42
SYMPLS
[20]
(O)
62
VDD
[7]
(S)
3
DATA5
[20]
(B)
23
VSS
[7]
(T)
43
VSS
[7]
(S)
63
VDD
[7]
(T)
4
DATA6
[20]
(B)
24
VSS
[7]
(T)
44
VSS
[7]
(T)
64
VSS
[7]
(S)
5
DATA7
[20]
(B)
25
VDD
[7]
(S)
45
VSS
[7]
(T)
65
VDD
[7]
(T)
6
VSS
[7]
(S)
26
CLKEN
[9,20]
(I)
46
VSS
[7]
(T)
66
VSS
[7]
(S)
7
VSS
[7]
(S)
27
VSS
[7]
(S)
47
VSS
[7]
(T)
67
RSTB
[20]
(I)
8
ADDR5
[20]
(I)
28
CLK
[20]
(I)
48
VSS
[7]
(T)
68
VSS
[7]
(T)
9
ADDR4
[20]
(I)
29
RDSLEN
[10]
(I)
49
VSS
[7]
(S)
69
VSS
[7]
(S)
10
ADDR3
[20]
(I)
30
VDD
[7]
(S)
50
[7]
(N.C.)
70
DIFFEN
[13]
(I)
11
VDD
[7]
(S)
31
5VDD
[7]
(I)
51
AV DD
[7]
(S)
71
NCO LD
[21]
(I)
12
ADDR2
[20]
(I)
32
SCRMEN
[10]
(I)
52
OUT
[20]
(AO)
72
CSEL
[20]
(I)
13
ADDR1
[20]
(I)
33
VSS
[7]
(S)
53
OUTN
[20]
(AO)
73
DSB
[20]
(I)
14
ADDR0
[20]
(I)
34
VSS
[7]
(T)
54
AV SS
[7]
(S)
74
WR
[20]
(I)
15
VSS
[7]
(S)
35
CKSUM
[12]
(O)
55
[7]
(N.C.)
75
VDD
[7]
(S)
16
VSS
[7]
(S)
36
VSS
[7]
(S)
56
VSS
[7]
(S)
76
DATA0
[20]
(B)
17
TSDATA
[9]
(I)
37
ACLK
[20]
(O)
57
VSS
[7]
(T)
77
DATA1
[20]
(B)
18
DATAEN
[10]
(I)
38
VDD
[7]
(S)
58
VSS
[7]
(T)
78
DATA2
[20]
(B)
19
TCLK
[9]
(I)
39
DATAENO [20]
(O)
59
VSS
[7]
(T)
79
DATA3
[20]
(B)
20
FCWSEL0
[21]
(I)
40
BITCLK
[9,20] (O)
60
VSS
[7]
(T)
80
VSS
[7]
(S)
Notes:
1. Pin 31 is applied to input buffers only.
2. See Package Outline (Figure 16) for pin
identification.
Legend:
(AO)
(B)
(I)
(N.C.)
Analog Output
Bi-directional (I/O) signal
Input signal
Not Connected
(O)
(S)
(T)
[#]
Output signal
Source
Factory Test Pin
Page Reference
POWER SUPPLY PINS
There are three separate power supply systems within
the STEL-1109. The primary supply for the digital logic
circuits is nominally 3.3 volts and is input on the VDD
pins. The digital inputs have a separate supply, 5VDD,
which can be connected to a 5 volt supply if the STEL1109 inputs are driven from 5 volt logic. If the logic
driving the STEL-1109 is run on 3.3 volts, then the 5VDD
pin should be connected to 3.3 volts. The return for
both digital supplies is VSS. The DAC has a separate
analog power supply and return, AVDD and AVSS. The
3.3 volt AV DD input allows the user to provide a
separate well filtered supply for the DAC to prevent
spurs that might be created from digital noise on the
VDD supply system.
PRELIMINARY PRODUCT INFORMATION
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STEL-1109
FUNCTIONAL BLOCK DIAGRAM DESCRIPTIONS
OVERVIEW
The STEL-1109 is comprised of the Data Path and
Control Unit sections shown in Figure 1. The Data Path
is comprised of a Bit Sync Block, Bit Encoder Block
(i.e.,Êthe Scrambler, Reed-Solomon Encoder, and two
Multiplexers shown in Figure 2), Symbol Mapper Block
(i.e., the Bit Mapper, Differential Encoder, and Symbol
Mapper are shown in FigureÊ5), two channels (one for I
and one for Q), a Combiner, and a 10-bit DAC. Each
channel consists of a Nyquist Filter, Interpolation Filter,
and Modulator. The Control Unit is comprised of a Bus
Interface Unit (BIU), Clock Generator, and NCO.
Table 1 summarizes the main features of the circuits
described by the remaining paragraphs of this section.
The STEL-1109 provides 58, programmable, read/write
registers (Configuration Registers). Table 3 provides a
graphic representation of the STEL-1109Õs
Configuration Registers and their data fields. Each
register can be selected for a write or read operation
using addresses 00H through 39H.
Table 3. STEL-1109 Configuration Register Data Fields
Address
Contents
(Hex)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
NCO
28 - 09
FIR Filter Coefficients
18
LSB Sampling Rate Control (see address 39 for MSB)
2A
Interpolation Filter Gain Control
19
Set To Zero
Set To Zero
Interpolation Filt. Bypass
2C
TCLK Sel.
9
Set To Zero
Set To Zero
2D
FZSINB
2E
Bit Mapping
Symbol Mapping
19
Set To One
Set To Zero
MOD
Set To One
15
FIR bypass
Set To Zero
18
PN Code Sel
9
18
CLRFIR
20
Set To Zero
PN On/Off
9
Bit Sync Re-arm
9
Set To Zero
11
32-30
SCRAMBLER Init Registers
35-33
SCRAMBLER Mask Registers
PPolynomial
13
BypassB
10
10
S-RS
Self-Sync
T
K
38
DATAENBPB
39
Set To Zero
10
10
DATAENSEL
Set To Zero
10
RSENBPB
TRLSBF
12
10
RSENSEL
LDLSBF
11
11
37
Note:
20
Invert I/Q Chan.
14
Set To Zero
13
2F
36
20
Auxiliary Clock Rate Divider
2B
21
Bit 0
21
08 - 00
29
Bit 1
12
12
12
SCRMENBPB
10
10
SCRMENSEL
14
DiffDCBPB
DiffDCSEL
MSB Sampling Rate Control (see address 29 for LSB)
14
20
Superscripted numbers are page references where discussion on setting the particular register(s)
or bit(s) begins.
STEL-1109
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PRELIMINARY PRODUCT INFORMATION
DIFFEN
TCLK
TSDATA
DATA PATH
BIT
Sync
Block
I[1:0]
I[1:0],
Q[1:0]
DATAEN
RDSLEN
SCRMEN
BIT
Encoder
Block
Symbol
Mapper
Block
4
2
Q[1:0]
2
OUT
Nyquist
Filter
Interpolating
Filter
Nyquist
Filter
Interpolating
Filter
10-Bit
DAC
OUTN
Modulator
DATAENO
CKSUM
AVDD
5VDD
VDD
SAMPLS
MASTER CLOCK
RST
BITCLK
SYMPLS
Clock
Generator
ACLK
CLKEN
CLK
COS 2πFT
NCO LD
FCWSEL1-0
SIN 2πFT
Numerically
Controlled
Oscillator
DATA7-0
ADDR5-0
DSB
WR
Bus
Interface
Unit
CSEL
CONTROL UNIT
WCP 52981.c-5/2/97
Figure 1. STEL-1109 Block Diagram
DATA PATH DESCRIPTION
BIT SYNC BLOCK
•
The Bit Sync Block has two functions, latching input
data, and synchronizing the STEL-1109 BITCLK and
symbol counters to the user data.
Externally supplied TSDATA is latched by an
externally provided TCLK
•
Internally generated PN code data is latched by the
internal BITCLK
Latching Input Data
See Table 4 for register settings to implement each
mode.
Latching of input data is accomplished in three ways:
•
Externally supplied TSDATA is latched by the
internal BITCLK.
Table 4. Data Latching Options
Data Source
TSDATA
TSDATA
PN Code 10, 3
PN Code 23, 18
Latched By
BITCLK
TCLK
BITCLK
BITCLK
PRELIMINARY PRODUCT INFORMATION
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Register 2C Bit 7
0
1
0
0
9
Register 2D Bits 1,0
X,0
X,0
0,1
1,1
Mode Name
Master Mode
Slave Mode
Test Mode
Test Mode
STEL-1109
BITCLK latches data on its falling edge. TCLK latches
data on its rising edge.
BIT ENCODER BLOCK
The Bit Encoder Block consists of a Scrambler, a
Reed-Solomon Encoder, and data path controls
(multiplexers), as shown in Figure 2.
Whenever the CLKEN input is low, the BITCLK output
will stop. In order to provide customers with a
continuous clock, the STEL-1109 provides an auxiliary
clock (ACLK) output which is discussed later in the
clock generator section. The ACLK output is primarily
for use in master mode where users may need a clock to
run control circuits during the guard time between
bursts.
DATAEN
When using slave mode, the data that is latched by the
rising edge of TCLK is re-latched internally by the next
falling edge of BITCLK which re-synchronizes the data
to the internal master clock.
RDSLEN
Scrambler
Reed-Solomon
Encoder
Output
Multiplexer
SERIAL
DATA
Input
Multiplexer
SCRMEN
ENCODED
SERIAL DATA
CHKSUM
SIGNAL
S-RS
WCP 52982.c-4/26/97
Synchronizing BITCLK / SYMPLS
Figure 2. Bit Encoder Functional Diagram
The synchronization circuit aligns the STEL-1109
BITCLK and its SYMPLS counter circuits to the
beginning of the first user data symbol. The circuit has
two parts, an arming circuit and a trigger circuit. Once
armed, the first rising edge on the TCLK input will
activate (trigger) the synchronization process.
Data Path Control (Multiplexers)
Once triggered, the sync circuit re-starts the BITCLK
and SYMPLS counters. The BITCLK output starts high,
and SYMPLS resets to the start of a symbol. There is a
delay equal to about three cycles of the master clock
from the rising edge of the TCLK input before this restart occurs. During this brief delay period, the BITCLK
and SYMPLS counters are still free running and may or
may not have transitions.
The STEL-1109 provides a great deal of flexibility and
control over the routing of data through or around the
encoding functions.
With appropriate register
selections, data can be routed around (bypass) both
encoders, through either one and around the other,
through the scrambler then the RS Encoder, or through
the RS Encoder and then the scrambler. Control over
the bypassing can be set for software control or external
(user) input signal control. Generally, if an encoding
function will be left either on or off continuously, then
software control is appropriate. If the function must be
turned on and off dynamically (typically in order to
send the preamble Ôin the clearÕ i.e. unencoded), then
external (user) input control is required. If the ReedSolomon encoder will not be used at all, then a separate
bypass option can be activated to remove an 8 bit delay
register from the data path that is required if the
possibility of turning on the encoder exists. Each of the
external (user) input control pins (if enabled) turns on
the encoding function when high and bypasses the
function when low.
In master mode, the rising edge of TCLK normally
marks the transition of the first user data bit (which will
be latched in by the next falling edge of BITCLK). In
slave mode, the first user data bit must already be valid
at this first rising edge of TCLK.
The DATAEN input signal determines whether or not
data will advance (shift through) the encoding blocks.
The presence of a high on the DATAEN input when the
BITCLK output goes low allows the circuits to advance
data through them. The DATAEN signal is delayed
The circuit can be armed in two ways; taking CLKEN
from low to high, or toggling Configuration Register
2EH bit 0 from low to high to low again. In a normal
burst mode application, the circuit is automatically rearmed between bursts because CLKEN goes low. For
applications that will not allow CLKEN to cycle low
between bursts, some system level precautions should
be observed to maintain synchronization of user data to
the STEL-1109 BITCLK.
STEL-1109
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PRELIMINARY PRODUCT INFORMATION
internally to allow the rising edge of DATAEN to
coincide with the first rising edge of TCLK.
See Table 5 for a summary of register settings required
to achieve the various data path possibilities.
Table 5. BIT Encoding Data Path Options
Data Path
Data stopped (continuously)
Data path on (continuously)
Data path enabled by pin 18
Scrambler off (continuously)
Scrambler on (continuously)
Scrambler enabled by pin 32
RS Encode off (continuously)
RS Encode on (continuously)
RS Encode enabled by pin 29
Scrambler then RS Encoder
RS Encoder then Scrambler
Bypass RS Encoder
Register 36 Bits 6,5
X,X
X,X
X,X
X,X
X,X
X,X
1,X
1,X
1,X
1,1
1,0
0,X
Register 38 Bits 7-2
01 XXÊXX
11 XXÊXX
X0 XXÊXX
XX XX 01
XX XX 11
XX XX X0
XX 01 XX
XXÊ11 XX
XXÊX0 XX
XXÊXXÊXX
XXÊXXÊXX
XXÊXXÊXX
Scrambler
The scrambler can be used to randomize the serial data
in order to avoid a strong spectral component that
might otherwise arise from the occurrence of repeating
patterns in the input data. The Scrambler (Figure 3)
uses a Pseudo-Random (PN) generator to generate a PN
code pattern. All 24 registers are presettable and any
combination of the registers can be connected (tapped)
to form any polynomial of up to 24 bits. The scrambler
may be either frame synchronized or self synchronized.
Table 6 shows the registers involved.
24-bit Mask Reg
1
2
3
24-bit INIT Reg
1
2
3
22
23
24
1
2
3
22
23
24
22 23
24
24-bit Shift Reg
XOR
The value in the INIT registers is loaded into the
scrambler shift registers whenever the scrambler is
disabled. The scrambler will scramble data one bit at a
time at each falling edge of BITCLK that occurs while
both the scrambler and DATAEN are active (enabled).
Internal delays on the SCRMEN control signal input
allow for a rising edge to occur coincident with the
rising edge of BITCLK that precedes the latching of the
first data bit to be scrambled.
SCRMEN
AND
SERIAL INPUT
SERIAL OUTPUT
XOR
SELF
SYNC
SSYNC
FRAME
SYNC
MUX
WCP 52983.c-4/26/97
Figure 3. Scrambler Block Diagram
Table 6. Scrambler Parameters
Parameter
Generator
Polynomial
(Mask Reg)
Characteristic
p(x) = c24x 24 + c23x 23 + É + c1 x + 1
where ci is a binary value (0, 1)
Configuration Register Setting
Register 34
Register 33
Register 35
Bit 7 to Bit 0
Bit 7 to Bit 0
Bit 7 to Bit 0
to c17
c16
to c9
c8
to c1
c24
Seed
(INIT Reg)
Any 24 bit binary value, s24-1
Register 32
Bit 7 to Bit 0
s24
to s17
Scrambler
Type
Frame synchronized (sidestream)
Register 36 Bit 4
Set to zero
Scrambler
Self-synchronized
Register 36 Bit 4
PRELIMINARY PRODUCT INFORMATION
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11
Register 31
Bit 7 to Bit 0
s16
to s9
Register 30
Bit 7 to Bit 0
s8
to s1
STEL-1109
Type
Set to one
The Mask, Init, and SSync fields can be programmed
for different scrambler configurations. For example, the
DAVIC Scrambler configuration shown in FigureÊ4 can
be implemented by programming the Mask, Init, and
SSync fields with the values indicated by Table 7.
Table 7. Sample Scramble Register Values
Parameter
Generator
Polynomial
(Mask Reg)
Characteristic
p(x) = x 15 + x 14 + 1
Configuration Register Setting
Register 35
Register 34
Register 33
Bit 7 to Bit 0
Bit 7 to Bit 0
Bit 7 to Bit 0
0000Ê0000
0110Ê0000
0000Ê0000
Seed
(INIT Reg)
0000A9 Hex
Register 32
Bit 7 to Bit 0
0000Ê0000
Scrambler
Type
Frame synchronized (sidestream)
Register 36 Bit 4
Set to zero
Register 31
Bit 7 to Bit 0
0000Ê0000
Register 30
Bit 7 to Bit 0
1010 1001
Reed-Solomon Encoder
The STEL-1109 uses a standard Reed-Solomon (RS)
Encoder for error correction encoding of the serial data
stream.
Reed-Solomon decoding circuitry along with the other
parameters.
The error correction encoding uses GF (256) and can be
programmed for an error correction capability of 1 to
10, a block length of 3 to 255, and one of two primitive
polynomials using the data fields listed in Table 8.
When DATAEN is high and the RS Encoder is enabled,
the serial data stream both passes straight through the
RS Encoder and also into encoding circuitry. The
encoding circuitry computes a checksum that is 2T
bytes long for every k bytes of input data. After the
last bit of each block of k bytes of input data, the RS
Encoder inserts its checksum (2T bytes of data) into the
data path. There is no adverse effect to letting TCLK or
TSDATA continue to run during the checksum; the data
input will be ignored. CKSUM (pin 35) will be asserted
high to indicate that the checksum bytes are being
inserted into the data stream and will be lowered at the
end of the checksum data insertion. The width of the
CKSUM pulse is 2T bytes.
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0
0
1
0
1
0
1
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
EX-OR
AND
EX-OR
Enable
The STEL-1109 registers include two bits for
determining the bit order for data into and checksum out
of the RS Encoder circuitry. Set these to match the
STEL-1109
1
Randomized Data
Clear Data Input
WCP 52984.c-4/26/97
Figure 4. DAVIC Scrambler
12
PRELIMINARY PRODUCT INFORMATION
Table 8. Reed-Solomon Encoder Parameters
Field Name
Configuration Register
PP
36H (bit 7)
Description
1-bit field for selecting Primitive Polynomial:
0 ⇒ p(x) = x8 + x 4 + x 3 + x 2 + 1
1 ⇒ p(x) = x8 + x 7 + x 2 + x + 1
T
36H (bits 3-0)
4-bit field for setting Error Correction Capability. Programmable over the range
of 1 to 10.
K
37H (bits 7-0)
8-bit field for setting User Data Packet Length (K) in bytes.
Programmable over the range of 1 to (255 - 2T). [ Net block length, N = K + 2T ]
LDLSBF
39H (bit 4)
Determines whether the first bit of the serial input is to be the MSB (bit 4 = 0) or
LSB (bit 4 = 1) of the byte applied to the RS Encoder.
TRLSBF
39H (bit 5)
Determines whether the MSB (bit 5 = 0) or LSB (bit 5 = 1) of the RS Encoder
checksum byte is to be the first bit of the serial output data.
Notes:
1. GF (256).
Code generator polynomial 1 is used when PP=0:
2.
3.
Code generator polynomial 2 is used when PP=1.
G(x) =
G(x) =
119 + 2T
∏ (x − α ) α = 02
i
H
i =120
2T −1
∏ (x − α ) α =
i
i=0
02H
SYMBOL MAPPER BLOCK
Bit Mapper
The Symbol Mapper Block (Figure 5) maps the serial
data bits output by the Bit Encoder Block to symbols,
differentially encodes the symbols, and (in 16QAM)
maps the symbols to one of five constellations. The
Symbol Mapper Block functions are modulation
dependent. The modulation mode also defines the
number of bits per symbol. The Symbol Mapper Block
outputs 2 bits for each symbol to each of the two
Nyquist (FIR) Filters.
The Bit Mapper receives serial data and maps the serial
data bits to output symbol bits (I1** , I0**, Q1**, and Q0** ).
There are four output bits per symbol even in BPSK and
QPSK modes. In BPSK, all bits are set equal to each
other. In QPSK, each input symbol bit drives a pair of
output bits. The four symbol bits are routed to the
Differential Encoder in parallel.
ENCODED
SERIAL DATA
1
DIFFEN
I[1:0]**
Q[1:0]**
I[1:0]*
Q[1:0]*
Bit
Mapper
4
Differential
Encoder
4
Symbol
Mapper
1
2
I[1:0]
Q[1:0]
2
For BPSK modulation, each bit (symbol = b0 ) of the
input serial data stream is mapped directly to I1**, Q1** ,
I0**, and Q0 ** (i.e., I1** = I0 **= Q1** = Q0 **= b 0 ). Thus, bit
mapping has no affect on the respective value of the
symbolÕs four bits, as shown in Table 9.
For QPSK modulation, each pair of bits (a dibit) forms a
symbol (b0 b1 ). The QPSK dibit is mapped so that
I1*Ê=ÊI0** and Q1** = Q0**, as shown in Table 9.
WCP 52985.c-4/26/97
Figure 5. Mapping Block Functional Diagram
PRELIMINARY PRODUCT INFORMATION
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For 16QAM, every four bits (a nibble) forms a symbol
(b0b 1b 2b 3). The 16QAM nibble is mapped to I 1** , Q1**, I0**,
and Q0**, as shown in Table 9.
13
STEL-1109
Table 9. Bit Mapping Options
Bit-To-Symbol Mapping
b0
b1
b2
Mode
**
**
**
**
BPSK
I1 Q1 I0 Q0
N/A
N/A
QPSK
I1 ** I0**
Q1 ** Q0**
N/A
QPSK
Q1 ** Q0**
I1 ** I0**
N/A
16QAM
I1 **
I0 **
Q1 **
**
**
16QAM
Q1
Q0
I1 **
**
**
16QAM
I0
I1
Q0 **
**
**
16QAM
Q0
Q1
I0 **
**
**
16QAM
I1
Q1
I0 **
**
**
16QAM
Q1
I1
Q0 **
**
**
16QAM
I0
Q0
I1 **
**
**
16QAM
Q0
I0
Q1 **
Note: b0 is the first serial data bit to arrive at the Bit Mapper
b3
N/A
N/A
N/A
Q0 **
I0 **
Q1 **
I1 **
Q0 **
I0 **
Q1 **
I1 **
Bit Mapping
Mod Mode
Register 2D Register 2C bits
bits 6-4
3,2
XXX
XX0
XX1
000
001
010
011
100
101
110
111
1X
00
00
01
01
01
01
01
01
01
01
Differential Encoder
The Differential Encoder encodes the bits (i.e., I1**, I0** ,
Q1** , and Q0** ) of each symbol received from the Bit
Mapper to determine the output bit values (i.e., I1*, Q1*,
I0*, and Q0*), which are routed to the Symbol Mapper.
If differential encoding is enabled, then the results are
described below for each modulation type.
The differential encoder can be either enabled or
bypassed under the control of either a register bit or a
user supplied control signal (DIFFEN pin 70). The
selection between user input pin control or register
control is made in another register bit, as shown in
Table 10.
In BPSK mode, the next output bit is found by XORing
the input bit with the current output bit. The result is a
180 degree phase change if the output is high and
0Êdegrees if the output is low.
BPSK
QPSK
Table 10. Differential Encoder Control
Level/Value
Encoding off (continuously)
In QPSK mode, the next output dibit is found by
XORing the input dibit with the current output dibit.
Table 11 shows the results of the differential encoding
performed for QPSK modulation and the resulting
phase shift. In the table, I = I1 = I0 and Q = Q1= Q0.
Register 38
Bits 1,0
0,1
Encoding on (continuously)
1,1
Encoding enabled by pin 70
high - enable the Differential Encoder
low - disable the Differential Encoder
X,0
16QAM
In 16QAM mode, the differential encoding algorithm is
the same as in QPSK. Only the two MSBÕs, I 1** and Q1**
are encoded. The output bits I 0* and Q 0* are set equal to
the inputs bits I0** and Q0** .
For any modulation mode, if differential encoding is
disabled then:
I1*Q1*I0*Q0*Ê=Ê I1**I0**Q1** Q0**
STEL-1109
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14
PRELIMINARY PRODUCT INFORMATION
Table 11. QPSK Differential Encoding and Phase Shift
Current Input
(IQ)
Current Output
(IQ)
Next Output
(IQ)
00
00
00
01
01
-90 (CW)
10
10
90 (CCW)
11
11
180
00
01
-90 (CW)
01
11
180
10
00
0
11
10
90 (CCW)
00
10
90 (CCW)
01
00
0
10
11
180
11
01
90 (CCW)
00
11
180
01
10
90 (CCW)
10
01
-90 (CW)
11
00
0
01
10
11
Phase Shift
(degrees)
0
Symbol Mapper
The Symbol Mapper receives I1*, Q1*, I 0*, Q0 * of each
symbol. Based on the signal modulation and the
symbol mapping selection, the Symbol Mapper block
maps the symbol to a constellation data point
(I1,Q1,I0 ,Q 0 ). The Symbol Mapping field (bits 7-5 of
Configuration Register 2EH) will map the four input bits
to a new value, as indicated in Table 12.
Q
11
3
11
For BPSK and QPSK, the settings of the symbol to
constellation mapping bits is ignored.
The
constellations for BPSK (Figure 6) and QPSK (Figure 7)
are shown below. I1Q1 values are indicated by large,
bold font (00 and 11) and I0Q0 values by the smaller
font (00 and 11).
1
-3
-1
1
3
I
-1
00
-3
00
WCP 52999.c-10/29/97
Figure 6. BPSK Constellation
PRELIMINARY PRODUCT INFORMATION
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15
STEL-1109
Q
Q
01
11
10
00
00
10
3
10
01
1
-3
00
11
-1
11
1
01
-3
3
-1
1
11
01
1
3
I
I
10
00
10
00
-1
00
10
00
01
11
10
-3
01
11
11
01
WCP 52987.c-10/29/97
WCP 52986.c-10/29/97
Figure 7. QPSK Constellation
Figure 8. Natural Mapping Constellation
Table 12. Symbol Mapping Selections
16QAM
For 16QAM modulation, the Symbol Mapper maps
each input symbol to one of the 16QAM constellations.
The specific constellation is programmed by the Symbol
Mapping field (bits 7-5 of Configuration Register 2E H)
to select the type of symbol mapping. If the MSB of the
Symbol Mapping field is set to 0, the mapping will be
bypassed and I 1Q1I0Q0 = I1 * Q 1*I0*Q0 * . The resulting
constellation (Figure 8) is the natural constellation for
the STEL-1109.
Mapping
Selection
Natural
Register 2E
Bits 7-5
0XX
Gray
100
DAVIC
101
Left
110
Right
111
If the MSB of the Symbol Mapping field is set to 1, bits
6-5 can select any of four possible types of symbol
mapping (Gray, DAVIC, Left, or Right), as indicated by
Table 12.
Table 13 summarizes the symbol mapping and the
resulting constellations are shown in Figure 8 and
Figure 9. In these figures, I1Q1 are indicated by large,
bold font (00, 01, 10, and 11) and I0Q0 by the
smaller font (00, 01, 10, and 11).
STEL-1109
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PRELIMINARY PRODUCT INFORMATION
Table 13. Symbol Mapping
Input Code
Natural
Mapping
(Bypass)
I 1 * Q1* I0 * Q0 *
0000
Gray
I 1 * Q1* I0 * Q0 *
0011
DAVIC
I 1 * Q1* I0 * Q0 *
0011
Left
I 1 * Q1* I0 * Q0 *
0011
Right
I 1 * Q1* I0 * Q0 *
0011
Output
Code
I 1 Q1 I0 Q0
0000
0001
0010
0001
0010
0001
0001
0010
0001
0010
0001
0010
0010
0011
0000
0000
0000
0000
0011
0100
0110
0110
0101
1010
0100
0101
0111
0111
0111
1011
0101
0110
0100
0100
0100
1000
0110
0111
0101
0101
0110
1001
0111
1000
1001
1001
1010
0101
1000
1001
1000
1000
1000
0100
1001
1010
1011
1011
1011
0111
1010
1011
1010
1010
1001
0110
1011
1100
1100
1100
1100
1100
1100
1101
1101
1110
1101
1110
1101
1110
1110
1101
1110
1101
1110
1111
1111
1111
1111
1111
1111
Q
Q
11
01
01
01
10
-1
1
00
1
01
11
10
11
00
-3
10
11
11
3
01
10
00
00
-3
-1
1
00
1
3
10
I
I
10
00
00
00
11
10
10
01
00
11
11
10
11
Figure 10. Left Coded Constellation
Figure 9. Gray Coded Constellation
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01
WCP 52989.c-4/26/97
WCP 52988.c-10/29/97
PRELIMINARY PRODUCT INFORMATION
01
01
11
10
01
00
17
STEL-1109
NYQUIST FIR FILTER
Q
11
01
10
11
10
10
00
1
00
-3
The finite impulse response (FIR) filters are used to
shape each transmitted symbol pulse by filtering the
pulse to minimize the sidelobes of its spectrum. The
Symbol Mapper Block outputs the I1I0 data to a pair of
I-channel FIR filters and the Q1Q0 data to a pair of
Q-channel FIR filters. Figure 13 shows the filter block
diagram for a channel pair (I or Q). The FIR filter can
be bypassed altogether or, in BPSK or QPSK modes,
individual channels can be turned on and off which
changes the effective filter gain. Table 14 shows the
various FIR configuration options.
00
-1
1
3
01
I
01
00
00
10
10
11
Table 14. FIR Filter Configuration Options
10
11
01
11
WCP 52990.c-4/26/97
Figure 11. DAVIC Coded Constellation
Q
01
11
10
10
00
00
-3
-1
1
00
1
3
01
I
01
00
00
10
11
10
01
Register 2E
Bits 4-1
XXXX
Register 2C
Bit 1
1
16QAM
Unity
1010
0
BPSK/QPSK
Unity
0000
0
BPSK/QPSK
x2
1111
0
BPSK/QPSK
x3
1010
0
Table 15. FIR Filter Coefficient Storage
10
11
Gain
N/A
Each of the 32 -tap, linear phase, FIR filters use
16Êten-bit, coefficients, which are completely programmable for any symmetrical (mirror image) polynomial. The FIR filter coefficients are stored in
addresses 09H - 28H, using two addresses for each 10-bit
coefficient as shown in Table. The coefficients are stored
as TwoÕs Complement numbers in the range -512 to
+511 (200H to 1FF H). The filter is always constrained to
have symmetrical coefficients, resulting in a linear
phase response. This allows each coefficient to be
stored once for two taps, as shown in Table 15.
11
01
Mode
No FIR Filter
MSB
(Bits 9-8)
0A H
0CH
0EH
10H
É
É
22H
24H
26H
28H
11
WCP 52991.c-4/26/97
Figure 12. Right Coded Constellation
Note:
STEL-1109
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18
LSB
(Bits 7-0)
09H
0BH
0DH
0F H
É
É
21H
23H
25H
27H
Filter Taps
Taps 0 and 31
Taps 1 and 30
Taps 2 and 29
Taps 3 and 28
É
É
Taps 12 and 19
Taps 13 and 18
Taps 14 and 17
Taps 15 and 16
For MSB storage, only bits 1-0 are used.
PRELIMINARY PRODUCT INFORMATION
I1/Q1
X2
FIR
1 M
U
0 X
COEFFICIENT
L
O
G
I
C
1
I0/Q0
M
U
0 X
FIR
OUT
2
CLRFIR
BYPASS
WCP-52992.c-4/26/97
Figure 13. Nyquist FIR Filter
INTERPOLATING FILTER
The Interpolating Filter, shown in Figure 14, is a
configurable, three-stage, interpolating filter. The filter
increases the STEL-1109Õs sampling rate (to permit the
wide range of RF carrier frequencies possible) by
interpolating between the FIR filter steps at the master
clock frequency.
This smoothes the digital
representation of the signal which removes spurious
signals from the spectrum.
momentary ÒhitsÓ of broad band spectral noise, then
the digital gain is too high. The interpolation filter gain
is the first place to adjust gain because it does not
directly affect the shape of the signal spectrum and it
has a very wide adjustment range. Overall, gain can
affected in the FIR filter function, the interpolation gain
function, and by the number of interpolation stages
(and therefore accumulators) used.
Normally, three interpolation stages are used, but there
is a bypass option for use when the interpolation is very
high. It should be used only as a last resort after all
other gain reduction options have been exercised
because of the severe impact to spurious performance.
The register bits that affect the interpolation filter
functions are shown inTable 16 and Table 17.
Table 16. Interpolation Filter Bypass Control
Number of
Interpolation Stages
Selected
3
Interpolation Filter Bypass
Register 2B Bits 5,4
2
0Ê1
2
1
1Ê0
1Ê1
0Ê0
Data Enable
Table 17. Interpolation Filter Signal Level Control
Bypass
2
16
Sample
Clock
3-Stage
Differentiator
Gain Control
16
G
a
i
n
32
3-Stage
Integrator
11
4
Master Clock
WCP 52993.c-5/2/97
Figure 14. Interpolation Filter Block Diagram
The interpolation filter contains accumulators. As the
interpolation ratio grows larger, the number of
accumulations per period of time increases. If the
interpolation ratio becomes too large, the accumulator
will overflow which will destroy the output spectral
characteristics.
To compensate for this, the
interpolation filter has a gain function. This gain is
normally set empirically. If the output spectrum is
broad band noise or if it appears correct but has regular
PRELIMINARY PRODUCT INFORMATION
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Gain Factor
(Relative)
20
Filter Gain Control
Register 2A Bits 7-4
0H
21
1H
2
2
2H
2
3
3H
2
4
4H
25
5H
2
6
6H
2
7
7H
2
8
8H
29
9H
2
10
AH
2
11
BH
2
12
CH
2 13
DH
2 14
EH
15
FH
2
19
STEL-1109
MODULATOR
CONTROL UNIT DESCRIPTION
The interpolated I and Q data signals are input from the
Interpolation Filter, fed into two complex modulators,
and multiplied by the sine and cosine carriers which are
generated by the NCO. The I channel signal is
multiplied by the cosine output from the NCO and the
Q channel signal is multiplied by the sine output. The
resulting modulated sine and cosine carriers are
applied to an adder and either added or subtracted
together according to the register settings shown in
Table 18. This provides control over the characteristics
of the resulting RF signal by allowing either or both of
the two products to be inverted prior to the addition.
BUS INTERFACE UNIT
The Bus Interface Unit (BIU) contains the Configuration
Registers (58 programmable 8-bit registers). The Reset
( RST ) input signal is the master reset for the
STEL-1109. Asserting a low on RST will reset the
contents of all Configuration Registers to 00H (as well as
clearing the data path registers). Asserting a high on
RST enables normal operation. After power is applied
and prior to configuring the STEL-1109, a low should
be asserted on RST . Since RST is asynchronous, the
CLKEN input should be held low whenever RST is
low.
Data Enable Output. The DATAENO output pin is a
modified replica of the DATAEN input. DATAENO is
asserted as a high 2 symbols after DATAEN goes high
and it is asserted as a low 13 symbols after DATAEN
goes low. In this way, a high on the DATAENO line
indicates the active period of the DAC during
transmission of the data burst. However, if the guard
time between the current and next data burst is less
than 13 symbols, then the DATAENO line will be held
high through the next burst.
The parallel address bus (ADDR5-0) is used to select
one of the 58 Configuration Registers by placing its
address on the ADDR 5-0 bus lines. The data bus
(DATA7-0) is an 8-bit, bi-directional data bus for writing
data into or reading data from the selected
Configuration Register.
The access operation is performed using the control
signals DSB , CSEL, and WR. The Chip Select
( CSEL) input signal is used to enable or disable access
operations to the STEL-1109. When a high is asserted
on CSEL, all access operations are disabled and a low
is asserted to enable the access operations. The
CSELinput only affects Configuration Register access
and has no effect on the data path.
Table 18. Signal Inversion Control
Output of Adder Block
Sum = I . cos(ωt) + Q . sin(ωt)
Invert I/Q Channel
Register 2B Bits 1,0
0Ê0
Sum = ÐI . cos(ωt) + Q . sin(ωt)
0Ê1
Sum = I . cos(ωt) Ð Q . sin(ωt)
1Ê0
Sum = ÐI . cos(ωt) Ð Q . sin(ωt)
1Ê1
The Data Strobe ( DSB ) input signal is used to write the
data that is on the data bus (D A T A 7-0 ) into the
Configuration Register selected by ADDR 5-0. The
Write/Read ( WR) input signal is used to control the
direction of the Configuration Register access
operation. When WR is high, the data in the selected
Configuration Register is output onto the DATA7-0 bus.
When WR is low, the rising edge of DSB is used to
latch the data on the DATA 7-0 bus into the selected
Configuration Register. (Refer to the Write and Read
Timing diagrams in the Timing Diagrams section.)
10-BIT DAC
The 10-bit Digital-to-Analog Converter (DAC) receives
the modulated digital data and the Master clock. The
DAC samples the digital data at the rate of the Master
clock and outputs a direct analog RF signal at a
frequency of 5 to 65 MHz. The DAC outputs, OUT and
OUTN, are complementary current sources designed to
drive double terminated 50Ω or 75Ω (25Ω or 37.5Ω
total) load to ground. The nature of digitally sampled
signals creates an image spur at a frequency equal to
the Master Clock minus the output RF frequency. This
image spur should be filtered by a user supplied low
pass filter. For best overall spurious performance, the
gain of the STEL-1109 should be the highest possible
(before digital overflow occurs - see Interpolation Filter
discussion).
STEL-1109
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Some of the Configuration Register data fields are used
for factory test and must be set to specific values for
normal operation. These values are noted in Table 3.
CLOCK GENERATOR
The timing of the STEL-1109 is controlled by the Clock
Generator, which uses an external master clock (CLK)
and programmable dividers to generate all of the
internal and output clocks. There are primarily two
20
PRELIMINARY PRODUCT INFORMATION
clock systems, the auxiliary clock and the data path
timing signals (bit, symbol, and sampling rate signals).
The auxiliary clock (ACLK) output is primarily for use
in master mode where users may need a clock to run
control circuits during the guard time between bursts
(when CLKEN is low and BITCLK has stopped). The
output clock rate is set by the frequency (fCLK ) of the
external master clock and the value (N) of the Auxiliary
Clock Rate Control field (bits 3-0 of Configuration
Register 2AH). The clock rate is set to:
ACLK =
duty cycle for BPSK and QPSK modes. It also has a
50% duty cycle in 16QAM mode when N+1 is even. If
N+1 is odd, then BITCLK will be high for (N÷2)+1
clocks and then low for N÷2 clocks. (Refer to the Bit
Clock Synchronization Timing diagram in the Timing
Diagrams section.)
The BITCLK frequency is determined by :
BITCLK =
fCLK
N +1 2 ≤ N ≤ 15
CLK
(N+1) ∗ K
K = 1 for 16QAM,
2 for QPSK,
4 for BPSK
3 ≤ N ≤ 4095
NCO
If N is set to 1 or 0, the ACLK output will remain set
high, thereby disabling this function. If the ACLK
signal is not required, it is recommended that it be set
in this mode to conserve power consumption. The
ACLK output is a pulse that will be high for 2 cycles of
C L K and low for (N-1) CLK cycles. Unlike other
functions, the ACLK output is not affected by CLKEN.
A 24-bit, Numerically Controlled Oscillator (NCO) is
used to synthesize a digital carrier for output to the
Modulator. The NCO gives a frequency resolution of
about 6 Hz at a clock frequency of 100 MHz. The NCO
also uses 12-bit sine and cosine lookup tables (LUTs) to
synthesize a carrier with very high spectral purity, typically better than -75 dBc at the digital outputs.
The data path timing is based on the ratio of the master
clock frequency to the symbol data rate. The ratio must
be a value of four times an integer number (N+1). The
value of N must be in the range of 3 to 4095. This value
is represented by a 12 bit binary number that is
programmed by LSB and MSB Sampling Rate Control
fields [Configuration Register 29H (LSB) and bits 3-0 of
Configuration Register 39 H (MSB)], which sets the
SYMPLS frequency [based on the frequency (fCLK) of
the external master clock] to:
The STEL-1109 provides register space for three
different carrier frequencies. The carrier frequency that
will drive the modulator is selected by the FCWSEL 1-0
control pin input signals. A high on the NCO LD input
pin causes the registers selected by FCWSEL to drive
the NCO at the frequency determined by the register
value.
Symbol Rate =
1 ∗ fCLK
4 N + 1 3 ≤ N ≤ 4095
The symbol pulse (SYMPLS) signal output is intended
to allow the user to verify synchronization of the
external serial data ( TSDATA) with the STEL-1109
symbol timing. SYMPLS is normally low and pulses
high for a period of one CLK cycle at the point where
the last bit of the current symbol is internally latched by
the falling edge of the internal BIT Clock (BITCLK)
signal. (Refer to the Timing Diagrams section.)
The internal BITCLK period is a function of the MOD
field (bits 3-2 of Configuration Register 2CH), which
determines the signal modulation. BITCLK has a 50%
PRELIMINARY PRODUCT INFORMATION
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The NCOÕs frequency is programmable using the NCO
field (Configuration Registers 08H -00H). The nine 8-bit
registers at addresses 00H through 08 H are used to store
the three 24-bit frequency control words FCW ÔAÕ, FCW
ÔBÕ and FCW ÔCÕ as shown in Table 19.
The output carrier frequency of the NCO (fCARR) will be:
fCARR =
fCLK . FCW
224
where, fCLK is the frequency of the CLK input signal.
The FZSINB field (bit 7 Configuration Register 2DH)
controls the sine component output of the NCO. This
can be used in BPSK to rotate the constellation 45
degrees (to Ôon axisÕ modulation). For normal
operation, it should be set to one.
21
STEL-1109
Table 19. FCW Selection
FCWSEL1-0
FCW Selected
23 - 16
FCW Value Bits
15 - 8
7-0
00
FCW A
Register 02H Bits 7 - 0
Register 01H Bits 7 - 0
Register 00H Bits 7 - 0
01
FCW B
Register 05H Bits 7 - 0
Register 04H Bits 7 - 0
Register 03H Bits 7 - 0
10
FCW C
Register 08H Bits 7 - 0
Register 07H Bits 7 - 0
Register 06H Bits 7 - 0
11
Zero Frequency
STEL-1109
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22
PRELIMINARY PRODUCT INFORMATION
TIMING DIAGRAMS
CLOCK TIMING
tCLK
CLK
PIN 28
tCLKH
tCLKL
tr
tf
WCP 52787.c-3/26/97
Table 20. Clock Timing AC Characteristics
(V DD = 3.3 V ±10%, VSS = 0 V, Ta = Ð40° to 85° C)
Symbol
Parameter
Clock Frequency (
tCLK
Clock Period
tCLKH
1
t CLK
Min.
Nom.
)
Max.
165
Units
MHz
6
nsec
Clock High Period
2.5
nsec
tCLKL
Clock Low Period
2.5
nsec
tR
Clock Rising Time
0.5
nsec
tF
Clock Falling Time
0.5
nsec
Conditions
PULSE WIDTH
tCEL
CLKEN
PIN 26
tRSTL
RSTB
PIN 67
NCO LD
PIN 71
tNLDH
WCP 52930.c-4/26/97
Table 21. Pulse Width AC Characteristics
(V DD = 3.3 V ±10%, VSS = 0 V, Ta = Ð40° to 85° C)
Symbol
Parameter
Min.
Nom.
Max.
Units
tCEL
Clock Enable (CLKEN) Low
4
nsec
tRSTL
Reset (RSTB) Low
5
nsec
tNLDH
NCO Load (NCO LD) High
1
CLK cycles
PRELIMINARY PRODUCT INFORMATION
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23
Conditions
STEL-1109
BIT CLOCK SYNCHRONIZATION
CLK
PIN 28
CLKEN
PIN 26
tCESU
TCLK
PIN 19
tCO
BITCLK
PIN 40
tCO
2 (N +1) BPSK
(N +1) QPSK
See Note 1
See Note 2
N +1 16QAM
2 n = Odd
N +2 16QAM
2 n = Even
WCP 52786.c-5/2/97
Note 1: BITCLK will be forced high on the second rising edge of CLK following the rising edge of TCLK.
Note 2: The period of time that BITCLK is high is measured in cycles of CLK (e.g. (N + 1) in QPSK). "N" is a 12 bit
binary number formed by taking bits 3-0 of Configuration Register 39 H as the MSB's and taking bits 7-0 of
Configuration Register 29H as the LSB's. The BITCLK low period is the same except for 16QAM when "N"
is even in which case the low period is (N/2) yielding the correct BITCLK period but not a perfect
squarewave.
Table 22. Bit Clock Synchronization AC Characteristics
(V DD = 3.3 V ±10%, VSS = 0 V, Ta = Ð40° to 85° C)
Symbol
tCO
Parameter
Min.
Clock to BITCLK, SYMPLS, DATAENO, or
Nom.
Max.
2
Units
Conditions
nsec
AUXCLK edge
tCESU
Clock Enable (CLKEN to TCLK Setup)
STEL-1109
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3
24
nsec
PRELIMINARY PRODUCT INFORMATION
INPUT DATA AND CLOCK TIMING
SLAVE MODE
MASTER MODE
NOTE 1
DON'T CARE
TCLK
TCLK
BITCLK NOTE 2 DON'T CARE
BITCLK
tSU
NOTE 3
tHD
TSDATA
NOTE 1
tCLK
tSU
tHD
TSDATA
WCP 52935.c -5/2/97
Note 1: Mode is determined by setting of BIT 7 in Configuration Register 2C H. Bit 7 high is slave mode; Bit 7
low is master mode.
Note 2: In slave mode, even though BITCLK is shown as ÒDon't CareÓ, it should be noted that internally the
STELÊ1109 will relatch the data on the next falling edge of BITCLK. Thus, avoid changing the control
signal inputs (DATAEN, DIFFEN, RDSLEN, SCRMEN) at the falling edges of BITCLK.
Note 3: In the STEL-1109, data is latched on the rising edge of the CLK that follows the falling edge of BITCLK.
Thus, the data validity window is one CLK period (tCLK) delayed. CLK not shown.
Table 23. Input Data and Clock AC Characteristics
(V DD = 3.3 V ±10%, VSS = 0 V, Ta = Ð40° to 85° C)
Symbol
Parameter
Min.
Nom.
Max.
Units
tCLK
Clock Period
6
nsec
tSU
TSDATA to Clock Setup
2
nsec
tHD
TSDATA to Clock Hold
2
nsec
PRELIMINARY PRODUCT INFORMATION
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25
Conditions
STEL-1109
WRITE TIMING
tAVA
tWAHD
tWASU
Address
ADDR[5-0]
tCSHD
tCSSU
CSEL
Pin 72
tWRHD
tWRSU
WR
Pin 74
tDSBL
DSB
Pin 73
tDH
tDSU
Data
DATA[7-0]
WCP 52717.c-5/2/97
Table 24. Write Timing AC Characteristics
(V DD = 3.3 V ±10%, VSS = 0 V, Ta = Ð40° to 85° C)
Symbol
Parameter
Min.
Nom.
Max.
Units
tWASU
Write Address Setup
10
nsec
tWAHD
Write Address Hold
6
nsec
20
nsec
tAVA
Address Valid Period
tCSSU
Chip Select CSEL Setup
5
nsec
tCSHD
Chip Select ( CSEL) Hold
3
nsec
tWRSU
Write Setup ( WR)
5
nsec
tWRHD
Write Hold ( WR)
3
nsec
tDSBL
Data Strobe Pulse Width
10
nsec
tDH
Data Hold Time
1
nsec
tDSU
Data Setup Time
3
nsec
STEL-1109
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26
Conditions
PRELIMINARY PRODUCT INFORMATION
READ TIMING
tAVA
tADV
Address
CS
WR
tDICSH
tDVCSL
tADIV
Data
WCP 52928.c-5/2/97
Table 25. Read Timing AC Characteristics
(V DD = 3.3 V ±10%, VSS = 0 V, Ta = Ð40° to 85° C)
Symbol
Parameter
Min.
Nom.
Max.
tAVA
Address Valid Period
tADV
Address to Data Valid Delay
tADIV
Address to Data Invalid Delay
6
nsec
tDVCSL
Data Valid After Chip Select Low
2
nsec
tDICSH
Data Invalid After Chip Select High
PRELIMINARY PRODUCT INFORMATION
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20
Units
nsec
9
1
27
Conditions
nsec
nsec
STEL-1109
NCO LOADING (USER CONTROLLED)
OUTPUT
OLD FREQ.
NEW FREQ.
tFCWHD
tFCWSU
FCWSEL1-0 DON'T CARE
VALID
DON'T CARE
tLDPIPE
NCO_LD
NOTE 1
WCP 52909.c-5/2/97
NCO LOADING (AUTOMATIC)
OUTPUT
ZERO
SELECTED FREQUENCY
ZERO
tDENHV
FCWSEL1-0
DON'T CARE
VALID
DON'T CARE
tDENLZ
DATAENO
tDOFCWV
tDOFCWI
WCP 52909.c-5/2/97
NOTE 1: The first rising edge of CLK after NCO LD goes high initiates the load process.
Table 26. NCO Loading AC Characteristics
(V DD = 3.3 V ±10%, VSS = 0 V, Ta = Ð40° to 85° C)
Symbol
tLDPIPE
Parameter
Min.
NCO-LD to Change in Output Frequency Pipeline
Nom.
Max.
23
Units
Conditions
CLK cycles
Delay
tFCWSU
FCWSEL1-0 to NCO-LD Setup
tFCWHD
FCWSEL1-0 to NCO-LD Hold
tDENLZ
DATAENO Low to Zero Frequency Out Delay
23
CLK cycles
tDENHV
DATAENO High to Valid Frequency Out Delay
23
CLK cycles
tDOFCWV
DATAENO to FCWSEL1-0 Valid
tDOFCWI
DATAENO to FCWSEL1-0 Invalid
STEL-1109
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3
10
CLK cycles
3
10
28
CLK cycles
CLK cycles
CLK cycles
PRELIMINARY PRODUCT INFORMATION
DIGITAL OUTPUT TIMING
CLK
tCO
AUXCLK
Note 1
tACKL
tCO
tACKH
BITCLK
tCO
tSPH
SYMPLS
tCO
DATAENO
tCO
tDENOD
WCP 52908.c-5/2/97
NOTE 1:
AUXCLK shown for "n" equal to 2: where n is the 4-bit binary value in Configuration
Register 2AH, BITSÊ3-0.
Table 27. Digital Output Timing AC Characteristics
(V DD = 3.3 V ±10%, VSS = 0 V, Ta = Ð40° to 85° C)
Symbol
tCO
Parameter
Min.
Nom.
Clock to BITCLK, SYMPLS, DATAENO,
Max.
2
Units
Conditions
nsec
or AUXCLK edge
tACKH
Auxiliary Clock (ACLK) High
2
CLK cycles
tACKL
Auxiliary Clock (ACLK) Low
(n-1)
CLK cycles
tSPH
Symbol Pulse (SYMPLS) High
1
CLK cycles
tDENOD
BITCLK Low to DATAENO edge
1
CLK cycles
Note 1
Notes:
1.
ÒnÓ is the 4 bit binary value in Configuration Register 2AH , bits 3-0.
PRELIMINARY PRODUCT INFORMATION
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29
STEL-1109
DATAEN TO DATAENO TIMING
tDENSP
DATAEN
tDIHDO
tSPDEN
tSPDEN
DATAENO
tDLDO
tDENSP
SYMPLS
WCP 52910.c-5/2/97
Table 28. DATAEN to DATAENO Timing AC Characteristics
(V DD = 3.3 V ±10%, VSS = 0 V, Ta = Ð40° to 85° C)
Symbol
tDIHDO
Parameter
Min.
DATAEN High to DATAENO High
Nom.
2
Max.
Units
Conditions
nd
SYMPLS
Note 1
th
SYMPLS
Note 1
tDLDO
DATAEN Low to DATAENO Low
13
tSPDEN
SYMPLS (trailing edge) to DATAEN Setup
3
nsec
tDENSP
DATAEN to SYMPLS (trailing edge) Setup
5
nsec
Notes:
1.
Shown for Configuration Register 36H, bit 6=0 (No Reed-Solomon). If bit 6 of Register 36H is a Ò1Ó, then the edges of
DATAENO will be delayed from those illustrated by 8, 4, or 2 SYMPLS for BPSK, QPSK, or 16QAM, respectively.
BURST TIMING EXAMPLES
Key:
The following seven timing diagrams are qualitative in
nature and meant to illustrate the functional
relationships between the control inputs and signal
outputs in various modes of burst operation. Use the
key at right to interpret the timing marks. Only the first
diagram is of a complete and realistic burst. The
remaining diagrams are too short in duration to show
DATAENO and CLKEN going low.
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
May
Change
from H to L
Will be
Changing
from H to L
May
Change
from L to H
Will be
Changing
from L to H
Don't Care.
Any Change
Permitted
Changing.
State
Unknown
Does Not
Apply
Center
Line is HighImpedance
“Off” State
WCP 53036.c-5/6/97
STEL-1109
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30
PRELIMINARY PRODUCT INFORMATION
SLAVE MODE, QPSK
BURST TIMING: FULL BURST
PIN
NAME
19
TCLK(1)
17
TSDATA
26
CLKEN
(B)
18
DATAEN
(C)
39 DATAENO(2)
(A)
(G)
(F)
(J)
(I)
(D)
(K)
70
DIFFEN(3)
29
RDSLEN
(L)
32
SCRMEN
(L)
(E)
(H)
(M)
(N)
Preamble
42
User Data
Guard Time
SYMPLS
WCP 52934.c -5/7/97
NOTES:
(1)
All input signals shown are derived from TCLK. Each edge is delayed from a TCLK edge by typically 6 to 18 nsec.
DATAENO does not depend on TCLK but its edges are synchronized to TCLK. TCLK itself can be turned off after DATAENI
goes low.
(2)
DATAENO shown at its minimum pipeline delay position. This is achieved by setting bit 6 of Configuration Register 36H to
zero. Reed-Solomon cannot be used in this mode. If bit 6 is set high, allowing Reed-Solomon an additional pipeline delay of
8Ê bits is inserted into the data path. This will shift both edges of DATAENO to the right by 8 cycles of TCLK.
(3)
If the preamble is not encoded the same as the user data, the DIFFEN control can be toggled in mid transmission as shown.
Otherwise, the DIFFEN control can be held high or low depending on encoding desired.
(A) First data bit transition on falling edge of TCLK (first of 14 preamble symbols). The data will be valid on the next rising edge of
TCLK.
(B) CLKEN rises on the same falling edge of TCLK that the data starts on. CLKEN is allowed to rise any time earlier than shown.
(C) DATAEN rises on the first rising edge of TCLK (middle of the first preamble bit).
(D) DATAENO rises on the falling edge of TCLK (at the end of the second symbol).
(E) DIFFEN rises on the rising edge of TCLK one symbol before the first user data symbol.
(F)
User data bits change on the falling edge of TCLK and must be valid during the next rising edge of TCLK.
(G) End of user data. Note that the data is allowed to go away immediately after it is latched in by the rising of TCLK which
occurs in the middle of the last user data bit.
(H) DIFFEN goes low on rising edge of TCLK (last user data symbol).
(I)
DATAEN goes low on rising edge of TCLK (on the cycle of TCLK after the last user data bit).
(J)
CLKEN must stay high until any time on or after the point where DATAENO goes low.
(K) DATAENO stays high until the 13th SYMPLS after DATAEN goes low.
(L) RDSLEN and SCRMEN go high on the first rising edge of TCLK in the User Data.
(M) RDSLEN goes low on the rising edge of TCLK (last user data symbol).
(N) SCRMEN goes low on the rising edge of TCLK (on the cycle of TCLK after the last user data bit).
PRELIMINARY PRODUCT INFORMATION
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31
STEL-1109
MASTER MODE, BPSK
BURST TIMING SIGNAL RELATIONSHIPS
CLKEN
BITCLK
TCLK
DATAEN
PI
TSDATA
PI
GUARD TIME
PI
PI
UI
UI
PREAMBLE
UI
UI
GI
USER DATA
DIFFEN
GI
GI
GI
GUARD TIME
NOTE 1
RDSLEN
SCRMEN
SYMPLS
DATAENO
NOTE 2
WCP 52911.c-5/6/97
SLAVE MODE, BPSK
BURST TIMING SIGNAL RELATIONSHIPS
CLKEN
BITCLK
TCLK
DATAEN
TSDATA
DIFFEN
PI
GUARD
TIME
PI
PI
PI
UI
PREAMBLE
UI
UI
USER DATA
UI
GI
GI
GI
GI
GUARD TIME
NOTE 1
RDSLEN
SCRMEN
SYMPLS
DATAENO
NOTE 2
WCP 52912.c-5/6/97
NOTE 1:
STEL receivers differentially decode relative to the last preamble symbol. To encode the
first symbol against a "zero" symbol reference instead, bring DIFFEN high at the
leading edge of the user data packet (dotted line).
NOTE 2:
If bit 6 of Configuration Register 36H is a "1" then the rising edge of DATAENO will be
delayed by eight cycles of BITCLK (dotted line). This is required if the Reed-Solomon
encoder is used.
STEL-1109
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PRELIMINARY PRODUCT INFORMATION
MASTER MODE, QPSK
BURST TIMING SIGNAL RELATIONSHIPS
CLKEN
BITCLK
TCLK
DATAEN
PI
TSDATA
GUARD TIME
PQ
PI
PQ
UI
PREAMBLE
UQ
UI
UQ
GI
USER DATA
DIFFEN
GQ
GQ
GI
GUARD TIME
NOTE 1
RDSLEN
SCRMEN
SYMPLS
DATAENO
NOTE 2
WCP 52840.c-5/7/97
SLAVE MODE, QPSK
BURST TIMING SIGNAL RELATIONSHIPS
CLKEN
BITCLK
TCLK
DATAEN
PI
TSDATA
GUARD TIME
PQ
PI
PREAMBLE
DIFFEN
PQ
UI
UQ
UI
USER DATA
UQ
GI
GQ
GI
GUARD TIME
GQ
NOTE 1
RDSLEN
SCRMEN
SYMPLS
DATAENO
NOTE 2
WCP 52839.c-5/7/97
NOTE 1:
STEL receivers differentially decode relative to the last preamble symbol. To encode the
first symbol against a "zero" symbol reference instead, bring DIFFEN high at the
leading edge of the user data packet (dotted line).
NOTE 2:
If bit 6 of Configuration Register 36H is a "1" then the rising edge of DATAENO will be
delayed by eight cycles of BITCLK (dotted line). This is required if the Reed-Solomon
encoder is used.
PRELIMINARY PRODUCT INFORMATION
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33
STEL-1109
MASTER MODE, 16QAM
BURST TIMING SIGNAL RELATIONSHIPS
CLKEN
BITCLK
TCLK
DATAEN
TSDATA
PI1 PQ1 PI0 PQ0 PI1 PQ1 PI0 PQ0 UI1 UQ1 UI0 UQ0 UI1 UQ1 UI0 UQ0 GI1 GQ1 GI0 GQ0 GI1 GQ1 GI0 GQ0
GUARD TIME
PREAMBLE
DIFFEN
USER DATA
GUARD TIME
NOTE 1
RDSLEN
SCRMEN
SYMPLS
DATAENO
NOTE 2
WCP 52913.c-5/6/97
SLAVE MODE, 16QAM
BURST TIMING SIGNAL RELATIONSHIPS
CLKEN
BITCLK
TCLK
DATAEN
TSDATA
PI1 PQ1 PI0 PQ0 PI1 PQ1 PI0 PQ0 UI1 UQ1 UI0 UQ0 UI1 UQ1 UI0 UQ0 GI1 GQ1 GI0 GQ0 GI1 GQ1 GI0 GQ0
GUARD TIME
DIFFEN
PREAMBLE
USER DATA
GUARD TIME
NOTE 1
RDSLEN
SCRMEN
SYMPLS
DATAENO
NOTE 2
WCP 52914.c-5/7/97
NOTE 1:
STEL receivers differentially decode relative to the last preamble symbol. To encode the
first symbol against a "zero" symbol reference instead, bring DIFFEN high at the
leading edge of the user data packet (dotted line).
NOTE 2:
If bit 6 of Configuration Register 36H is a "1" then the rising edge of DATAENO will be
delayed by eight cycles of BITCLK (dotted line). This is required if the Reed-Solomon
encoder is used.
STEL-1109
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34
PRELIMINARY PRODUCT INFORMATION
ELECTRICAL SPECIFICATIONS
The STEL-1109 electrical characteristics are provided by Table 29 through Table 31.
WARNING
Stresses greater than those shown in Table 29 may cause permanent damage to the
STEL-1109. Exposure to these conditions for extended periods may also affect the
STEL-1109Õs reliability.
Table 29. Absolute Maximum Ratings
Symbol
Parameter
Range
Units Note 1
T stg
Storage Temperature
Ð40 to +125
°C
VDDmax
Supply voltage on VDD
Ð0.3 to +4.6
volts
AV DDmax
Supply voltage on AVDD
Ð0.3 to +4.6
volts
5VDDmax
Supply voltage on 5VDD
Ð0.3 to +7.0
volts Note 2
AV SS
Analog supply return for AVDD
±10% of VDD
volts
VI(max)
Input voltage
Ð0.3 to V DD+0.3
volts
Ii
DC input current
± 30
mA
PDiss (max)
Power dissipation @ 85oC
690
mW Note 3
Note:
1.
All voltages are referenced to VSS.
2.
5VDD must be greater than or equal to VDD. This rule can be violated for a
maximimum of 100 msec during power up.
3.
See Duty Cycle Derating Curves (Figure 15)
PRELIMINARY PRODUCT INFORMATION
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35
STEL-1109
Duty Cycle (%)
100
90
80
70
60
50
25
30
35
40
45
50
55
60
65
70
75
80
85
Ambient Temperature (degrees C)
WCP 52994.c-4/26/97
Figure 15. Duty Cycle Derating versus Temperature (@3.3V)
Table 30. Recommended Operating Conditions
Symbol
Range NOTE 1
Parameter
Units
AV DD
Supply Voltage
+3.3 ± 10%
volts
5VDD
Supply Voltage
+5.0 ± 10%
volts Note 2
VDD
Supply Voltage
+3.3 ± 10%
volts
CLOAD
DAC Load Capcitance
≤ 20
pF
RLOAD
DAC Load Resistance
≤ 30K
ohms
Recommended DAC Load
37.5
ohms
VLOAD
DAC Output Voltage
≤ 1.25
Volts
Ta
Operating Temperature (Ambient)
Ð40 to +85
°C Note 3
Note:
1.
All voltages with respect to Vss and assume AV SSÊ=ÊVSS
2.
If interface logic is to be driven by VDD then connect the 5VDD pin to the
VDDÊsupply.
3.
Duty Cycle derating is required from +70 to +85 degrees.
STEL-1109
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PRELIMINARY PRODUCT INFORMATION
Table 31. DC Characteristics
(V DD = 3.3 V +/-10%, VSS = 0 V, Ta = -40° to 85° C)
Symbol
Parameter
Min.
Nom.
Max.
1.0
Units
IVDDQ
Supply Current, Quiescent
IVDD
Supply Current, Operational, VDD
1.9
mA/MHz
I5VDD
Supply Current, Operational, 5VDD
0.2
mA
IAV DD
Supply Current, Operational, AVDD
12.0
mA
VIHCLK
Clock High Level Input Voltage
VILCLK
Clock Low Level Input Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IIH
IIL
Static, no clock
volts
CLK, Logic '1'
volts
CLK, Logic '0'
volts
Other inputs, Logic '1'
0.8
volts
Other inputs, Logic '0'
High Level Input Current
10
µA
VIN = 5V DD
Low Level Input Current
Ð10
µA
VIN = VSS
2.4
VOL(max) Low Level Output Voltage
Output Short Circuit CurrentÊ
0.8
2.0
VOH(min) High Level Output Voltage
IOS
2.0
mA
Conditions
NOTE 3
3.0
VDD
volts
IO = Ð2.0 mA
0.2
0.4
volts
IO = +2.0 mA
mA
VOUT = VDD,
40
VDDÊ=Êmax
CIN
Input Capacitance
2
COUT
Output Capacitance
4
IOFS
Output Full Scale DAC Current
19.2
mA
VO
DAC Compliance Voltage
±0.96
Volts
10
pF
All inputs
pF
All outputs
(Differential)
RO
DAC Output Resistance
TBD
Ohms
CO
DAC Output Capacitance
TBD
VNO
DAC Output Noise Voltage Density
TBD
pF
nV
Hz
NOTES:
1.
With V SS = AVSS, Noise coupling from supply to the DAC output.
2.
Noise coupling to DAC output when noise is common to AVDD and AVSS with respect to VSS of VDD and VSS with respect to
AV SS.
3.
Specified for digital outputs. The DAC output can survive an indefinite short circuit to AVSS.
PRELIMINARY PRODUCT INFORMATION
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37
STEL-1109
RECOMMENDED INTERFACE CIRCUITS
SLAVE MODE INTERFACE
TSDATA
D
Q
CLKEN
D
Q
TSDATA
CLKEN
OR
DATAENO
DATAEN
D
Q
DATAEN
DIFFEN
D
Q
DIFFEN
FCWSEL 1-0
D
Q
2
STEL-1109
FCWSEL 1-0
TCLK
TCLK
WCP 52995.c-5/2/97
MASTER MODE INTERFACE
TSDATA
D
Q
D
Q
TSDATA
DATAEN
D
Q
D
Q
DATAEN
DIFFEN
D
Q
D
Q
DIFFEN
D
Q
TCLK
BITCLK
STEL-1109
CLKEN*
WCP 52115.c-5/2/96
* CLKEN may be turned off between bursts to conserve power as long as it is kept on until after
DATAENO goes low. Note that the BITCLK output goes inactive whenever CLKEN is low.
STEL-1109
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PRELIMINARY PRODUCT INFORMATION
EXAMPLE OUTPUT LOAD SCHEMATIC
0.1
Iout
Pin 52
T1-6TKK81
0.1
50Ω line Note 1
50Ω
load
50Ω
X
AVSS
0.1
Ioutn
Pin 53
MiniCircuits
1:1
50Ω
AVSS
WCP-52997.c-5/6/97
Note 1: Normally some application dependant alias filtering and
amplitude control appear at this point in the circuit.
MECHANICAL SPECIFICATIONS
The STEL-1109 is packaged as a single chip. The chipÕs package style, dimensions, and pin identification are shown
in Figure 16.
0.787"
±0.008"
0.913"
±0.008"
64
65
41
40
0.551"
± 0.008"
Top View
80
1
Detail of pins
0.677"
± 0.008"
0.01" max.
25
24
0.0315"
±0.008"
0.029"/
0.041"
0.012"/0.018"
Pin 1 Identifier
0.130" max.
Package style: 80-pin MQFP.
Thermal coefficient, θja = 58° C/W
WCP 52998.c-4/26/97
Note:
Tolerance on pin spacing is not cumulative
Figure 16. STEL-1109 Mechanical Characteristics
PRELIMINARY PRODUCT INFORMATION
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39
STEL-1109
Information in this document is provided in connection with
Intel® products. No license, express or implied, by estoppel
or otherwise, to any intellectual property rights is granted by
this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied
warranty, relating to sale and/or use of Intel® products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent,
copyright or other intellectual property right. Intel products
are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
For Further Information Call or Write
INTEL CORPORATION
Cable Network Operation
350 E. Plumeria Drive, San Jose, CA 95134
Customer Service Telephone: (408) 545-9700
Technical Support Telephone: (408) 545-9799
FAX: (408) 545-9888
WCP 970156
Copyright © Intel Corporation, December 15, 1999. All rights reserved
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