STLVDS9637 HIGH SPEED DIFFERENTIAL LINE RECEIVERS ■ ■ ■ ■ ■ ■ ■ ■ ■ MEETS OR EXCEEDS THE REQUIREMENTS OF ANSI TIA/EIA-644 STANDARD OPERATES WITH A SINGLE 3.3V SUPPLY DESIGNED FOR SIGNALING RATE UP TO 400Mbps DIFFERENTIAL INPUT THRESHOLDS ±100mV MAX TYPICAL PROPAGATION DELAY TIME OF 2.5ns POWER DISSIPATION 60mW TYPICAL PER RECEIVER AT 200MHz LOW VOLATGE TTL (LVTTL) LOGIC OUTPUT LEVELS OPEN CIRCUIT FAIL SAFE ESD PROTECTION: 7KV RECEIVER PINS 3KV ALL PINS VS GND DESCRIPTION The STLVDS9637, is a differential line receiver that implements the electrical characteristics of low voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5V differential standard levels (such as TIA/EIA-422B) to reduce the power, increase the switching speeds and allow operations with a 3.3V supply rail. This differential receiver provides a SOP valid logical output state with a 3.3V supply rail. It also provides a valid logical output state with a ±100mV differential input voltage within the input common mode voltage range. The input common mode voltage allows 1V of ground potential difference between two LVDS nodes. The intended application of this device and signalling technique is both point-to-point and multidrop data transmission over controlled impedance media approximately 100Ω. The transmission media may be printed circuit board traces, backplanes or cables. The ultimate rate and distance of data transfer depend upon the attenuation characteristics of the media and noise coupling to the environment. The STLVDS9637 version is characterized for operation from -40°C to 85°C. ORDERING CODES Type Temperature Range Package Comments STLVDS9637BD STLVDS9637BDR -40 to 85 °C -40 to 85 °C SO-8 (Tube) SO-8 (Tape & Reel) 100parts per tube / 40tube per box 2500 parts per reel September 2003 1/10 STLVDS9637 PIN CONFIGURATION PIN DESCRIPTION PlN N° SYMBOL 2, 3 5, 7 6, 8 4 1Y to 2Y 1B to 2B 1A to 2A GND VCC 1 NAME AND FUNCTION Receiver Outputs Negated Receiver Inputs Receiver Inputs Ground Supply Voltage LOGIC DIAGRAM AND LOGIC SYMBOL TRUTH TABLE DIFFERENTIAL INPUTS OUTPUT A, B Y VID ≥ 100mV H -100mV < VID < 100mV VID ≤ -100mV ? OPEN H L = Low level, H = High Level, X = Don’t care, Z = High Impedance, ? = Indeterminate 2/10 L STLVDS9637 ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Supply Voltage (Note 1) VI Input Voltage VI Input Voltage (A or B inputs) ESD Tstg Value Human Body Model Unit -0.5 to 4.6 V -0.5 to (VCC + 0.5) V -0.5 to 4.6 V 7 3 KV -65 to +150 °C Pins Receivers All Pins vs GND Storage Temperature Range Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. Note 1: All voltages except differential I/O bus voltage, are with respect to the network ground terminal. RECOMMENDED OPERATING CONDITIONS Symbol Min. Typ. Max. Unit VCC Supply Voltage Parameter 3.0 3.3 3.6 V VIH HIGH Level Input Voltage (ENABLE) 2.0 VIL LOW Level Input Voltage (ENABLE) |VID| Magnitude of Differential Input Voltage VIC Common Mode Input Voltage V 0.8 V 0.1 0.6 V 0.5|VID| 2.4-0.5|VID| V VCC - 0.8 TA Operating Temperature Range 85 -40 °C ELECTRICAL CHARACTERISTICS (Over recommended operating conditions unless otherwise noted. All typical values are at TA = 25°C, and VCC = 3.3V) Symbol Parameter VITH+ VOH Positive Going Differential Input Voltage Threshold Negative Going Differential Input Voltage Threshold High Level Output Voltage VOL Low Level Output Voltage IOH = 8mA ICC Supply Current No Load VITH- II Test Conditions IIH IIL IOZ Max. Unit 100 mV mV IOH = -8mA 2.4 V IOH = -4mA 2.8 0.4 V 4 10 mA -10 -20 µA 20 µA VIH = 2V 10 µA VIL = 0.8V 10 µA ± 10 µA Input Current (A or B inputs) VI = 0V Power off Input Current (A or B inputs) High Level Input Current (EN, G, G or Inputs) Low Level Input Current (EN, G, G or Inputs) High Impedance Output Current Typ. -100 -2 VI = 2.4V II(OFF) Min. VCC = 0 -1.2 VI = 3.6V VO = 0 or VCC -3 10 3/10 STLVDS9637 SWITCHING CHARACTERISTICS (Unless otherwise noted. Typical values are referred to TA = 25°C and VCC = 3.3V) Symbol tPLH tPHL tr tf tsk(O) tsk(P) tsk(PP) tPZH tPZL tPHZ tPLZ Parameter Test Conditions Propagation Delay Time, CL = 10pF Low to High Output Propagation Delay Time, High to Low Output Differential Output Signal Rise Time Differential Output Signal Fall Time Channel to Channel Output Skew (note1) Pulse Skew (|tPHL - tPLH|) (note2) Part to Part Skew (note3) Propagation Delay Time, High Impedance to High Level Output Propagation Delay Time, High Impedance to Low Level Output Propagation Delay Time, High Level to High Impedance Output Propagation Delay Time, Low Level to High Impedance Output Fig. 2 Fig. 1 Min. Typ. Max. Unit 1.5 2.5 3.3 ns 1.5 2.5 3.3 ns 0.4 ns 0.4 ns 0.1 0.3 ns 0.2 0.4 ns 1 ns 3 12 ns 5 12 ns 5 12 ns 5 12 ns Note 1: tsk(O) is the maximum delay time difference between the propagation delay of one channel and that of the others on the same chip with any event on the inputs. Note 2: tsk(P) is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. Note 3: tsk(PP) is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same VCC, and within 5°C of each other within the operating temperature range. 4/10 STLVDS9637 Figure 1 : Timing Test Circuit, Timing And Waveforms Note A: All input pulse are supplied by a generator having the following characteristics: tr or tf ≤ 1ns, pulse repetition rate (PRR) = 50Mpps, pulse width = 10 ± 0.2ns. Note B: CL includes instrumentation and fixture capacitance within 6mm of the D.U.T. 5/10 STLVDS9637 Figure 2 : Enable And Disable Time Test Circuit And Waveform Note A: All input pulse are supplied by a generator having the following characteristics: tr or tf ≤ 1ns, pulse repetition rate (PRR) = 50Mpps, pulse width = 500 ± 10ns. Note B: CL includes instrumentation and fixture capacitance within 6mm of the D.U.T. 6/10 STLVDS9637 TYPICAL PERFORMANCE CHARACTERISTICS (unless otherwise specified Tj = 25°C) Figure 3 : Output Current vs Output Voltage Figure 4 : Output Current vs Output Voltage 7/10 STLVDS9637 SO-8 MECHANICAL DATA DIM. mm. MIN. TYP inch MAX. MIN. TYP. MAX. A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.04 0.010 A2 1.10 1.65 0.043 0.065 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 3.80 4.00 0.150 0.157 e 1.27 0.050 H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 k ddd 8˚ (max.) 0.1 0.04 0016023/C 8/10 STLVDS9637 Tape & Reel SO-8 MECHANICAL DATA mm. inch DIM. MIN. A TYP MAX. MIN. 330 MAX. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 13.2 TYP. 0.504 22.4 0.519 0.882 Ao 8.1 8.5 0.319 0.335 Bo 5.5 5.9 0.216 0.232 Ko 2.1 2.3 0.082 0.090 Po 3.9 4.1 0.153 0.161 P 7.9 8.1 0.311 0.319 9/10 STLVDS9637 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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