TMPR4955AF-200 TOSHIBA RISC PROCESSOR TMPR4955AF-200 (TX4955A) (64-bit RISC MICROPROCESSOR) 1. GENERAL DESCRIPTION The TMPR4955AF is a 64-bit RISC (Reduced Instruction Set Computer) microprocessor that is a lowcost, low-power microprocessor developed for interactive consumer applications including set-top terminals, LBP(Laser Beam Printer), and video games. 2. FEATURES • • • • • • • • • • • • • • True 64-bit microprocessor, with TX49/H2 core. Optimized 5-stage pipeline 32-bit System Address/Data bus Single or double-precision Floating-Point Operation 32-bit physical address space and 64-bit virtual address space. 32-bit SysAD bus interface with R4000/R4400/R5000 or TX4300 compatible protcol On-chip 32-Kbyte Instruction Cache and 32-Kbyte Data Cache. Low power consumption 3.3 /1.5V Dual power supply (I/O:3.3V,Internal:1.5V) Reduced power mode (Halt) Data cache prefetching Memory management unit contains 48-double entry JTLB, 2-entry Instruction TLB, and 4-entry Data TLB Software compatibility with all MIPS processors MIPS I, II, and III Instruction Set Architecture (ISA) EJTAG (Enhanced JTAG) debug support Maximum operating frequency Internal:200MHz External:100MHz Package : 160-pin QFP •The information contained herein is subject to change without notice. •TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. • TMPR4955AF 2002-01-17 1/19 TMPR4955AF-200 3. SYSTEM CONFIGURATION 3.1 TMPR4955AF BLOCK DIAGRAM TMPR4955AF MasterClock Interrupt /Reset CG (PLL) Synchronizer TX49/H2 Core Integer Unit Floating-Point Coprocessor (CP1) CP0 Registers GPR Data Path System Control Coprocessor (CP0) CP1 Registers Pipeline Controller MMU w/ TLB Data Path JTAG Interface 32-bit SysAD Bus DSU (EJTAG) SysAD Interface MAC 32K Byte 4-way Set Instruction Cache Exception Unit Cache Controller 32K Byte 4-way Set Data Cache Write Buffer TMPR4955AF 2002-01-17 2/19 TMPR4955AF-200 3.2 BLOCK FUNCTION q TX49/H2 Core • True 64-bit microprocessor • 32, 64-bit integer general purpose registers • 32, 64-bit floating point general purpose registers • Optimized 5-stage pipeline • Instruction Set Upward compatible with MIPS I,MIPS II, MIPS III ISA MAC(Multiply and Accumulate) instructions PREF(Prefetch) instruction • On-chip 32-Kbyte Instruction Cache and 32-Kbyte Data Cache 4-way set associative and Lock function support Data Cache: Write-back and Write-through support • MMU 32-bit physical address space and 64-bit virtual address space 48-double-entry (even/odd) Joint TLB 2-entry Instruction TLB and 4-entry Data TLB • IEEE754 compatible single and double precision FPU • Debug Support Unit (DSU) with EJTAG support • Power management modes ( HALT/DOZE ) q SysAD BUS I/F • Bus protocol conversion It converts TMPR4955AF Internal GBus Read/Write request into outside SyAD Bus protocol. • Output buffer level selectable q Synchronizer • The external interrupt It takes contents of interrupt register and bitwise OR of external interrupt signal (INT(5:0)). q Clock Generator • Generates the internal operating clock of the TMPR4955AF from external crystal oscillator. q Debug Support Unit (DSU) • EJTAG function support Consists of an Enhanced JTAG (EJTAG) Module and a Debug Support Unit (DSU). It can be used to provide single-step execution and hardware break-points for debugging processor systems. EJTAG utilizes JTAG interface and extends the ability to access the inside register contents, host sytem peripherals, and system memory. TMPR4955AF 2002-01-17 3/19 TMPR4955AF-200 4. PIN DESCRIPTION 4.1 PIN OUT (160-pin QFP) 1 Vss 2 BufSel1 3 JTDO 4 JTDI 5 JTCK 6 JTMS 7 VccIO 8 Vss 9 SysAD4 10 SysAD5 11 VccInt 12 Vss 13 SysAD6 14 VccIO 15 Vss 16 SysAD7 17 SysAD8 18 VccInt 19 Vss 20 SysAD9 21 VccIO 22 Vss 23 SysAD10 24 SysAD11 25 VccInt 26 Vss 27 SysAD12 28 VccIO 29 Vss 30 SysAD13 31 SysAD14 32 VccInt 33 Vss 34 SysAD15 35 BufSel0 36 PCST3 37 PCST2 38 PCST1 39 PCST0 40 VccIO 41 Vss 42 TRST* 43 RdRdy* / (GND) 44 WrRdy* / (EOK*) 45 ValidIn* / (Evalid*) 46 ValidOut* / (Pvalid*) 47 Release* / (PMaster*) 48 VccIO 49 PLLReset* 50 VccInt 51 TintDis 52 Vss 53 SysCmd0 54 SysCmd1 55 SysCmd2 56 SysCmd3 57 SysCmd4 58 SysCmd5 / (GND) 59 VccIO 60 Vss 61 SysCmd6 / (GND) 62 SysCmd7 / (GND) 63 SysCmd8 / (GND) 64 SysCmdP / (GND) 65 VccInt 66 Vss 67 VccIO 68 HALT/DOZE 69 Int0* 70 Int1* 71 Int2* 72 Int3* 73 Int4* 74 Int5* 75 VccIO 76 Vss 77 TPC3 78 TPC2 79 TPC1 80 DCLK 81 VccInt 82 NMI* 83 ExtRqst* / (Ereq*) 84 Reset* 85 ColdReset* 86 VccIO 87 Endian 88 VccIO 89 Vss 90 SysAD16 91 VccInt 92 Vss 93 SysAD17 94 SysAD18 95 VccIO 96 Vss 97 SysAD19 98 VccInt 99 Vss 100 SysAD20 101 SysAD21 102 VccIO 103 Vss 104 SysAD22 105 VccInt 106 Vss 107 SysAD23 108 SysAD24 109 VccIO 110 Vss 111 SysAD25 112 VccInt 113 Vss 114 SysAD26 115 SysAD27 116 VccIO 117 MODE43* 118 DivMode1 119 DivMode0 120 Vss 121 SysAD28 122 SysAD29 123 VccInt 124 Vss 125 SysAD30 126 VccIO 127 Vss 128 SysAD31 129 SysADC2/ (GND) 130 VccInt 131 Vss 132 SysADC3/ (GND) 133 VccIO 134 Vss 135 SysADC0/ (GND) 136 VccInt 137 Vss 138 SysADC1/ (GND) 139 SysAD0 140 VccIO 141 Vss 142 SysAD1 143 SysAD2 144 VccInt 145 Vss 146 SysAD3 147 PCST8 148 PCST7 149 PCST6 150 PCST5 151 PCST4 152 VccIO 153 Vss 154 VccIO 155 VssPLL 156 PLLCAP 157 VccPLL 158 Vss 159 MasterClock 160 VccIO Note1: “ * “ means the signal is the low-active. Note2: MODE43* SysAD Bus protocol select. 0 : TX4300 protocol 1 : R5000 protocol Note3: At TX4300 protocol mode PReq* signal Is not support. TMPR4955AF 2002-01-17 4/19 TMPR4955AF-200 4.2 PIN FUNCTION The following is a list of interface, interrupt, and miscellaneous pins available on the TMPR4955AF. SYSTEM INTERFACE (When MODE43* = 1) PIN NAME I/O FUNCTION SysAD(31:0) I/O System address / data bus A 32-bit address and data bus for communication between the processor and an external agent. I/O System command / data identifier bus A 9-bit bus for command and data identifier transmission between the processor and an external agent. SysADC(3:0) I/O System command/data check bus A 4-bit bus containing parity check bits for the SysAD bus during data cycles. SysCmdP I/O Reserved for system command/data identifier bus parity For the TMPR4955AF this signal is unused on input and zero on output. SysCmd(8:0) I Valid input The external agent asserts ValidIn* when it is driving a valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus. ValidOut* O Valid output The processor asserts ValidOut* when it is driving a valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus. ExtRqst* I External request An external agent asserts ExtRqst* to request use of the System interface. Release* O Release interface Signals that the system interface needs to submit an external request. WrRdy* I Write Ready Signals that an external agent can now accept a processor write request. RdRdy* I Read Ready Signals that an external agent can now accept a processor read request. ValidIn* TMPR4955AF 2002-01-17 5/19 TMPR4955AF-200 SYSTEM INTERFACE (When MODE43* = 0) PIN NAME SysAD(31:0) SysCmd(4:0) I/O FUNCTION I/O System address / data bus A 32-bit address and data bus for communication between the processor and an external agent. I/O System command / data identifier bus A 9-bit bus for command and data identifier transmission between the processor and an external agent. SysCmd(8:5) / GND O Reserved Always output Low level signal. SysADC(3:0) / GND O Reserved Always output Low level signal. SysCmdP / GND O Reserved Always output Low level signal. ValidIn* / EValid* I Valid input The external agent asserts EValid* when it is driving a valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus. ValidOut* / PValid* O Valid output The processor asserts PValid* when it is driving a valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus. ExtRqst* / EReq* I External request An external agent asserts EReq* to request use of the System interface. Release* / O Processor master Show that the TMPR4955AF is the System bus master. I External OK Signals that an external agent can now accept a processor write request. I Reserved Always input Low level signal. This signal has the internal pull-down registor. PMaster* WrRdy* / EOK* RdRdy* / GND TMPR4955AF 2002-01-17 6/19 TMPR4955AF-200 CLOCK / CONTROL INTERFACE PIN NAME I/O FUNCTION I Master clock Master clock input that establishes the processor operating frequency. DivMode(1:0) I Set the operational frequency of the System interface DivMode(1:0) MasterClock Pclock 00 50.0MHz 200MHz (1:4) 01 80.0MHz 200MHz (1:2.5) 10 100.0MHz 200MHz (1:2) 11 66.7MHz 200MHz (1:3) TintDis I Timer-Interrupt disable input 0 enable Timer-Interrupt (can not use int5*) 1 disable Timer-Interrupt MasterClock HALT/DOZE PLLReset* Endian O HALT/DOZE mode output This signal indicates that the TMPR4955AF is in the HALT or DOZE mode when this signal is “H”. I PLL reset input A signal to halt the PLL oscillation of the TMPR4955AF built-in clock generator. 0 PLL is halt (no oscillation ) 1 PLL is enabled. I Endianess input Indicates the initial setting of the endian during a reset. 0 Little Endian 1 Big Endian INTERRUPT INTERFACE PIN NAME I/O FUNCTION Int(5:0)* I Interrupt Five general processor interrupts, bit-wise ORed with bits 5:0 of the interrupt register and visible as bits 15:10 of the Cause register. NMI* I Non-maskable interrupt Non-maskable interrupt, ORed with bit 6 of the interrupt register. TMPR4955AF 2002-01-17 7/19 TMPR4955AF-200 JTAG INTERFACE PIN NAME JTDI JTCK JTDO/TPC(0) I/O FUNCTION I JTAG data in put / Debug interrupt input Run-time mode : input serial data to data/instruction register of JTAG. Real-time mode : interrupt line to change the debug unit state from real time mode to Run-time mode. I JTAG clock input The processor receives a serial clock on JTCK. On the rising edge of JTCK, both JTDI and JTMS are sampled. O JTAG data output / PC Trace output Run-time mode : output serial data from data/instruction register of JTAG. Real-time mode : output non-sequential program. I JTAG command JTAG command signal, indicating the incoming serial data is command data. O Debug Clock A clock output for a real-time debug system. The timing of a serial monitor bus and PC trace interface signal are all defined by this debug clock DCLK. The operation clock of the TMPR4955AF is divided by 3 at the time of a serial monitor bus operation. PCST (8:0) O PC trace status Output PC trace status information and the mode of the serial monitor bus. TPC(3:1) O PC trace output Output a non-sequential program counter at DCLK. TRST* I JTMS DCLK Test Reset input A reset input for a real-time debug system. When TRST* is asserted, the debug support unit (DSU) is initialized. TMPR4955AF 2002-01-17 8/19 TMPR4955AF-200 INITIALIZATION INTERFACE PIN NAME Reset* ColdReset* MODE43* BufSel(1:0) PLLCAP I/O FUNCTION I Soft (Warm) Reset This signal must be asserted synchronously with MasterClock for a soft reset. I Cold reset This signal indicates to the processor that the +3.3V(I/O) and +1.5V(Internal) power supply is stable and the processor should initiate a cold reset sequence, resetting the PLL. I MODE43* SysAD Bus protocol select. 0 TX4300 protocol 1 R5000 protocol I Output buffer level Select BufSel( 1:0) Level 00 50% (4mA buffer) 01 Reserved 10 150% (12mA buffer) 11 100% (8mA buffer) I PLL connect to capacitor Non connection. OTHERS PIN NAME I/O FUNCTION VccPLL I Quiet V CC for PLL Quiet V CC for the internal phase locked loop. (1.5v) VssPLL I Quiet V SS for PLL Quiet V SS for the internal phase locked loop. VccIO I Vcc Power supply pin for IO.( 3.3v ) VccInt I Vcc Power supply pin for internal.(1.5v) VSS I Vss Ground pin TMPR4955AF 2002-01-17 9/19 TMPR4955AF-200 5. ELECTRICAL CHARACTERISTICS Note: “Be careful of static” , please see “From Incoming to Shipping” of General Safety Precautions and Usage Considerations. 5.1 ABSOLUTE MAXIMUM RATINGS TMPR4955AF-200 VSS = 0 V (GND) SYMBOL RATINGS UNIT Supply voltage ( for I/O) PARAMETER VccIOMax -0.5 to 3.9 V Supply voltage ( for internal ) VccIntMax -0.5 to 3.0 V VIN -0.5 to V CC + 0.3 V T STG -65 to +150 °C Input voltage (*1) (*2) Storage Temperature Note ) If LSI is used above the maximum ratings, permanent destruction of LSI can result. In addition, it is desirable to use LSI for normal operation under the recommended condition. If these conditions are exceeded, reliability of LSI may be adversely affected. (*1) VIN Min. = -1.5V for pulse width less than 10 ns. (*2) keep (VccIO + 0.3V) less than VccIOMax 5.2 RECOMMENDED OPERATING CONDITIONS TMPR4955AF- 200 VSS = 0 V (GND) PARAMETER SYMBOL CONDITIONS MIN. MAX. Unit Supply Voltage ( for I/O ) VccIO 3.1 3.5 V Supply Voltage ( for internal ) VccInt 1.4 1.6 V Operating Case Temperature TC 0 +70 °C Note : The recommended operating conditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. If the device is used under operating conditions other than the recommended operating conditions (supply voltage, operating temperature range, specified AC and DC values etc.), malfunction may occur. Thus, when designing products which include this device, ensure that the recommended operating conditions for the device are always adhered to. TMPR4955AF 2002-01-17 10/19 TMPR4955AF-200 5.3 DC CHARACTERISTICS TMPR4955AF-200 T C = 0°C to 70°C, VccInt = 1.5V ± 0.1V,VccIO = 3.3 V ± 0.2V PARAMETER SYM BOL CONDITIONS Output High Voltage VOH VccIO = 3.3V,Vss=0V IOH = -4 mA Output Low Voltage VOL VccIO = 3.3V,Vss=0V IOL = 4 mA MIN. TYP. MAX. 2.4 UNITS V 0.4 V Input High Voltage (*2) VIH 2.0 VccIO+ 0.3 V Input Low Voltage (*1,2) VIL -0.5 0.8 V 550 mA 150 mA 50 mA 60 mA ± 10 µA (*1) Operating Current 1 (Normal operation) ICCInt Operating Current 2 (HALT mode) ICCInt Operating Current 3 (MasterClock stopped) ICCInt Operating Current ICCIO Input Leakage Pull-up (*3) Pull-down (*4) ILI VccIO = 3.3V, VccInt = 1.5V, MasterClock=100MHz, PClock = 200MHz 350 VccIO = 3.3V, VccInt = 1.5V, MasterClock=100MHz, PClock = 0MHz VccIO = 3.3V, VccInt = 1.5V, MasterClock=0MHz, PClock = 0MHz VccIO = 3.3V, VccInt = 1.5 V, MasterClock=100MHz, PClock = 200MHz Load = 25pF 50 Except (*3)port Rinu 30 50 100 Kohm Rind 30 50 100 Kohm Output Leakage ILO ± 20 µA Input Capacitance C IN 10 pF Output Capacitance C OUT 10 pF (*1) (*2) (*3) (*4) VIL Min. = -1.5V for pulse width less than 10 ns. Except for MasterClock input Applies to Int(5:0)*,NMI*, RESET*,JTMS, JTCK, JTDI, TPC1 inputs with pull-up resistor Applies to TRST*,RdRdy*,TPC3,TPC2 inputs with pull-down resistor TMPR4955AF 2002-01-17 11/19 TMPR4955AF-200 5.4 AC CHARACTERISTICS 5.4.1 CLOCK TIMING TMPR4955AF-200 T C = 0°C to 70°C, VccInt = 1.5V ± 0.1V,VccIO = 3.3 V ± 0.2V PARAMETER SYMBOL MasterClock High MasterClock Low MasterClock Frequency (*1) CONDITIONS MIN. MAX. UNITS tMCH Transition 5 ns 3.0 ns tMCL Transition 5 ns 3.0 ns fMCK 20 100.0 MHz fPCK 50 200 MHz MasterClock Period tMCP 10 50 ns MasterClock Rise Time tMCR 2.0 ns MasterClock Fall Time tMCF 2.0 ns Internal Frequency Operation (*1) Operation of TMPR495AF is only guaranteed with the Phase Lock Loop enabled. (*2) All output timings assume a 25 pF capacitive load. Output timings should be derated where appropriate. 5.4.2 SYSTEM INTERFACE TMPR4955AF-200 T C = 0°C to 70°C, VccInt = 1.5V ± 0.1V,VccIO = 3.3 V ± 0.2V, BufSel=100% PARAMETER Data Output (*1,2,3) Data Setup (*3) Data Hold (*3) SYMBOL MIN. MAX. UNITS tDO 1.0 6.5 ns tDS 3.5 ns tDH 1.0 ns (*1) Timings are measured from 1.5V of the SClock to 1.5V of signal. (*2) Capacitive load for all output timings is 25 pF. (*3) Data Output, Data Setup and Data Hold apply to all logic signals driven out of or driven into the TMPR4955AF on the system interface. Clocks are specified separately. TMPR4955AF 2002-01-17 12/19 TMPR4955AF-200 5.5 TIMING DIAGRAMS 5.5.1 CLOCK TIMING tMCP MasterClock tMCL tMCH 0.8 *VccIO 0.2 *VccIO tMCR tMCF TMPR4955AF 2002-01-17 13/19 TMPR4955AF-200 5.5.2 PClock to SClock DIVISOR of 2 cycle 1 2 3 4 MasterClock PClock (Internal Signal) SClock (Internal Signal) SysAD Driven D D D D tDO SysAD Received D D D D tDS tDH TMPR4955AF 2002-01-17 14/19 TMPR4955AF-200 5.5.3 SYSTEM INTERFACE TIMING MasterClock SClock (Internal Signal) tDO SysAD SysCmd SysADC SysCmdP tDS Valid output tDO tDH Valid input tDO ValidOut*, Release* tDS ValidIn*, ExtRqst*, WrRdy*, RdRdy*, Int(5:0)*,NMI* tDH Valid input TMPR4955AF 2002-01-17 15/19 TMPR4955AF-200 5.5.4 COLD RESET TIMING MasterClock tDS tDH DivMode(1:0) tDS tDH More than 16 MasterClock cycles Reset* More than 64000 MasterClock ColdReset* 5.5.5 WARM RESET TIMING MasterClock tDS tDS tDH Reset* More than 16 MasterClock cycles ColdReset* TMPR4955AF 2002-01-17 16/19 TMPR4955AF-200 6. PACKAGE DIMENSION QFP160-P-2828-0.65A UNIT : mm TMPR4955AF 2002-01-17 17/19 TMPR4955AF-200 7. PLL Passive Components The Phase Locked Loop circuit requires several passive components for proper operation, which are connected to VccPLL, and VssPLL, as illustrated in Figure 1. In addition, the capacitors for PLLCAP (CP) can be connected to either VccPLL. Note that C2 and the Cp capacitors are only incorporated into the QFP package as surface-mounted chip capacitors. VccInt TX4955A R L VccPLL C1 C2 C3 PLLCAP (Reserved) VssPLL C1, C2, C3, R and L are Board R L Components which should be placed as close as possible to the processor. VSS Figure 1 PLL Recommended Circuit Reference Values: R = 5 Ω (*1) C1 = 1 nF (*1) C2 = 82 nF (*1) C3 = 10uF (*1) VccInt = 1.5 V ± 0.1 V Note *1 : Change to the suitable value on each board The inductors (L) can be used as alternatives to the resistors (R) to filter the power supply. It is essential to isolate the analog power and ground for the PLL circuit (VccPLL/VssPLL) from the regular power and ground (VccInt/Vss). TMPR4955AF 2002-01-17 18/19 TMPR4955AF-200 8. Differences Between the TMPR4955F and the TMPR4955AF Product Name TMPR4955F TMPR4955AF Power Supply: Core (incl. PLL) I/O 2.5V 3.3 V 1.5V 3.3 V Pin Assignment (No.2) and (No.35) VccIO VccIO BufSel1 BufSel0 1.0 Selectable from 0.5, 1.0 and 1.5 I/O Buffer (Ratio) Note: Drive BufSel (1:0) = Output Drive Ratio = Influenced Signals SysAD(31:0) SysCmd(8:0) SysADC(3:0) SysCmdP ValidOut* Release* HALTDOZE 11 100% I/O I/O I/O I/O I/O O O O 10 01 00 150% Reserved 50% 1 9. History 2000-9-29 2000-10-12 page-9 OTHERS of PIN FUNCTION VccPLL 2.5V -> 1.5V 2000-11-17 AC and DC specification PLL passive components 2002-1-17 Deleated 167MHz spec. TMPR4955AF 2002-01-17 19/19