ETC BT445KHF135

150 MHz Monolithic CMOS
Triple 256 x 8 RAMDAC 
Bt445
The Bt445 is designed specifically for high-performance, high-resolution color
graphics applications. The wide input pixel port and internal multiplexing
modes enable TTL- compatible interfacing to the frame buffer, while maintaining PLL-generated 150 MHz, or externally provided 150 MHz video data rates
required for high refresh rate, high-resolution color graphics.
The Bt445 supports PLL pixel clock generation, supporting a variety of frequencies using an M/N divisor scheme. This decreases system cost due to the
elimination of multiple crystal oscillators that are used to support a variety of
monitor and refresh rates. In addition, the Bt445 provides the serial VRAM
clock, video clock, and various multi-purpose system clocks.
Using a patented pixel port architecture, Flexport , the input pixel port can
be configured in an almost unlimited variety of pixel depths, multiplex modes,
and input port widths. For example, these modes include 1-, 2-, 4-, 8-, 12-, 16-,
and 24-bit/pixel pseudo color and true color with overlay and cursor palette support. The Bt445 runs 24-bit true color with cursor, overlay, and palette bypass
support at pixel rates for 1280 x 1024 monitors. The Bt445 is also Bt458 software compatible.
Other features include programmable setup and digital pixel outputs, as
required for active matrix TFT support or NTSC encoding.
Functional Block Diagram
GND
CLOCK
CLOCK*
VIDCLK*
SCLK*
VIDCLKI
LD/SCLKI
P(63–0)
BLANK*
VSYNC*
SYNC*/
HSYNC*
XTAL2
Pixel
Clock
PLL
Clock
MPX
R
E
G
I
S
T
E
R
Pixel
Unpackaging
Logic
MCLK20
VREF
FS ADJUST
MCLK25
CPUCLK
CPU
Clock
PLL
Pixel Load
Control
Logic
R
E
G
I
S
T
E
R
S(1,0)
XTAL1
RANGE
VAA
CPU Clock
Generator
COMP2
COMP
Red
Extract
Palette
Bypass
DAC
IOR
Green
Extract
3 x 256 x 8
Color
Palette
DAC
IOG
Blue
Extract
16 x 24
Overlay
DAC
IOB
Overlay
Extract
Expand,
Blink, and
Mask Logic
Digital
Output
Logic
Cursor
Extract
JTAG
TMS TCK TDI TDO
CE* R/W C(2–0)
Brooktree
®
Addr Reg
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
PLL Pixel Clock Generation (M/N/L)
Up to 64-Bit Input Pixel Port Width
150, and 135 MHz Operation
High-Resolution True-Color Support
2:1 to 64:1 Multiplexed Pixel Port
Bt458 Software Compatible
Programmable Pixel Format
Three 256 x 8 Color Palette RAMs
16 x 24 Overlay Palette
4 x 24 Cursor Palette
Digital Pixel Output Port
0 or 7.5 IRE Blanking
VRAM Shift Clock Generation
System Clock Generation
JTAG Support
160-Pin PQFP Package
Applications
•
•
•
•
•
•
High-Resolution Color Graphics
CAE/CAD/CAM
Image Processing
Instrumentation
Desktop Publishing
Color Flat-Panel Displays
Related Products
• Bt431
• Bt458
• Bt858
4 x 24
Cursor
Bypass
Extract
Bus Control
Distinguishing Features
R
G B
PCLK
PSYNC*
PBLANK*
PVSYNC*
PHSYNC*
OR(3–0)
OG(3–0)
OB(3–0)
D(7–0)
Brooktree Corporation • 9868 Scranton Road • San Diego, CA 92121-3707 • 619-452-7580
1-800-2-BT-APPS • FAX: 619-452-1249 • Internet: apps@brooktree.com • L445001 Rev. F
Ordering Information
Model Number
Speed (MHz)
Package
Ambient Temperature Range
Bt445KHF150
150
160-pin Plastic Quad Flatpack
0° to +70° C
Bt445KHF135
135
160-pin Plastic Quad Flatpack
0° to +70° C
Copyright  1993, 1995 Brooktree Corporation. All rights reserved.
Print date: February, 1996
Brooktree reserves the right to make changes to its products or specifications to improve performance, reliability, or
manufacturability. Information furnished by Brooktree Corporation is believed to be accurate and reliable. However, no
responsibility is assumed by Brooktree Corporation for its use; nor for any infringement of patents or other rights of third parties
which may result from its use. No license is granted by its implication or otherwise under any patent or patent rights of Brooktree
Corporation.
Brooktree Products are not designed or intended for use in life support appliances, devices, or systems where malfunction of a
Brooktree Product can reasonably be expected to result in personal injury or death. Brooktree customers using or selling Brooktree
Products for use in such applications do so at their own risk and agree to fully indemnify Brooktree for any damages resulting from
such improper use or sale.
Brooktree is a registered trademark of Brooktree Corporation. Product names or services listed in this publication are for
identification purposes only, and may be trademarks or registered trademarks of their respective companies.
Specifications are subject to change without notice.
PRINTED IN THE UNITED STATES OF AMERICA
TABLE OF CONTENTS
List Of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
List Of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii
Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
MPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Reading/Writing Color Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Frame Buffer Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Pixel Loading Using SCLK* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pixel Loading Using VIDCLK*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VIDCLK Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
15
17
17
Frame Buffer Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Systems Using VIDCLK* for Loading Pixel Data . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Color Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Pixel Port Start Position Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pixel Unpacking Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pixel Depth Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiplex Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Start Position/Pixel Depth/Multiplex Rate Restrictions . . . . . . . . . . . . . . . . . . . . . . .
21
21
22
22
22
Pixel Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Generation of Unspecified Pixel Data LSBs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Color Palette Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Blinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Pixel Output Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4-4-4 True-Color Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8-8-8 True-Color Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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Bt445
Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
JTAG Test Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Boundary Scan Testability Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Programming Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Command Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Command Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Red MSB Position. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Red Width Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Red Blink Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Red Display Enable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Green MSB Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Green Width Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Green Blink Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Green Display Enable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Blue MSB Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Blue Width Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Blue Blink Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Blue Display Enable Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Overlay MSB Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Overlay Width Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Overlay Blink Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Overlay Display Enable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Cursor MSB Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Cursor Width Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Cursor Blink Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Cursor Display Enable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Palette Bypass Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Palette Bypass Width Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Pixel Port Start Position Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Pixel Format Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Pixel Depth Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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Bt445
Pixel PLL Rate Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Pixel PLL Rate Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
VIDCLK* Cycle Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Pixel Load Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Digital Output Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
MPX Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Read Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Blink Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Signature Analysis Registers (SAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Signature Analysis Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Test Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
PC Board Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Power and Ground Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COMP Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Signal Interconnect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Output Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
55
55
56
56
57
57
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Test Features of the Bt445 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Signature Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Analog Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Initializing the Bt445 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Color Palette Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Pipeline Delay Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
PLL Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Crystal Frequency Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Ratio Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Frame Buffer Interface Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Externally Generated Pixel Clock with Externally Generated
VRAM Serial Shift Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL-Generated Pixel Clock with Externally Generated VRAM Shift Clock. . . . . . . .
Bt445-Generated VRAM Shift Clock, Externally Generated Pixel Clock . . . . . . . . .
The Bt445-Generated VRAM Shift Clock and PLL-Generated Pixel Clock . . . . . . .
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72
73
74
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Digital Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Interfacing to High-Resolution Flat-Panel Displays. . . . . . . . . . . . . . . . . . . . . . . . . . 76
Digital Output Connection in 8-8-8 True-Color Mode . . . . . . . . . . . . . . . . . . . . . . . . 77
Parametric Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
DC Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
160-pin Plastic Quad Flatpack (PQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
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Bt445
LIST OF FIGURES
List Of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Brooktree
®
Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PLL Clock Generation Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Oscillator Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Differential ECL Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Frame Buffer Clocking Interface, Using SCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Frame Buffer Interface Timing Diagram Using SCLKI . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Composite Video Output Waveform (SETUP = 7.5 IRE) . . . . . . . . . . . . . . . . . . . . . . . . . 18
Composite Video Output Waveform (SETUP = 0 IRE) . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Frame Buffer and Pixel Port Timing Diagram, Using VIDCLK* Output . . . . . . . . . . . . . . 20
Pixel Output Interface Modes Representative Timing Diagram. . . . . . . . . . . . . . . . . . . . 26
JTAG Boundry Scan Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
JTAG Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Representative Power/Ground Analog Area Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Typical Connection Diagram and Parts List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Signature Analysis Register Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Frame Buffer Interface, External Pixel Clock, and Serial Clock Generation . . . . . . . . . . 71
Frame Buffer Interface, with PLL Pixel Clock
and no Bt445-Provided Shift Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Frame Buffer Interface with Externally Generated Pixel Clock
and Bt445-Generated SCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Frame Buffer Interface for Bt445-Generated
VRAM Serial Clock and Pixel Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Typical Connection diagram for digital Output Port to
640 x 480 TFT Flat-Panel Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Interfacing the Bt445 with a 1024 x 768 TFT Active Matrix Flat Panel. . . . . . . . . . . . . . . 76
Interfacing the Bt445 to a Bt858 Video Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
MPU Read/Write Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Input Pixel Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Input Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Video Output Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Reset, CPU Clock, and VIDCLK* Output Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Pixel Output Port Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
vii
Bt445
LIST OF TABLES
List Of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
viii
Pin Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Address Register (ADDR) Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Video Output Truth Table (SETUP = 7.5 IRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Video Output Truth Table (SETUP = 0 IRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Expansion of Pixel Color Fields Less Than 8 Bits
to an 8-Bit Field (Five-Bit Pixel Color Field Example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
OE Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Test Register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Test Register 0 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Test Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Color Palette Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Sample Pixel Clock Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Recommended VCO Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
MPU Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Input Pixel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
VIDCLKI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
INPUT CLOCK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
System Clock Generation AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
PLL Clock Generation Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Digital Pixel Output Port AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Brooktree
®
CIRCUIT DESCRIPTION
Introduction
The Bt445 is a flexible 150 MHz RAMDAC, that provides multiple multiplex operating modes with multiple plane depth resolutions, while still maintaining Bt458
register compatibility.
Two Phase Lock Loops (PLLs) are provided to eliminate high-speed signals on
the PCB and expensive ECL crystal oscillators. The first PLL is programmable
([M/N]/L, where M is six bits, N is four bits, and the L value can be one, two, four,
or eight) and is used to generate the pixel clock frequency. The second PLL operates from the same crystal or oscillator input as the pixel PLL, and is not programmable. For example, it may be used to provide additional clock outputs for the
CPU system, SCSI, and Ethernet clocks.
The Bt445’s input pixel port can be software-configured to be any width from
two to 64 pins. This allows maximum versatility for frame buffer configuration.
For example, the Bt445 can support a frame buffer architecture having a 6:1 multiplexed 8-bit pseudo-color frame buffer (48 signals) with 2-bit overlay (12 signals). The input port width in this case may be set to 60 pins. A pixel display order
can be selected to start from the lower-numbered bits of the input pixel port (LSB
unpacking) or from the higher-numbered bits (i.e., the pixel port width, MSB unpacking).
The Bt445 also provides fully programmable multiplex rates (2:1 to 64:1, any
integer value) and fully programmable pixel widths (one to 32 bits per pixel, any
integer value). The only restrictions are that the pixel port start position, multiplex
rate, and pixel width be consistent. This means that the number of bits per pixel
multiplied by the multiplex rate must be less than or equal to the number of input
port bits configured.
After pixel serialization has occurred, the Bt445 allows full configurability for
source and width selection of the red, green, blue, overlay, cursor, and palette bypass fields of the source pixel. For example, in a 16-bit-wide pixel, the red field
may come from bits 4–0, green may come from bits 9–5, blue may come from bits
14–10, and palette bypass control may come from bit 15 of the pixel.
Brooktree
®
1
CIRCUIT DESCRIPTION
Introduction
Bt445
Pseudo-color modes are supported by sourcing the red, green, and blue fields
from the same bits in the source pixel. In fact, any field of an input pixel may appear in any order or be coincident or overlapped with other fields.
The color palette bypass bit controls the selection between color palette usage
or bypass. Users can use the lookup table for gamma correction or they can bypass
the LUT on a pixel-by-pixel basis. This allows users to customize features with
ASICs, while providing capabilities for cost-efficient high-resolution 1280 x 1024
true-color graphics. Color palette bypass is available in all pixel modes, allowing
numerous monochrome/gray-scale options on the Bt445.
The Bt445 also provides a digital pixel output port from the DAC inputs to support driving an active matrix TFT LCD or an NTSC encoder such as the Bt858.
The Bt445 provides a clock, and the red, green, and blue pixel data prior to the decoder of the DACs. In addition, the pipelined sync and blank outputs are provided
so that users can synchronize their timing to valid pixel data. Two modes of operation are provided: 4-4-4 true color where the high-order nibble of red, green, and
blue are provided, and an 8-8-8 true-color mode where all bits of red, green, and
blue are provided at a reduced pixel rate. When using the digital output port (i.e.,
output bits OR3–OR0, OG3–OG0, or OB3–OB0), the DAC output quality is not
guaranteed.
For battery-powered applications, various power-down modes are available. In
one mode, the RAM and DACs are turned off. The RAM retains data and may be
accessed for read or write operations by the MPU. Another mode powers down the
pixel clock, RAM, and DACs.
A video RAM shift clock (SCLK*) is provided by the Bt445, changing the cycle frequency in correspondence with the multiplex factor. This simplifies timing
requirements to develop external logic for VRAM timing generation. In addition,
the Bt445 provides another output clock (VIDCLK*) which should be used for the
generation of the CRT timing signals.
2
Brooktree
®
CIRCUIT DESCRIPTION
Bt445
Pin Information
Pin Information
Pin
Count
Pin Name
Description
1
BLANK*
Composite Blank control input (TTL-compatible). A logical zero drives the analog outputs to
the blanking level, as illustrated in Table 3 and Table 4. It is registered on the rising edge of
VIDCLK. When BLANK* is a logical zero, the pixel and overlay inputs are ignored.
1
SYNC*/HSYNC*
Composite Sync/Hsync control input (TTL-compatible). For proper operation, this signal
needs to be provided at all times with front and back porch. Depending on the state of the
Command Register 1 Bit 7, a logical zero on this input switches off an IRE current source
on the IOG output (see Figure 7 and Figure 8). SYNC*/HSYNC* does not override any
other control or data input, as shown in Table 3 and Table 4; therefore, it should be
asserted only during the blanking interval. It is registered on the rising edge of VIDCLKI.
1
VSYNC*
Separate Sync control input (TTL-compatible). This signal is registered with each rising
edge of VIDCLKI and is pipelined to the pixel data rate, then output with pixel timing to the
PVSYNC* output. This signal is not internally used by the Bt445.
1
VIDCLKI
Video Clock input (TTL-compatible). The rising edge of this input is used to load the SYNC*
and BLANK* control inputs. Also, if SCLK* is not used to control the VRAM frame buffer,
the signal driving the VIDCLKI input would also be connected to LD/SCLKI. This input is
usually driven with a system-buffered/skewed version of the VIDCLK* output.
1
LD/SCLKI
Load Serial Clock input (TTL-compatible). Pixel data are loaded on the rising edge of this
signal, except for the first rising edge, which occurs during blanking. This input is usually
driven with a system-buffered/skewed version of either the SCLK* output or VIDCLK*.
64
P(63–0)
Pixel Inputs Port (TTL-compatible). These inputs are used to specify, on a pixel basis,
which one of the 256 entries in the color palette RAM, 16 entries of the overlay palette, or
four entries of cursor palette is to be used to provide color information. Depending on the
pixel configuration, up to 64 consecutive pixels per load cycle are input through this port.
They are registered on the rising edge of LD/SCLKI. These inputs have internal pullup
resistors; therefore, unused pins do not require connection. However, if the system configuration allows, the unused pins should be connected to GND.
2
S(1, 0)
CPU Clock Rate Select Switch (TTL-compatible). These inputs are used to set the initial
CPU clock rate at reset time.
3
IOR, IOG, IOB
Red, Green, and Blue Video Current outputs. These high-impedance current sources are
capable of directly driving a doubly terminated 75 Ω coaxial cable (Figure 14).
1
SCLK*
VRAM Shift Clock output (TTL-compatible). The signal on this pin is equal to the selected
pixel clock divided by the MPX rate. This clock must be redriven through an inverting buffer
prior to the connection to the serial clock of the VRAMs.
1
VIDCLK*
Video Clock output (TTL-compatible). This output is a divided pixel as programmed in the
VIDCLK* Cycle Control register. This clock must be redriven through an inverting buffer
prior to the connection to the CRT timing generation logic.
Brooktree
®
3
CIRCUIT DESCRIPTION
Bt445
Pin Information
Pin
Count
4
Pin Name
Description
1
PCLK
Pixel Clock (TTL-compatible). This clock is used to synchronize the next stage with the digital outputs. It must be redriven through a noninverting buffer prior to the connection to the
next stage. This clock has a maximum output clock speed of 55 MHz driving a 20 pF load.
1
PSYNC*
Composite SYNC control output (TTL-compatible). This signal is synchronized with the
pixel outputs. These outputs must be redriven through a non-inverting buffer prior to the
connection to the next stage.
2
PHSYNC*,
PVSYNC*
Separate SYNC control outputs (TTL-compatible). These signals are synchronized with the
pixel outputs. These outputs must be redriven through a non-inverting buffer prior to the
connection to the next stage.
1
PBLANK*
Composite BLANK control output (TTL-compatible). This signal is synchronized with the
pixel outputs. These outputs must be redriven through a non-inverting buffer prior to the
connection to the next stage.
12
OR (3–0)
OG (3–0)
OB (3–0)
Digital Outputs (TTL-compatible). These low-drive outputs represent the four MSBs of the
red, green, and blue DAC decoder and can be used to drive an active matrix TFT. These
outputs must be redriven through a non-inverting buffer prior to the connection to the next
stage.
1
CPUCLK
CPU Clock (TTL-compatible). This clock is used to derive the CPU clock and is selectable
between 50, 40, 33, and 25 MHz (when using a 20 MHz crystal). This clock must be
redriven through a buffer prior to the connection to the next stage. This clock has a maximum output clock speed of 50 MHz driving a 10 pF load.
1
MCLK20
20 MHz Master Clock (TTL-compatible). This master clock generates a constant 20 MHz
clock when a 20 MHz crystal is used. This clock must be redriven through a buffer prior to
the connection to the next stage.
1
MCLK25
25 MHz Master Clock (TTL-compatible). This master clock generates a constant 25 MHz
clock when a 20 MHz crystal is used. This clock must be redriven through a buffer prior to
the connection to the next stage.
1
TMS
Test Mode Select (TTL-compatible). JTAG input pin whose transitions drive the JTAG state
machine through its sequences. When not performing JTAG operations, this pin should be
driven to a logic high.
1
TCK
Test Clock (TTL-compatible). Used to synchronize all JTAG test structures. Maximum clock
rate for this pin is 50 MHz. When not performing JTAG operations, this pin should be driven
to a logic high.
1
TDI
Test Data In (TTL-compatible). JTAG input pin used for loading instructions to the TAP controller or for loading test vector data for boundary scan operation. When not performing
JTAG operations, this pin should be driven to a logic high.
1
TDO
Test Data Out (TTL-compatible). JTAG output used for verifying test results of all JTAG
sampling operations. This output pin is active for certain JTAG sequences, and will be
three-stated at all other times. When not performing JTAG operations, this pin should be
left floating.
2
COMP, COMP2
Compensation pins. These pins provide compensation for the internal reference amplifier.
A 0.1 µF ceramic capacitor must be connected between these two pins (Figure 14).
Brooktree
®
CIRCUIT DESCRIPTION
Bt445
Pin Information
Pin
Count
1
Pin Name
FS ADJUST
Description
Full-scale adjust control. A resistor (RSET) connected between this pin and GND controls
the magnitude of the full-scale video signal (Figure 14). Note that the IRE relationships in
Figure 7 and Figure 8 are maintained, regardless of the full-scale output current.
The relationship between RSET and the full-scale output current on IOG is:
RSET (Ω) = K1 * VREF (V) / IOG (mA)
The full-scale output current on IOR and IOB for a given RSET is:
IOR, IOB (mA) = K2 * VREF (V) / RSET (Ω)
where K1 and K2 are defined as:
Setup
IOG
IOR, IOB
7.5 IRE
K1 = 11,294
K2 = 8,067
0 IRE
K1 = 10,684
K2 = 7,457
1
VREF
Voltage reference input. An external voltage reference circuit, such as the one shown in
Figure 14, must supply this input with a 1.235 V (typical) reference. The use of a resistor
network to generate the reference is not recommended, as any low-frequency power supply noise on VREF will be directly coupled onto the analog outputs. A 0.1 µF ceramic
capacitor must be used to decouple this input to VAA, as shown in Figure 14. The decoupling capacitor must be as close as possible to the device to keep lead lengths to an absolute minimum.
2
CLOCK,
CLOCK*
Clock inputs. These differential clock inputs are designed to be driven by ECL logic configured for single supply (+5 V) operation. The clock rate is typically the pixel clock rate of the
system.
1
XTAL1
Crystal input. This input is either connected to a crystal or driven by a CMOS oscillator. The
internal PLLs generate the pixel and CPU clocks using this input.
1
XTAL2
Crystal amplifier output. This output is connected to the second terminal of the crystal
when used.
1
CE*
Chip enable control input (TTL-compatible). This input must be a logical zero to enable
data to be written to or read from the device. During write operations, data is internally registered on the rising edge of CE*. Care should be taken to avoid glitches on this edge-triggered input.
1
R/W
Read/write control input (TTL compatible). To write data to the device, both CE* and R/W
must be a logical zero. To read data from the device, CE* must be a logical zero and R/W
must be a logical one. R/W is registered on the falling edge of CE*.
3
C(2–0)
Command control inputs (TTL compatible). C2, C1, and C0 specify the type of read or write
operation being performed, as illustrated in Table 2. They are registered with the falling
edge of CE*.
8
D(7–0)
Data bus (TTL compatible). Data are transferred into and out of the device over this 8-bit
bidirectional data bus. D0 is the least significant bit.
1
RANGE
Compensation for VCO. A 0.01 µF ceramic chip capacitor and a 4.7µF tantalum capacitor
must be connected between this pin and adjacent VAA pin 23 of the Bt445 (Figure 14).
Brooktree
®
5
CIRCUIT DESCRIPTION
Bt445
Pin Information
Pin
Count
Pin Name
Description
1
RESET*
Reset input (TTL compatible). When this signal is asserted, all the Command Register Bits
are set to be in a Bt458-compatible mode.
7
NC
No Connect. Reserved for future expansion. These pins should be left open.
19
VAA
Power. All VAA pins must be connected.
11
GND
Ground. All GND pins must be connected.
CPUCLK
HSY NC*/SY NC*
Figure 1. Pin Diagram
VAA
1
VAA
2
GND
3
NC
4
CE*
5
R/W
6
C1
8
C2
9
RESET*
10
S0
11
TCK
13
TDO
14
TDI
15
TMS
16
CLOCK*
18
GND
19
XTA L1
20
XTA L2
21
VAA
23
RA NGE
24
COMP2
25
COMP
26
IOB
28
VAA
29
GND
30
IOG
31
VAA
33
IOR
34
VAA
35
GND
36
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
P39
P40
P41
P42
P43
P44
P45
P46
P47
GND
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P60
P61
P62
P63
NC
OB0
OB1
GND
VAA
VAA
VAA
VAA
P13
P14
48
P38
121
122
P15
123
P16
124
P17
125
P18
P19
126
127
P20
128
P21
129
P22
130
P23
P24
131
132
P25
133
P26
135
P27
135
P28
P29
136
137
P30
138
P31
139
140
MCLK25
MCLK20
141
142
LD/SCLKI
143
V IDCLKI
144
145
BLA NK*
NC
146
147
V SY NC*
148
GND
149
D0
150
D1
D2
151
152
D3
153
D4
154
D5
155
47
40
P37
VAA
P36
39
46
VAA
45
38
P35
FSA DJ
44
37
P34
V REF
D6
32
43
GND
156
27
42
VAA
D7
22
P33
GND
157
17
41
CLOCK
158
12
P32
S1
6
7
VAA
C0
159
160
VAA
AA
AAA
AA
AAA
AAA
AAAAA
AAA
AAAAA
AAA
AAAAA
AAA
AAAAA
AAA
AAAAA
AAA
AAAAA
AAA
AAAA
AA
AA
A
AA
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
Bt445
AA
AA
AA
160 Pin Plastic
AA
AA
Quad
Flat Pack
AA
Top View
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
AAA
AA A
120
VAA
119
VAA
118
P12
117
P11
116
P10
115
P9
114
P8
113
P7
112
P6
111
P5
110
P4
109
P3
108
P2
107
P1
106
P0
105
NC
104
NC
103
NC
102
PHSY NC*
101
PV SY NC*
100
PSY NC*
99
PBLA NK*
98
SCLK*
97
V IDCLK*
96
PCLK
95
GND
94
OR3
93
OR2
92
OR1
91
OR0
90
OG3
89
OG2
88
OG1
87
OG0
86
OB3
85
OB2
84
NC
83
GND
82
VAA
81
VAA
Brooktree
®
CIRCUIT DESCRIPTION
Bt445
Pin Information
Table 1. Pin Labels
Pin #
Pin Name
u
Pin #
81
Pin Name
VAA
Pin #
121
Pin Name
VAA
2
VAA
42
P32
82
VAA
122
VAA
3
GND
43
P33
83
GND
123
P13
4
N/C
44
P34
84
N/C
124
P14
5
CE*
45
P35
85
OB2
125
P15
6
R/W
46
P36
86
OB3
126
P16
7
C0
47
P37
87
OG0
127
P17
8
C1
48
P38
88
OG1
128
P18
9
C2
49
P39
89
OG2
129
P19
10
RESET*
50
P40
90
OG3
130
P20
11
S0
51
P41
91
OR0
131
P21
12
S1
52
P42
92
OR1
132
P22
13
TCK
53
P43
93
OR2
133
P23
14
TDO
54
P44
94
OR3
134
P24
15
TDI
55
P45
95
GND
135
P25
16
TMS
56
P46
96
PCLK
136
P26
17
CLOCK
57
P47
97
VIDCLK*
137
P27
18
CLOCK*
58
GND
98
SCLK*
138
P28
19
GND
59
P48
99
PBLANK*
139
P29
20
XTAL1
60
P49
100
PSYNC*
140
P30
21
XTAL2
61
P50
101
PVSYNC*
141
P31
22
GND
62
P51
102
PHSYNC*
142
CPUCLK
23
VAA
63
P52
103
N/C
143
MCLK25
24
RANGE
64
P53
104
N/C
144
MCLK20
25
COMP2
65
P54
105
N/C
145
LD/SCLKI
26
COMP
66
P55
106
P0
146
VIDCLKI
27
VAA
67
P56
107
P1
147
HSYNC*/SYNC*
28
IOB
68
P57
108
P2
148
BLANK*
29
VAA
69
P58
109
P3
149
N/C
30
GND
70
P59
110
P4
150
VSYNC*
31
IOG
71
P60
111
P5
151
GND
32
GND
72
P61
112
P6
152
D0
33
VAA
73
P62
113
P7
153
D1
34
IOR
74
P63
114
P8
154
D2
35
VAA
75
N/C
115
P9
155
D3
36
GND
76
OB0
116
P10
156
D4
37
VREF
77
OB1
117
P11
157
D5
38
FSADJ
78
GND
118
P12
158
D6
39
VAA
79
VAA
119
VAA
159
D7
40
VAA
80
VAA
120
VAA
160
VAA
®
VAA
Pin #
1
Brooktree
41
Pin Name
VAA
7
CIRCUIT DESCRIPTION
MPU Interface
Bt445
MPU Interface
As illustrated in the functional block diagram, the Bt445 supports a standard MPU
bus interface, allowing the MPU to access the internal control registers and color
palettes. The dual-port color palette RAM, overlay palette, and cursor color registers allow color updating without contention with the display refresh process.
Table 2 illustrates how the C(2–0) control inputs work in conjunction with the
internal address register to specify which control register, color palette RAM entry,
overlay register, or cursor color register will be accessed by the MPU.
The reset pin presets the internal registers, defaulting all internal registers to be
compatible with the 4:1 multiplex configuration of the Bt458. Features such as alternate pixel depth modes and multiplex factors are available through the use of the
C(2) control pin, which provides access to the extra features.
The 8-bit address register, ADDR(7–0), is used to address the internal color and
control registers, eliminating the requirement for external address multiplexers.
ADDR(0) corresponds to D(0) and is the least significant bit.
Reading/Writing Color Data
To write color data the MPU loads the address register with the address of the color
palette RAM location, overlay palette, or cursor color register to be modified. The
MPU performs three successive write cycles (red, green, and blue), using C(2–0)
to select the color register. During the blue write cycle, the three bytes of color information are concatenated into a 24-bit word and written to the location specified
by the address register. The address register then increments to the next location,
which the MPU may modify by simply writing another sequence of red, green, and
blue data.
To read color data, the MPU loads the address register with the address of the
color palette RAM location or overlay register to be read. The MPU performs three
successive read cycles (red, green, and blue), using C(2–0) to select either the color
palette RAM, overlay palette, or cursor color registers. Following the blue read cycle, the address register increments to the next location, which the MPU may read
by simply reading another sequence of red, green, and blue data.
When accessing the color palette RAM, the address register resets to $00 after
a blue read or write cycle to location $FF. To keep track of the red, green, and blue
read/write cycles, the address register has two additional bits that count modulo
three. They are reset to zero when the MPU reads or writes to the address register.
The MPU does not have access to these bits. The other eight bits of ADDR(7–0)
are accessible to the MPU.
8
Brooktree
®
CIRCUIT DESCRIPTION
Bt445
Additional Information
Additional Information
Although the color and overlay palette RAMs and cursor color registers are dual
ported, if the pixel data are addressing the same palette entry being written to by
the MPU during the write cycle, it is possible for one or more of the pixels on the
display screen to be disturbed. A maximum of one pixel is disturbed if the write
data from the MPU are valid during the entire chip enable time.
The control registers can also be accessed through the address register in conjunction with the C(2–0) inputs, as shown in Table 2. All control registers may be
written to or read by the MPU at any time. The address register does not increment
following read or write cycles to the control registers, facilitating read-modify-write operations.
To prevent pixels from being disturbed during writes to the control registers, the
MPU data must be valid during the entire chip enable time, or the accesses should
be limited to blanking time. The setup times shown in the AC Characteristics section are the minimum required to internally capture the data.
Note that if an invalid address is loaded into the address register, data written to
the device will be ignored and invalid data will be read by the MPU. This is not recommended, as this may cause problems in Bt445 code-compatible products.
Brooktree
®
9
CIRCUIT DESCRIPTION
Additional Information
Bt445
Table 2. Address Register (ADDR) Operation (1 of 2)
ADDR(7-0)
C(2-0)
10
Reset Value
[Hex]
Addressed by MPU
0
0
0
$xx
Address Register
0
0
1
$00–$FF
Primary Color Palette RAM*
0
1
0
$00
$01
$02
$03
$04
$05
$06
$07
$08–$FF
3A
DX
FF
0
43
0
ID Register ($3A)
Revision Register ($DX)
Reserved
Reserved
Read Enable Register
Blink Enable Register
Command Register 0
Test Register 0
Reserved
0
1
1
$00–$0F
$10–$FF
Overlay Color Palette RAM (1)
Reserved
1
0
0
$xx
Reserved
1
0
1
$00
$01
$02
$03
$04–$07
07
08
FF
0
Red MSB Position
Red Width Control
Red Display Enable Control
Red Blink Enable Register
Reserved ($00)
$08
$09
$0A
$0B
$0C–$0F
07
08
FF
0
Green MSB Position
Green Width Control
Green Display Enable Control
Green Blink Enable Register
Reserved ($00)
$10
$11
$12
$13
$14–$17
07
08
FF
0
Blue MSB Position
Blue Width Control
Blue Display Enable Control
Blue Blink Enable Register
Reserved ($00)
$18
$19
$1A
$1B
$1C–1F
09
02
03
0
Overlay MSB Position
Overlay Width Control
Overlay Display Enable Control
Overlay Blink Enable Register
Reserved ($00)
Brooktree
®
CIRCUIT DESCRIPTION
Bt445
Additional Information
Table 2. Address Register (ADDR) Operation (2 of 2)
ADDR(7-0)
C(2-0)
1
1
1
1
0
1
Reset Value
[Hex]
Addressed by MPU
$20
$21
$22
$23
$24–$FF
0
02
03
0
Cursor MSB Position
Cursor Width Control
Cursor Display Enable Control
Cursor Blink Enable Register
Reserved ($00)
$00
$01
$02
$03
$04
$05
$06
$07
$08
$09
$0A
$0B
$0C
$0D
$0E
$0F
$10–$FF
0X
40
0
03
Test Register 1
Command Register 1
Digital Output Control Register
VIDCLK* Cycle Control Register
Reserved
Pixel PLL Rate Register 0
Pixel PLL Rate Register 1
PLL Control Register
Pixel Load Control Register
Pixel Port Start Position Register
Pixel Format Control Register
MPX Rate Register
Signature Analysis Registers (1)
Pixel Depth Control Register
Palette Bypass Position
Palette Bypass Width Control
Reserved ($00)
$00
$01
$02
$03
$04–$FF
19
04
X8
04
28
08
03
XX
0A
0
01
Cursor Color 0 (1)
Cursor Color 1 (1)
Cursor Color 2 (1)
Cursor Color 3 (1)
Reserved
Notes: (1). Requires modulo 3 loading/reading.
Brooktree
®
11
CIRCUIT DESCRIPTION
Bt445
Clock Generation
Clock Generation
The Bt445 has two PLLs for generating the pixel clock and three system clocks.
(See the PLL Clock Generation Block Diagram and Figure 2). The pixel clock is
fully programmable, able to generate over 500 unique pixel clock frequencies using a single crystal.
The advanced PLLs contain an internal loop filter to provide maximum noise
immunity and to reduce jitter. Except for the reference crystal or oscillator, no external components or adjustments are necessary.
The pixel clock generator uses an M over (L x N) scheme to provide precise frequencies. The M, N, and L values can be programmed through the command registers with a variety of values, which generally provide frequency granularity that
averages less than 1 MHz. M is a binary 6-bit value, N is a binary 4-bit value, and
L is selectable to be one, two, four, or eight. Serial clock and video clocks are generated from the derived pixel clock.
A second PLL generates a number of various clocks (MCLK20, MCLK25,
CPUCLK), which may be used for the CPU clock and other system clocks. Using
a 20 MHz crystal, constant 20 MHz and 25 MHz clocks are available for Ethernet
and SCSI clock generation, while the CPU clock output is selectable between 25,
33, 40, or 50 MHz. The reference crystal used must be an AT crystal, and operated
in the fundamental mode. An oscillator reference can also be used by capacitively
coupling the oscillator’s output to the XTAL1 input, as shown in Figure 3. For this
configuration, leave the XTAL2 pin disconnected as shown.
Both PLLs can be disabled separately to provide maximum flexibility in configuring the Bt445 to match the system requirements. In order to minimize noise,
all unused outputs should be disabled via the command registers. Additionally, in
order to provide minimal noise effects to the RAMDAC, all of the clock generated
outputs are low drive and must be redriven by a buffer before distribution.
With the assertion of RESET*, the video clock defaults into a mode whereby a
one-fourth pixel rate video clock is automatically generated. This rate is consistent
with the LD rate needed to use a Bt458 in 4:1 multiplex mode. The PLLs are also
initiated with RESET* to generate the system clocks.
As an alternative to using the PLL for pixel clock generation, the Bt445 is also
designed to accept differential clock signals (CLOCK and CLOCK* in Figure 4).
These clock inputs can be generated by ECL logic operating at +5 V. Note that the
CLOCK and CLOCK* inputs require termination resistors (220 Ω to GND) that
should be located as close to the driving source as possible. A 150 Ω chip resistor
near the RAMDAC pins is also needed to ensure proper termination. (See
Figure 4).
12
Brooktree
®
CIRCUIT DESCRIPTION
Bt445
Clock Generation
Figure 2. PLL Clock Generation Block Diagram
CLOCK
CLOCK*
MPX
SCLK*
Divider
SCLK*
VIDCLK*
Divider
Pixel
Clock PLL
M/NxL
Oscillator
or
Crystal
6–25 MHz
VIDCLK*
Internal
RAMDAC
Pixel Clock
XTAL1
XTAL2
Crystal
Amplifier
Select
x 5/2
CPU
Clock
PLL
x 5/3
x2
CPUCLK
MPX
x 5/4
MCLK25
MCLK20
x1
Figure 3. Oscillator Clock Interface
+5 V
Bt445
1000 pF
Oscillator
XTAL1
XTAL2
10 kΩ
CLOCK
CLOCK*
Brooktree
®
13
CIRCUIT DESCRIPTION
Clock Generation
Bt445
Figure 4. Differential ECL Clock Interface
Bt438
Bt445
CLOCK
CLOCK
220 Ω
150
CLOCK*
CLOCK*
220 Ω
VAA
0.1 µF
VREF
VREF
1 kΩ
LD/SCLKI
VIDCLKI
14
VIDCLK*
Brooktree
®
CIRCUIT DESCRIPTION
Bt445
Frame Buffer Clocking
Frame Buffer Clocking
Pixel data may be clocked into the Bt445 in one of two modes: with VIDCLK input
and output signals, or with the SCLK input and output signals.
Brooktree
Pixel Loading
Using SCLK*
System designs that interface VRAM frame buffer serial data directly to the Bt445
can use the SCLK* and LD/SCLKI signal pairs to load pixel data. In this mode, the
Bt445 facilitates the generation of the VRAM shift clock by providing VRAM serial shift clock, SCLK*. SCLK* should be used to clock the VRAM shift registers
that provide pixel data to the Bt445. The ratio of SCLK* to the pixel clock equals
the value set into the MPX rate register.
SCLK* is stopped (in a logical one state) during blanking to allow the system to
reload the VRAM serial shift registers. System implementations using “midline”
transfer may necessitate inserting a VRAM shift clock pulse during blanking time
to load the shift register tap address. The system may insert this additional clock
without incurring additional gate delays by using a NAND driver for generating
SCLK to the VRAMs. The unused input on the NAND driver may be used to insert
the additional SCLK to load the tap address. The SCLK* (active low time) pulse
width is nominally two pixel clock cycles; as a result, architectures using less than
4:1 multiplexing will not normally use the SCLK*, LD/SCLKI signals for pixel
loading. Also refer to the AC timing specifications for the maximum rates at which
the SCLK* may be operated.
The buffered version of SCLK*, referred to in this specification as SCLK, is returned to the Bt445 to be used to load the input pixel data. This allows for faster serial path operation, as the buffer delay does not add to the serial port delay in
determining the minimum SCLK cycle time at which the system may operate (refer to Figure 5 and Figure 6).
The VIDCLKI signal is still used to load the VSYNC*, HSYNC*/SYNC*, and
BLANK* signals. The VIDCLK rate is independent of the pixel depth; the VIDCLK rate is selected by the VIDCLK rate select register.
Pixel Loading
Using VIDCLK*
System architectures that preclude using the SCLK* signal for loading pixel data
may instead use the VIDCLK* signal to load pixel data. In this mode of operation,
the LD/SCLKI and VIDCLKI should be connected together.
In this mode, the VIDCLK rate select field should be written as the same value
as the MPX Rate Register. The SCLK* output is disabled (high-z) when the Bt445
is configured in this mode.
®
15
CIRCUIT DESCRIPTION
Frame Buffer Clocking
Bt445
Figure 5. Frame Buffer Clocking Interface, Using SCLK
RAS*
CAS*
DT*/OE*
SCLK
Memory
Data
Transfer
Control
Pixel Memory Array
74F1804
CRT Timing
Generator
LD/SCLKI
VIDCLKI
SYNC*/HSYNC*
BLANK*
XTAL
SCLK*
Bt445
VIDCLK*
20 MHz
Oscillator
‘1’
74F1804
Figure 6. Frame Buffer Interface Timing Diagram Using SCLKI
PCLK
VIDCLKI
BLANK
SCLK*
Non-Midline
Transfer
Mode
LD/SCLKI
Group 0
P(63–0)
Group 1
SCLK*
Midline
Transfer
Mode
LD/SCLKI
P(63–0)
Group 0
Group 1
Pixel Data Valid from
System-Inserted Shift Clock
16
Brooktree
®
CIRCUIT DESCRIPTION
Bt445
Frame Buffer Clocking
VIDCLK Generation
At reset time, the Bt445 is configured to load pixels using VIDCLK. The multiplex
rate is set to 4:1 (Bt458 compatible). When changing the VIDCLK* cycle rate, the
VIDCLK* output is guaranteed not to glitch when changing from one rate to another. During the transition, the minimum low or high pulse width will be at least
the low or high width of the faster of the old or new VIDCLK rate. For 2:1 VIDCLK* rate, the VIDCLK* output will have a 50/50 duty cycle; for 3:1 to 64:1 VIDCLK* rates, the VIDCLK* active (low) pulse width is two pixel clocks.
Video Generation
The VIDCLK* output is a free-running clock typically used for clocking the display timing generator. The period of VIDCLK* is independent of SCLK* and is
controlled by the MPU via the VIDCLK* rate register. VIDCLK may be the pixel
clock divided by any integer from 2 to 64. SYNC* and BLANK* information are
registered with each rising edge of VIDCLKI and inserted into the pipelined pixel
stream at the appropriate time.
When using SCLK* to clock pixels, SYNC* and BLANK* are registered by a
different clock from the pixel data; therefore, they do not correspond to the pixel
inputs that are present at the same time. The SYNC* and BLANK* inputs are used
to provide the RAMDAC with timing information.
When the Bt445 is configured to use VIDCLK for loading pixel data, SYNC*
and BLANK* correspond to the pixel data being loaded on the same clock edge.
Every clock cycle, the selected color information from the color palette RAMs
or overlay registers are presented to the D/A converters.
The SYNC* and BLANK* inputs, pipelined to maintain synchronization with
the pixel data, add appropriately weighted currents to the analog outputs, producing the specific output levels required for video applications, as illustrated in
Figure 7 and Figure 8.
The varying output current from each of the D/A converters produces a corresponding voltage level, which is used to drive the color CRT monitor. Note that
only the green output (IOG) may contain sync information. Table 3 and Table 4
detail how the SYNC* and BLANK* inputs modify the output levels.
The D/A converters on the Bt445 use a segmented architecture in which bit currents are routed to either the current output or GND by a sophisticated decoding
scheme. This architecture eliminates the need for precision component ratios and
greatly reduces the switching transients associated with turning current sources on
or off. Monotonicity and low glitch are guaranteed by using identical current
sources and current steering their outputs. An on-chip operational amplifier stabilizes the D/A converter’s full-scale output current against temperature and power
supply variations.
Brooktree
®
17
CIRCUIT DESCRIPTION
Frame Buffer Clocking
Bt445
Figure 7. Composite Video Output Waveform (SETUP = 7.5 IRE)
Red,Blue
mA
V
19.05
Green
mA
0.714 26.67
V
1.000
White Level
92.5 IRE
1.44
0.054
9.05
0.340
Black Level
7.5 IRE
0.00
0.000
7.62
Blank Level
0.286
40 IRE
0.00
Sync Level
0.000
Table 3. Video Output Truth Table (SETUP = 7.5 IRE)
Description
Sync
Iout (mA)
No Sync
Iout (mA)
SYNC
BLANK
DAC
Input Data
WHITE
DATA
DATA–SYNC
BLACK
BLACK–SYNC
BLANK
SYNC
26.67
data + 9.05
data + 1.44
9.05
1.44
7.62
0
19.05
data + 1.44
data + 1.44
1.44
1.44
0
0
1
1
0
1
0
1
0
1
1
1
1
1
0
0
$FF
data
data
$00
$00
$xx
$xx
Note:
18
Typical with RSET = 523 Ω, VREF = 1.235 V. Blank pedestal = 7.5 IRE.
Brooktree
®
CIRCUIT DESCRIPTION
Bt445
Frame Buffer Clocking
Figure 8. Composite Video Output Waveform (SETUP = 0 IRE)
Red,Blue
mA
V
18.06
Green
mA
0.698 26.67
V
1.00
White Level
100 IRE
Black Level
0.00
0.000
8.05
0.302
0.00
0.000
0.00
0.000
Blank Level
40 IRE
Sync Level
Table 4. Video Output Truth Table (SETUP = 0 IRE)
Description
Sync
Iout (mA)
No Sync
Iout (mA)
SYNC*
BLANK*
DAC
Input Data
WHITE
DATA
DATA–SYNC
BLACK
BLACK–SYNC
BLANK
SYNC
26.67
data + 8.05
data
8.05
0
8.05
0
18.60
data
data
0
0
0
0
1
1
0
1
0
1
0
1
1
1
1
1
0
0
$FF
data
data
$00
$00
$xx
$xx
Note:
Typical with RSET = 523 Ω, VREF = 1.235 V. Blank pedestal = 0 IRE.
Brooktree
®
19
CIRCUIT DESCRIPTION
Frame Buffer Interface
Bt445
Frame Buffer Interface
Systems Using VIDCLK*
for Loading Pixel Data
To enable pixel data to be transferred from the frame buffer at TTL data rates, the
Bt445 incorporates internal registers and multiplexers. As illustrated in Figure 9,
on the rising edge of LD/SCLKI and VIDCLKI, sync and blank information, color,
overlay, cursor, and palette bypass information are all registered. The number of
pixels supplied for each input cycle depends on the multiplex rate as determined by
the current mode. Note that with this configuration, the sync and blank timing will
be recognized only with load pixel rate resolution, set by the multiplex mode. Typically, the LD/SCLKI signal is generated from the inverted signal of the VIDCLK*
output of the Bt445.
Pixel port bits used as overlay inputs have pixel timing, facilitating the use of
additional bit planes in the frame buffer to control overlay selection on a pixel basis, or they may be controlled by external character or cursor generation logic.
LD/SCLKI may be phase shifted in any amount relative to CLOCK or VIDCLK*. As a result, the pixel and overlay data are registered on the rising edge of
LD/SCLKI, independent of the clock phase.
Internal logic maintains an internal LOAD signal, synchronous to CLOCK, and
is guaranteed to follow the LD/SCLKI signal by at least one but not more than 3
clock cycles. This LOAD signal transfers the registered pixel and overlay data into
a second set of registers, which are then internally multiplexed at the pixel clock
rate.
Figure 9. Frame Buffer and Pixel Port Timing Diagram, Using VIDCLK* Output
PCLK
VIDCLKI
LD/SCLKI
BLANK*
P(63–0)
20
Group 0
Group 1
Group 2
Group 3
Brooktree
®
CIRCUIT DESCRIPTION
Bt445
Color Selection
Color Selection
At each pixel port load cycle, two or more pixels consisting of color, overlay, cursor, and/or palette bypass information are processed by the multiplexing and unpacking logic, read masks, blink mask, and command registers. Through the use of
the control registers, individual bit planes may be enabled or disabled for display,
and/or blinked at one of four blink rates and duty cycles.
The color selection process may be broken down into the following steps:
1 Multiplex the input pixels from the pixel port load cycle to the pixel clock
rate using the appropriate pixel port start position, pixel unpacking mode,
and pixel multiplex mode.
2 Expand the resulting 1:1 pixel data to eight bits each of red, green, and
blue; four bits of overlay; two bits of cursor; and one bit of palette bypass
control. Pseudo-color modes will supply the same 8-bit result to each of
the red, green, and blue colors at this point.
3 Apply the appropriate read masks to the pixel data.
4 Apply the appropriate blink masks to the pixel data.
5 If the palette is bypassed apply the resulting pixel data directly to the
DAC inputs; otherwise, apply the pixel data to the addresses of each of
the respectively red, green, and blue color palettes. Use the results to
drive the DACs inputs.
Pixel Port Start
Position Selection
The Bt445’s pixel path architecture allows the configurability of the starting position for pixel unpacking. This provides the system designer with greater options to
tailor the Bt445 to the desired frame buffer organization. The starting position is
configured via the Pixel Port Start Position Register when MSB unpacked, and
may be specified to be any position from P(63) to P(0). When LSB is unpacked, the
start position is P(0).
One use could be in systems utilizing double frame buffer designs. For example,
in an MSB unpacking, 8-bit pixel, 4:1 multiplex configuration, frame buffer A
could be attached to input pixel port bits P(31–0) and frame buffer B could be attached to input pixel port bits P(63–32). Assuming the other registers have been
appropriately programmed, the Bt445 would allow switching between the frame
buffers by simply programming a $20 (for frame buffer A) or a $40 (for frame buffer B) into the Pixel Port Start Position Register.
Pixel Unpacking
Selection
The Bt445 supports pixel unpacking starting from either the low-order side of the
input pixel port (LSB unpacking) or the high-order side of the input pixel port
(MSB unpacking). The starting bit for the MSB unpacking direction is specified by
using the Pixel Port Start Position Register. For further information, see the Pixel
Port Start Position Register in the Internal Register section. Within each pixel, the
MSB is the highest numbered bit.
Brooktree
®
21
CIRCUIT DESCRIPTION
Pixel Processing
Bt445
Pixel Depth Selection
The Bt445 provides extremely flexible options for various pixel depths on a
frame-by-frame basis. The selection of the pixel depth is set via the Pixel Depth
Register. The pixel depth may be specified to be any size from one to 32 bits per
pixel. Not all bits of a pixel will necessarily be used. The pixel depth must be consistent with the pixel port start position and multiplex rate.
Multiplex Rate Selection
The Multiplex Rate is selectable independent from the pixel depth and pixel port
start position. Valid multiplex rates are 2:1 to 64:1 (any integer amount). Again, the
only restriction is that the multiplex rate must be consistent with the pixel depth
and pixel port start position. When using VIDCLKI to load pixels, the multiplex
rate should be programmed at the same rate as the VIDCLK* cycle rate.
Note that the 4:1 multiplex mode is not available for the standard 150 MHz
speed grade of the Bt445 device. It is available under the part number
PS044504-150. The 4:1 MUX mode is available for the standard 135 MHz Bt445
device.
Start Position/Pixel
Depth/Multiplex Rate
Restrictions
The Bt445 is specified to operate at the pixel depths, pixel port start positions, and
multiplex rates that satisfy the following relationship:
For MSB unpacking:
Start Position – (Pixel Depth × Multiplex Rate) ≥ 0
For LSB unpacking:
(Pixel Depth × Multiplex Rate) ≤ 64
Programming the Bt445 to configurations not consistent with this relationship
will yield unspecified results that will not be tested or guaranteed.
Pixel Processing
The pixel unpacking process, which uses the pixel port start position, pixel depth,
and multiplex rate, internally yields a serialized pixel stream. Each pixel in this serial stream may be up to 32 bits wide, as specified by the Pixel Depth Register. At
this point, the individual fields are extracted from each pixel. The fields extracted
are: Red, Green, Blue, Overlay, Cursor, and Palette Bypass Control. The red,
green, and blue fields may each be up to eight bits wide, the overlay field may be
up to four bits wide, and the palette bypass control may be one bit wide. The MSB
position and width of each of these fields within the pixel are independently specified by the corresponding source and width registers. The fields may overlap or be
noncontiguous. For example, for 8-bit pseudo-color mode, the red, green, and blue
position and width registers would specify the same field of the pixel.
22
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CIRCUIT DESCRIPTION
Generation of Unspecified Pixel Data LSBs
Bt445
Generation of Unspecified Pixel Data LSBs
When true-color source pixel data contains less than eight bits per color channel,
the data is expanded to eight bits by left justifying and adding the appropriate LSBs
to allow for full-scale and best-fit linearity over the DAC output range. This allows
the use of the same gamma correction table for the various pixel modes. Table 5 illustrates this effect by indicating the actual values applied to the red DAC input
when in the 16-bit-per-pixel 5-5-5 mode, with palette bypass.
Color Palette Bypass Mode
The color palette bypass control is used to control the access to the color palette
RAM by the pixel data. The overlay and cursor color palette are not affected; they
are always used if overlay or cursor data is present. Bypassing the color palette delivers what would have been the palette address directly to the DAC inputs.
Blinking
To ensure that a color change due to blinking does not occur during the active display time (i.e., in the middle of the screen), the Bt445 monitors the BLANK* input
to determine vertical retrace intervals. A vertical retrace interval is recognized by
determining the number of syncs per blanking time. The Bt445 assumes that a vertical retrace occurs whenever more than one sync occurs during a blank interval.
Systems that do not require separate sync for the digital output section may provide a composite sync input on the SYNC*/HSYNC* input pin; the VSYNC* input should be a logical one. The Bt445 generates composite PSYNC* by logically
ORing the SYNC*/HSYNC* input with the VSYNC* input.
The processed pixel data is then used to select which color palette entry or overlay register is to provide color information. Note that P0 is the LSB when addressing the color palette RAM.
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CIRCUIT
Blinking
DESCRIPTION
Bt445
Table 5. Expansion of Pixel Color Fields Less Than 8 Bits to an 8-Bit Field (Five-Bit Pixel Color Field Example)
5-Bit Input Pixel Field
Hex
Binary
High-Order Bits of Input
Pixel to be Low-Order
Appended
$00
$01
$02
$03
$04
$05
$06
$07
$08
$09
$0A
$0B
$0C
$0D
$0E
$0F
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
$1B
$1C
$1D
$1E
$1F
0 0000
0 0001
0 0010
0 0011
0 0100
0 0101
0 0110
0 0111
0 1000
0 1001
0 1010
0 1011
0 1100
0 1101
0 1110
0 1111
1 0000
1 0001
1 0010
1 0011
1 0100
1 0101
1 0110
1 0111
1 1000
1 1001
1 1010
1 1011
1 1100
1 1101
1 1110
1 1111
000
000
000
000
001
001
001
001
010
010
010
010
011
011
011
011
100
100
100
100
101
101
101
101
110
110
110
110
111
111
111
111
Resulting 8-Bit Expanded
Field
$00
$08
$10
$18
$21
$29
$31
$39
$42
$4A
$52
$5A
$63
$6B
$73
$7B
$84
$8C
$94
$9C
$A5
$AD
$B5
$BD
$C6
$CE
$D6
$DE
$E7
$EF
$F7
$FF
Note: If this effect is not desired, the read mask registers may be used to force the appended LSBs to zero, or you may
set the palette addressing mode in Command Register 1 to continuous.
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CIRCUIT DESCRIPTION
Bt445
Pixel Output Interface
Pixel Output Interface
The digital pixel output interface can be operated in either of two true-color
modes: 4-4-4 or 8-8-8. This interface also provides the pixel output clock (PCLK),
pipelined sync (PSYNC*) and pipelined blank (PBLANK*) outputs, and 12 bits of
data. The pixel output interface signals OR(3–0), OG(3–0), OB(3–0), and PCLK
are specified to run at a maximum pixel rate of 55 MHz when in 4-4-4 mode, or
27.5 MHz when in 8-8-8 mode (see Figure 10).
Note that the digital pixel outputs have low drive capability in order to minimize
on chip noise. To increase the drive capability of the digital pixel outputs, they
should be redriven with non-inverting buffers. Additionally, trace lengths to the
buffers should be as short as possible to minimize trace capacitances and help
maintain the AC integrity of the signals.
4-4-4 True-Color Mode
When operated in 4-4-4 true-color mode, the pixel output interface provides 12
bits of pixel data, (one pixel) on each rising or falling edge of the pixel clock output, where each group of 4 bits corresponds to the most significant nibble of the 3
bytes being provided at the red, green, and blue DAC inputs. OR(3–0) carries the
R(7–4), OG(3–0) carries G(7–4), and OB(3–0) carries B(7–4).
8-8-8 True-Color Mode
When operated in 8-8-8 true-color mode, the pixel output interface provides 24
bits of pixel data each PCLK cycle. Each edge of the pixel data carries 12 bits of
the pixel data, first the high-order nibbles of red, green, and blue are presented on
the rising edge of the pixel clock, then the low-order nibbles are presented on the
falling edge of the clock. Note that decreased horizontal spacial resolution is traded for increased color resolution.
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CIRCUIT DESCRIPTION
Reset Initialization
Bt445
Figure 10. Pixel Output Interface Modes Representative Timing Diagram.
PCLK
PBLANK*
Pixel 0
Pixel 1
Pixel 2
Pixel 3
Pixel 4
Pixel 5
OR(3–0)
R(7–4)
R(7–4)
R(7–4)
R(7–4)
R(7–4)
R(7–4)
OG(3–0)
G(7–4)
G(7–4)
G(7–4)
G(7–4)
G(7–4)
G(7–4)
OB(3–0)
B(7–4)
B(7–4)
B(7–4)
B(7–4)
B(7–4)
B(7–4)
Pixel 0
Pixel 1
4-4-4
True
Color
Mode
Pixel 2
PCLK
PBLANK*
OR(3–0)
R(7–4)
R(3–0)
R(7–4)
R(3–0)
R(7–4)
R(3–0)
OG(3–0)
G(7–4)
G(3–0)
G(7–4)
G(3–0)
G(7–4)
G(3–0)
OB(3–0)
B(7–4)
B(3–0)
B(7–4)
B(3–0)
B(7–4)
B(3–0)
8-8-8
True
Color
Mode
Reset Initialization
The S0 and S1 inputs are used at reset time to load the PLL Control Register with
the proper CPU output clock multiplex rate. This allows for immediate proper selection of the CPU clock rate. While RESET* is a logical zero, the S0 and S1 inputs flow through and are latched as RESET* rises. The CPU output clocks also
have no glitches during transitions as defined for VIDCLK rate transitions.
Power-Down Mode
The Bt445 incorporates a power-down capability, controlled by command bits
CR13 and CR14. While both command bits are a logical zero, the Bt445 functions
in the normal operating mode.
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CIRCUIT DESCRIPTION
Bt445
JTAG Test Registers
The command bits can be set so that the DACs and power to the RAM are turned
off. Note that the RAM still retains the data. The RAM may be read or written
through the MPU. The RAM automatically powers up during MPU read/write cycles and shuts down when the MPU access is completed. The DACs output no current, and the command registers may still be written to or read by the MPU. Note
that the output DACs require about 1 second to turn off (sleep mode) or turn on depending on the compensation capacitor.
In order to conserve power during TFT-only operation, the DACs can be turned
off, shunting valid pixel data to the TTL outputs. During this operation, the RAM
is still active, indexing pixel data to RGB values.
JTAG Test Registers
Boundary Scan
Testability Structures
Brooktree
®
The Bt445 incorporates special circuitry that allows it to be accessed with tests defined by the Joint Test Action Group (JTAG), and documented in IEEE 1149.1,
Standard Test Access Port and Boundary Scan Architecture. The Bt445 has dedicated pins which are used for these test purposes only.
JTAG uses boundary-scan cells placed at each digital pin, both inputs and outputs.
Figure 11 shows how all scan cells are interconnected into a Boundary-Scan
Register (BSR), which applies or captures test data used for functional verification
of the Bt445. JTAG is particularly useful for board testers using functional testing
methods.
Access to JTAG consists of four dedicated pins comprising the Test Access Port
(TAP). These pins are Test Mode Select (TMS), Test Clock (TCK), Test Data Input
(TDI), Test Data Out (TDO). Connection verification of the Bt445 can be achieved
through these four TAP pins. Internal power-on reset (POR) circuitry ensures that
the Bt445 initializes each pin to its normal RAMDAC configuration during power
up. With boundary-scan cells at each digital pin, the Bt445 is able to apply and capture the logic level. Since all of the digital pins are interconnected as a long shift
register, the TAP logic has access and control of all the necessary pins to verify
board connections. The TAP controller can shift in any number of test vectors
through the TDI input and apply them to the internal circuitry. The output result is
scanned out on the TDO pin and externally checked. While isolating the Bt445
from the other components on the board, the user has easy access to all Bt445 digital pins through the TAP and can perform complete interconnect testing without
using expensive bed-of -nails testers.
The bidirectional MPU port and other digital I/Os require extra attention with
respect to JTAG. Because JTAG requires full control over each digital pin, additional Output Enable (OE) cells are included in the BSR for the MPU I/O port
(OEMPU) and various digital I/Os. When loaded by the JTAG instructions, these
OE cells control the directionality of their respective pins, and are listed in Table 6.
27
CIRCUIT DESCRIPTION
Device Identification Register
Bt445
With the JTAG bus, users also have access to an internal block of the Bt445, the
Signature Analysis Register (SAR). With access to this register, users can easily
verify expected video data serially through the JTAG port. The SAR is located between the lookup table and the inputs to the DACs.
Table 6. OE Register Description
Register
Outputs
OEMPU
D0–7
OEVIDTIM
PHSYNC*, PVSYNC*
OEPSYNC
PSYNC*
OEPBLANK
PBLANK*
OESCLK
SCLK*
OEVIDCLK
VIDCLK*
OEPCLK
PCLK
OEDIGOUT
OR0–3, OG0–3, OB0–3
OECMCLK
CPUCLK, MCLK20, MCLK25
Device Identification Register
The Bt445 does not incorporate the Device Identification Register defined in sections 7.10 and 7.11 of IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE Std 1149.1–1990). The Device Identification and Revision Numbers
can only read through the MPU Port.
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CIRCUIT DESCRIPTION
Bt445
JTAG Instructions
JTAG Instructions
The Bt445 has five usable JTAG instructions. The instruction register is four bits
wide and is shown in Table 7.
Table 7. JTAG Instructions
Code (1)
Data
Register
EXTEST
0
BSR
Scan In And Apply To Outputs
INTEST
1
BSR
Scan In And Apply To Inputs
SAMPLE
2
BSR
Capture Levels in BSR, Scan Out
Reserved
3
Reserved
4
SCNOSR
23
Reserved
6
BYPASS
7–F
Name
Note:
Brooktree
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23
BYR
Description
Scan Out SAR
TDI to TDO, Disable JTAG
The JTAG instruction register of the Bt445 is 4 bits wide, and is loaded
MSB first NOT LSB first.
29
CIRCUIT DESCRIPTION
JTAG Instructions
Bt445
Figure 11. JTAG Boundry Scan Registers
TDI
P50
S1
OECMCLK
P8
S0
P31
P7
OR0
P49
RESET*
P30
P6
OG3
P48
C2
P29
P5
OG2
P47
C1
P28
P4
OG1
P46
C0
P27
P3
OG0
P45
R/W
P26
P2
OB3
P44
CE*
P25
P1
OB2
P43
OEMPU
P24
P0
OEDIGOUT
P42
D7
P23
OEVIDTIM
OB1
P41
D6
P22
PHSYNC*
OB0
P40
D5
P21
PVSYNC*
P63
P39
D4
P20
OEPSYNC
P62
P38
D3
P19
PSYNC*
P61
P37
D2
P18
OEPBLANK
P60
P36
D1
P17
PBLANK
P59
P35
D0
P16
OESCLK
P58
P35
VSYNC
P15
SCLK*
P57
P34
HSYNC
P14
OEVIDCLK
P56
P33
VLCKI
P13
VIDCLK*
P55
P32
SCLKI
P12
OEPCLK
P54
CLOCK*
MCLK20
P11
PCLK
P53
CLOCK
MCLK25
P10
OR3
P52
CPUCLK
P9
OR2
P51
OR1
TDO
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CIRCUIT DESCRIPTION
Bt445
JTAG Instructions
Figure 12. JTAG Block Diagram
OE
Boundary Scan Register
OE
OE
Bt445
OE
Signature
Analysis
Register
P.O.R.
OE
JTAG
Controller
OE
I/O
Brooktree
®
I/O
I/O
13
14
15
16
TCK
TDO
TDI
TMS
31
INTERNAL REGISTERS
Programming Notes
The following are important programming notes regarding future code compatibility:
•
Internal reserved address locations should not be accessed.
•
To ensure compatibility with future Bt445 code-compatible devices, reserved values for fields should never
be written.
•
To ensure compatibility with future Bt445 code-compatible devices, reserved bits should be maintained
with read-modify-writes, which only update the unreserved bits. Furthermore, when testing the contents of
internal registers, reserved fields should be ANDed off prior to making comparisons. Although it should not
be assumed that these reserved bits will always return zeros when read, the reset values will always be as
shown.
•
It is recommended that the lower two bits of overlay blink-and-read mask values be read and/or written from
the extended register space (i.e., Command Register 1 bit 2=1 (continuous)). Although functionally equivalent to accesses from the Bt458-compatible address space, new code will be easier to modify for future
Bt445 code-compatible devices if these accesses are made in the extended register space.
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33
INTERNAL REGISTERS
Bt445
Command Register 0
Command Register 0
The command register may be written to or read by the MPU at any time. Bit 0 corresponds to data bus bit D0.
Bit(s)
34
Field Name
Reset
Value
Field Description
7
Reserved (logical zero)
0
In the Bt458, this bit specifies 4:1 multiplex mode. In the
Bt445, this bit is ignored. To configure the Bt445 for
Bt458-compatible 5:1, the extended Bt445 register set must
be used.
6
Overlay color 0 disable
(0)
Use overlay color 0
(1)
Use color palette RAM
1
When the overlay select bits are 0000, this bit specifies
whether to use the color palette RAM or overlay color 0 to
provide color information.
5,4
Blink rate selection
(00)
Moderate (25%/75%)
(01)
Fast (50%/50%)
(10)
Moderate (50%/50%)
(11)
Slow (50%/50%)
00
These two bits control the blink rate and duty cycle. The percentages specify the duty cycle (% masked/% displayed).
3
Overlay Plane 1 blink enable
(0)
Disable blinking
(1)
Enable blinking
0
If a logical one, this bit forces the overlay bit 1 inputs, if any,
to toggle between a logical zero and the input value at the
selected blink rate prior to selecting the palettes. A value of
logical zero does not affect the value of the overlay bit 1
inputs. This bit is also mapped into the Overlay Blink Enable
Register bit 1.
2
Overlay Plane 0 blink enable
(0)
Disable blinking
(1)
Enable blinking
0
If a logical one, this bit forces the overlay bit 0 inputs to toggle between a logical zero and the input value at the selected
blink rate prior to selecting the palettes. A value of logical
zero does not affect the value of the overlay bit 0 inputs. This
bit is also mapped into the Overlay Blink Enable Register bit
0.
1
Overlay plane 1 display enable
(0)
Disable
(1)
Enable
1
If a logical zero, this bit forces the overlay plane 1 inputs, if
any, to a logical zero prior to selecting the palettes. A value of
a logical one does not affect the value of the overlay plane 1
input. This bit is also mapped into the Overlay Display
Enable Register bit 1.
0
Overlay plane 0 display enable
(0)
Disable
(1)
Enable
1
If a logical zero, this bit forces the overlay plane 0 inputs, if
any, to a logical zero prior to selecting the palettes. A value of
a logical one does not affect the value of the overlay plane 0
input. This bit is also mapped into the Overlay Display
Enable Register bit 0.
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INTERNAL REGISTERS
Bt445
Command Register 1
Command Register 1
The command register may be written to or read by the MPU at any time. Bit 0 corresponds to data bus bit D0.
Bit(s)
Field Name
Reset
Value
Field Description
7
Green sync enable
(0)
Disable sync on IOG
(1)
Enable sync on IOG
0
This bit enables or disables sync information from being generated on the IOG output.
6
Pedestal Enable
(0)
0 IRE
(1)
7.5 IRE
1
This bit specifies whether a 0 or 7.5 IRE blanking pedestal is to
be generated on the video outputs. A 0 specifies that the black
and blank levels are the same.
5
Reserved
0
Reserved for future expansion.
Power Down Enable
(00)
Normal Operation
(01)
DACs off
(10)
DACs and RAM off
(11)
Disable Internal Clocking
00
While these bits are 00, the device operates normally. With the
DACs off, standard operation occurs but the output of the LUT
is routed directly to the TTL outputs. If these register bits are
set with the power to the DACs and RAM turned off, functional
operation is discontinued. In both power-down modes, the
RAM still retains the data, and CPU reads and writes can occur
with no loss of data. While the device is in the disable internal
clocking mode, the internal clock and other output clock modes
are completely disabled to further conserve power when in
power-down mode. The RAM still retains the data and MPU
reads and writes can occur with no loss of data.
2
Palette Addressing Mode
(0)
Sparse
(1)
Contiguous
0
This bit controls the field expansion mode. When this bit is a
logical zero, pixel fields containing fewer than the normal width
of the field will be expanded by left justifying the specified bits
and using group replication onto the unspecified lower bits.
When this bit is a logical one, the specified bits will be right justified with zeros placed onto the unspecified MSBs.
1
Signature Analysis Enable
(0)
Disable SAR
(1)
Enable SAR
0
This bit enables operation of all Signature Analysis Register
(SAR) clocking. A logical zero is the normal mode, the SAR disabled. Writing a logical one enables the SAR for operation on
every pixel. As slightly more power is consumed when the SAR
is enabled, it is recommended that the SAR be disabled when
not actually being used.
0
Reset Pipelined Depth
0
Transitioning this bit from a logical zero to a logical one causes
the pixel pipeline depth to be initialized. For further information,
see “Pipeline Delay Initialization” in the Applications section.
4,3
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INTERNAL REGISTERS
Bt445
Red MSB Position
Red MSB Position
Bit(s)
7–0
Field Name
MSB Position
($00)–Pixel Bit 0
($01)–Pixel Bit 1
:
($1F)–Pixel Bit 31
($20)–Reserved
:
($FF)–Reserved
Reset
Value
$07
Field Description
Position of the MSB of the red field within the input pixel. This field,
in conjunction with the size, determines which bits of the input pixel
are used to access the red color palette or red DAC output. The
value specified should be less than the pixel size.
Red Width Control
Bit(s)
7–0
Field Name
Size
($00)–Reserved
($01)–1 Bit
($02)–2 Bits
:
($08)–8 Bits
($09)–Reserved
:
($FF)–Reserved
Reset
Value
$08
Field Description
Number of bits to be used for the red field in a pixel. The size and
position of the red field must lie within the defined pixel size.
Red Blink Enable Register
Bit(s)
7–0
36
Field Name
Blink Enable
Reset
Value
$00
Field Description
Bits 7–0, corresponding to the expanded (i.e., either right justified
and zero padded, or left justified and MSB replicated) pixel planes
7–0, respectively, enable blinking of individual planes. A logical one
in any bit position causes the corresponding pixel plane to be
turned off in accordance with the blink rate counter and duty cycle.
A logical zero causes the corresponding pixel plane to be unaffected by the blink logic. The register is also written with MPU data
whenever the Bt458-compatible blink register is written.
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INTERNAL REGISTERS
Red Display Enable Control
Bt445
Red Display Enable Control
This register is also written when the Bt458-compatible read mask register is written.
Bit(s)
Field Name
Reset
Value
Field Description
7
Enable Bit Plane 7
(0)
Disable
(1)
Enable
1
This bit controls the enabling of red bit plane 7. A logical zero
causes bit 7 of the red field of the pixel to be forced to zero. A logical one causes bit 7 of the red field to pass to the color palette or
DAC.
6
Enable Bit Plane 6
(0)
Disable
(1)
Enable
1
This bit controls the enabling of red bit plane 6. A logical zero
causes bit 6 of the red field of the pixel to be forced to zero. A logical one causes bit 6 of the red field to pass to the color palette or
DAC.
5
Enable Bit Plane 5
(0)
Disable
(1)
Enable
1
This bit controls the enabling of red bit plane 5. A logical zero
causes bit 5 of the red field of the pixel to be forced to zero. A logical one causes bit 5 of the red field to pass to the color palette or
DAC.
4
Enable Bit Plane 4
(0)
Disable
(1)
Enable
1
This bit controls the enabling of red bit plane 4. A logical zero
causes bit 4 of the red field of the pixel to be forced to zero. A logical one causes bit 4 of the red field to pass to the color palette or
DAC.
3
Enable Bit Plane 3
(0)
Disable
(1)
Enable
1
This bit controls the enabling of red bit plane 3. A logical zero
causes bit 3 of the red field of the pixel to be forced to zero. A logical one causes bit 3 of the red field to pass to the color palette or
DAC.
2
Enable Bit Plane 2
(0)
Disable
(1)
Enable
1
This bit controls the enabling of red bit plane 2. A logical zero
causes bit 2 of the red field of the pixel to be forced to zero. A logical one causes bit 2 of the red field to pass to the color palette or
DAC.
1
Enable Bit Plane 1
(0)
Disable
(1)
Enable
1
This bit controls the enabling of red bit plane 1. A logical zero
causes bit 1 of the red field of the pixel to be forced to zero. A logical one causes bit 1 of the red field to pass to the color palette or
DAC.
0
Enable Bit Plane 0
(0)
Disable
(1)
Enable
1
This bit controls the enabling of red bit plane 0. A logical zero
causes bit 0 of the red field of the pixel to be forced to zero. A logical one causes bit 0 of the red field to pass to the color palette or
DAC.
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37
INTERNAL REGISTERS
Bt445
Green MSB Position
Green MSB Position
Bit(s)
7–0
Field Name
MSB Position
($00)–Pixel Bit 0
($01)–Pixel Bit 1
:
($1F)–Pixel Bit 31
($20)–Reserved
:
($FF)–Reserved
Reset
Value
$07
Field Description
Position of the MSB of the green field within the input pixel. This
field, in conjunction with the size, determines which bits of the
input pixel are used to access the green color palette or green
DAC output. The value specified should be less than the pixel
size.
Green Width Control
Bit(s)
7–0
Field Name
Size
($00)–Reserved
($01)–1 Bit
($02)–2 Bits
:
($08)–8 Bits
($09)–Reserved
:
($FF)–Reserved
Reset
Value
$08
Field Description
Number of bits to be used for the green field in a pixel. The size
and position of the green field must lie within the defined pixel size.
Green Blink Enable Register
Bit(s)
7–0
38
Field Name
Green Blink Enable
Reset
Value
$00
Field Description
Bits 7–0, corresponding to the expanded (i.e., either right justified
and zero padded, or left justified and MSB replicated) green pixel
planes 7–0, respectively, enable blinking of individual planes. A
logical one in any bit position causes the corresponding pixel plane
to be turned off in accordance with the blink rate counter and duty
cycle. A logical zero causes the corresponding pixel plane to be
unaffected by the blink logic. The register is also written with MPU
data whenever the Bt458-compatible blink register is written.
Brooktree
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INTERNAL REGISTERS
Green Display Enable Control
Bt445
Green Display Enable Control
This register is also written mapped to the Bt458-compatible read mask.
Bit(s)
Field Name
Reset
Value
Field Description
7
Enable Bit Plane 7
(0)
Disable
(1)
Enable
1
This bit controls the enabling of green bit plane 7. A logical zero
causes bit 7 of the green field of the pixel to be forced to zero. A
logical one causes bit 7 of the green field to pass to the color palette or DAC.
6
Enable Bit Plane 6
(0)
Disable
(1)
Enable
1
This bit controls the enabling of green bit plane 6. A logical zero
causes bit 6 of the green field of the pixel to be forced to zero. A
logical one causes bit 6 of the green field to pass to the color palette or DAC.
5
Enable Bit Plane 5
(0)
Disable
(1)
Enable
1
This bit controls the enabling of green bit plane 5. A logical zero
causes bit 5 of the green field of the pixel to be forced to zero. A
logical one causes bit 5 of the green field to pass to the color palette or DAC.
4
Enable Bit Plane 4
(0)
Disable
(1)
Enable
1
This bit controls the enabling of green bit plane 4. A logical zero
causes bit 4 of the green field of the pixel to be forced to zero. A
logical one causes bit 4 of the green field to pass to the color palette or DAC.
3
Enable Bit Plane 3
(0)
Disable
(1)
Enable
1
This bit controls the enabling of green bit plane 3. A logical zero
causes bit 3 of the green field of the pixel to be forced to zero. A
logical one causes bit 3 of the green field to pass to the color palette or DAC.
2
Enable Bit Plane 2
(0)
Disable
(1)
Enable
1
This bit controls the enabling of green bit plane 2. A logical zero
causes bit 2 of the green field of the pixel to be forced to zero. A
logical one causes bit 2 of the green field to pass to the color palette or DAC.
1
Enable Bit Plane 1
(0)
Disable
(1)
Enable
1
This bit controls the enabling of green bit plane 1. A logical zero
causes bit 1 of the green field of the pixel to be forced to zero. A
logical one causes bit 1 of the green field to pass to the color palette or DAC.
0
Enable Bit Plane 0
(0)
Disable
(1)
Enable
1
This bit controls the enabling of green bit plane 0. A logical zero
causes bit 0 of the green field of the pixel to be forced to zero. A
logical one causes bit 0 of the green field to pass to the color palette or DAC.
Blue MSB Position
Brooktree
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39
INTERNAL REGISTERS
Bt445
Blue Width Control
Bit(s)
7–0
Field Name
MSB Position
($00)–Pixel Bit 0
($01)–Pixel Bit 1
:
($1F)–Pixel Bit 31
($20)–Reserved
:
($FF)–Reserved
Reset
Value
$07
Field Description
Position of the MSB of the blue field within the input pixel. This
field, in conjunction with the size, determines which bits of the input
pixel are used to access the blue color palette or blue DAC output.
The value specified should be less than the pixel size.
Blue Width Control
Bit(s)
7–0
Field Name
Size
($00)–Reserved
($01)–1 Bit
($02)–2 Bits
:
($08)–8 Bits
($09)–Reserved
:
($FF)–Reserved
Reset
Value
$08
Field Description
Number of bits to be used for the blue field in a pixel. The size and
position of the blue field must lie within the defined pixel size.
Blue Blink Enable Register
Bit(s)
7–0
Field Name
Blue Blink Enable
Reset
Value
$00
Field Description
Bits 7–0, corresponding to the expanded (i.e., either right justified
and zero padded, or left justified and MSB replicated) blue pixel
planes 7–0, respectively, enable blinking of individual planes. A
logical one in any bit position causes the corresponding pixel plane
to be turned off in accordance with the blink rate counter and duty
cycle. A logical zero causes the corresponding pixel plane to be
unaffected by the blink logic. The register is also written with MPU
data whenever the Bt458-compatible blink register is written.
Blue Display Enable Control
40
Brooktree
®
INTERNAL REGISTERS
Overlay MSB Position
Bt445
This register is also written when the Bt458-compatible read mask register is written.
Bit(s)
Field Name
Reset
Value
Field Description
7
Enable Bit Plane 7
(0)
Disable
(1)
Enable
1
This bit controls the enabling of blue bit plane 7. A logical zero
causes bit 7 of the blue field of the pixel to be forced to zero. A logical one causes bit 7 of the blue field to pass to the color palette or
DAC.
6
Enable Bit Plane 6
(0)
Disable
(1)
Enable
1
This bit controls the enabling of blue bit plane 6. A logical zero
causes bit 6 of the blue field of the pixel to be forced to zero. A logical one causes bit 6 of the blue field to pass to the color palette or
DAC.
5
Enable Bit Plane 5
(0)
Disable
(1)
Enable
1
This bit controls the enabling of blue bit plane 5. A logical zero
causes bit 5 of the blue field of the pixel to be forced to zero. A logical one causes bit 5 of the blue field to pass to the color palette or
DAC.
4
Enable Bit Plane 4
(0)
Disable
(1)
Enable
1
This bit controls the enabling of blue bit plane 4. A logical zero
causes bit 4 of the blue field of the pixel to be forced to zero. A logical one causes bit 4 of the blue field to pass to the color palette or
DAC.
3
Enable Bit Plane 3
(0)
Disable
(1)
Enable
1
This bit controls the enabling of blue bit plane 3. A logical zero
causes bit 3 of the blue field of the pixel to be forced to zero. A logical one causes bit 3 of the blue field to pass to the color palette or
DAC.
2
Enable Bit Plane 2
(0)
Disable
(1)
Enable
1
This bit controls the enabling of blue bit plane 2. A logical zero
causes bit 2 of the blue field of the pixel to be forced to zero. A logical one causes bit 2 of the blue field to pass to the color palette or
DAC.
1
Enable Bit Plane 1
(0)
Disable
(1)
Enable
1
This bit controls the enabling of blue bit plane 1. A logical zero
causes bit 1 of the blue field of the pixel to be forced to zero. A logical one causes bit 1 of the blue field to pass to the color palette or
DAC.
0
Enable Bit Plane 0
(0)
Disable
(1)
Enable
1
This bit controls the enabling of blue bit plane 0. A logical zero
causes bit 0 of the blue field of the pixel to be forced to zero. A logical one causes bit 0 of the blue field to pass to the color palette or
DAC.
Overlay MSB Position
Brooktree
®
41
INTERNAL REGISTERS
Overlay Width Control
Field Name
Bit(s)
7–0
MSB Position
($00)–Pixel Bit 0
($01)–Pixel Bit 1
:
($1F)–Pixel Bit 31
($20)–Reserved
:
($FF)–Reserved
Bt445
Reset
Value
$09
Field Description
Position of the MSB of the overlay field within the input pixel. This
field, in conjunction with the size, determines which bits of the input
pixel are used to access the overlay palette or all DAC outputs. The
value specified should be less than the pixel size.
Overlay Width Control
Bit(s)
7–0
Field Name
Size
($00)–Reserved
($01)–1 Bit
($02)–2 Bits
($03)–3 Bits
($04)–4 Bits
($05)–Reserved
:
($FF)–Reserved
Reset
Value
$02
Field Description
Number of bits to be used for the overlay field in a pixel. The size
and position of the overlay field must lie within the defined pixel
size.
Overlay Blink Enable Register
Bit(s)
Field Name
Reset
Value
Field Description
7–4
Reserved
$0
Reserved for future expansion.
3–0
Overlay Blink Enable
$0
Bits 3–0, corresponding to the expanded (i.e., either right justified
and zero padded, or left justified and MSB replicated) overlay pixel
planes 3–0, respectively, enable blinking of individual planes. A
logical one in any bit position causes the corresponding pixel plane
to be turned off in accordance with the blink rate counter and duty
cycle. A logical zero causes the corresponding pixel plane to be
unaffected by the blink logic. Bits 0 and 1 of this field are also read
and written by accessing the Bt458-compatible overlay blink controls in Command Register 0.
42
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INTERNAL REGISTERS
Overlay Display Enable Control
Bt445
Overlay Display Enable Control
Bits 1 and 0 of this register are also mapped to the Bt458-compatible command register 0 bits 1 and 0.
Bit(s)
7–4
Field Name
Reset
Value
Field Description
Reserved
0
Reserved for future expansion.
3
Enable Bit Plane 3
(0)
Disable
(1)
Enable
0
This bit controls the enabling of overlay bit plane 3. A logical zero
causes bit 3 of the overlay field of the pixel to be forced to zero. A
logical one causes bit 3 of the overlay field to pass to the overlay
palette.
2
Enable Bit Plane 2
(0)
Disable
(1)
Enable
0
This bit controls the enabling of overlay bit plane 2. A logical zero
causes bit 2 of the overlay field of the pixel to be forced to zero. A
logical one causes bit 2 of the overlay field to pass to the overlay
palette.
1
Enable Bit Plane 1
(0)
Disable
(1)
Enable
1
This bit controls the enabling of overlay bit plane 1. A logical zero
causes bit 1 of the overlay field of the pixel to be forced to zero. A
logical one causes bit 1 of the overlay field to pass to the overlay
palette.
0
Enable Bit Plane 0
(0)
Disable
(1)
Enable
1
This bit controls the enabling of overlay bit plane 0. A logical zero
causes bit 0 of the overlay field of the pixel to be forced to zero. A
logical one causes bit 0 of the overlay field to pass to the overlay
palette.
Cursor MSB Position
Bit(s)
7–0
Field Name
MSB Position
($00)–Pixel Bit 0
($01)–Pixel Bit 1
:
($1F)–Pixel Bit 31
($20)–Reserved
:
($FF)–Reserved
Reset
Value
$00
Field Description
Position of the MSB of the cursor field within the input pixel. This
field, in conjunction with the size, determines which bits of the input
pixel are used to access the cursor palette or all DAC inputs. The
value specified should be less than the pixel size.
Cursor Width Control
Brooktree
®
43
INTERNAL REGISTERS
Cursor Blink Register
Field Name
Bit(s)
7–0
Size
($00)–Reserved
($01)–1 Bit
($02)–2 Bits
($03)–Reserved
:
($FF)–Reserved
Bt445
Reset
Value
$02
Field Description
Number of bits to be used for the cursor field in a pixel. The size
and position of the cursor field must lie within the defined pixel size.
Cursor Blink Register
Bit(s)
Field Name
7–2
Reserved
1, 0
Cursor Blink Enable
Reset
Value
000000
00
Field Description
Reserved for future expansion.
Bits 1 and 0, corresponding to the expanded (i.e., either right justified and zero padded, or left justified and MSB replicated) cursor
pixel planes 1 and 0, respectively, enable blinking of individual
planes. A logical one in any bit position causes the corresponding
pixel plane to be turned off in accordance with the blink rate
counter and duty cycle. A logical zero causes the corresponding
pixel plane to be unaffected by the blink logic.
Cursor Display Enable Control
Bit(s)
7–2
44
Field Name
Reserved
Reset
Value
0000000
Field Description
Reserved for future expansion.
1
Enable Bit Plane 1
(0)
Disable
(1)
Enable
1
This bit controls the enabling of cursor bit plane 1. A logical zero
causes bit 1 of the cursor field of the pixel to be forced to zero. A
logical one causes bit 1 of the cursor field to pass to the cursor
palette.
0
Enable Bit Plane 0
(0)
Disable
(1)
Enable
1
This bit controls the enabling of cursor bit plane 0. A logical zero
causes bit 0 of the cursor field of the pixel to be forced to zero. A
logical one causes bit 0 of the cursor field to pass to the cursor
palette.
Brooktree
®
INTERNAL REGISTERS
Palette Bypass Position
Bt445
Palette Bypass Position
Field Name
Bit(s)
7–0
LSB Position
($00)–Pixel Bit 0
($01)–Pixel Bit 1
:
($1F)–Pixel Bit 31
($20)–Reserved
:
($FF)–Reserved
Reset
Value
$00
Field Description
Position of the LSB of the palette bypass field within the input pixel.
This field, in conjunction with the size, determines which bits of the
input pixel are used to control palette bypass. The value specified
should be less than the pixel size.
Palette Bypass Width Control
Bit(s)
7–0
Field Name
Size
($00)–Reserved
($01)–1 Bit
($02)–Reserved
:
($FF)–Reserved
Reset
Value
$01
Field Description
Number of bits to be used for the palette bypass field in a pixel. The
size and position of the palette bypass field must lie within the
defined pixel size.
Pixel Port Start Position Register
The command register may be written to or read by the MPU at any time. Bit 0 corresponds to data bus bit D0.
Bit(s)
7–0
Field Name
Pixel Port Start Position
($00) Bit 0
($01) Bit 1
:
($3F) Bit 63
($40) Bit 64
($41) Reserved
:
($FF) Reserved
Brooktree
®
Reset
Value
$28
Field Description
When MSB unpacked, this register should be loaded with the MSB
+ 1 of the pixel input bits to be used. When LSB unpacked, the register value is ignored. However, it is recommended to write 0 to this
register for future compatibility. For example, if MSB unpacking is
desired using bits 31–0 of the input pixel port, then this register
should be loaded with $20. This register selects the starting bit
position for the pixel unpacking logic.
45
INTERNAL REGISTERS
Pixel Format Control Register
Bt445
Pixel Format Control Register
The command register may be written to or read by the MPU at any time. Bit 0 corresponds to data bus bit D0.
Bit(s)
Field Name
Reset
Value
Field Description
7
Pixel Unpacking Order
(0)
MSB Unpacking
(1)
LSB Unpacking
0
This bit selects the pixel unpacking ordering. When pixels are MSB
unpacked, the first pixel output will come from the higher-order bits
of the input pixel port. When LSB unpacked, the first pixel output
will come from the lower-order bits of the input pixel port.
6
Reserved
0
Reserved for future expansion.
5
Cursor Enable
(0)
Disable
(1)
Enable
0
This bit enables the input pixel cursor field to select the cursor palette. When this bit is a logical zero, the input pixel cursor field is
ignored.
4
Cursor Color 0 Enable
(0)
Disable
(1)
Enable
0
This bit enables the use of cursor color 0. When this bit is a logical
zero, a cursor field value of zero causes the cursor to be transparent. When this bit is a logical one, a cursor field value of zero
causes cursor color 0 to be used.
3
Overlay Enable
(0)
Disable
(1)
Enable
1
This bit enables the input pixel overlay field to select the overlay
palette. When this bit is a logical zero, the input pixel overlay field is
ignored.
2
Reserved
0
Reserved for future expansion.
Palette Bypass Control
(00)
Always use Color
Palette
(01)
Always bypass Color
Palette
(10)
Use input pixel field
(11)
Reserved
00
This field specifies how the pixel data should address the color palette, or bypass it. If the color palette is used, a pixel will address
the color palettes, and its contents would then be used as the
inputs to the DACs or to drive the pixel output port. Cursor and
overlays always use the color palette.
1, 0
Pixel Depth Control Register
The command register may be written to or read by the MPU at any time. Bit 0 corresponds to data bus bit D0.
46
Brooktree
®
INTERNAL REGISTERS
Pixel PLL Rate Register 0
Bt445
Bit(s)
7–0
Field Name
Pixel Depth Select
($00) Reserved
($01) 1 Bit/Pixel
($02) 2 Bits/Pixel
($03) 3 Bits/Pixel
:
($1E) 30 Bits/Pixel
($1F) 31 Bits/Pixel
($20) 32 Bits/Pixel
($21) Reserved
:
($FF) Reserved
Reset
Value
$0A
Field Description
These bits select the pixel depth. The total number of bits per pixel,
including overlay, cursor, and unused bits in each pixel, must be
specified. The reset value is consistent with the Bt458 (10 bits per
pixel, 8 pseudo color plus 2 overlay).
Pixel PLL Rate Register 0
The command register may be written to or read by the MPU at any time. Bit 0 corresponds to data bus bit D0.
Bit(s)
Field Name
Reset
Value
7, 6
Reserved (logical zero)
00
5–0
Multiplier Selection (M)
($00) Reserved
:
($17) Reserved
($18) Multiply by 24
($19) Multiply by 25
:
($3E) Multiply by 62
($3F) Multiply by 63
011001
Field Description
Reserved.
Determines the multiplier factor for the input oscillator frequency
(M) used in determining the final pixel clock frequency.
Pixel PLL Rate Register 1
The command register may be written to or read by the MPU at any time. Bit 0 corresponds to data bus bit D0.
Brooktree
®
47
INTERNAL REGISTERS
Bt445
PLL Control Register
Bit(s)
Field Name
Reset
Value
Field Description
7, 6
Pixel Clock Divider (L)
(00)
Divide by 1
(01)
Divide by 2
(10)
Divide by 4
(11)
Divide by 8
00
This bit controls the Pixel PLL divider L.
5,4
Reserved
00
Reserved.
3–0
Pixel Clock Divisor Selection (N)
(0000) Reserved
(0001) Reserved
:
(0011) Divide by 4
(0100) Divide by 5
:
(1110) Divide by 15
(1111) Reserved
0100
Determines the divisor factor for the input oscillator frequency (N)
used in determining the final pixel clock frequency.
PLL Control Register
The command register may be written to or read by the MPU at any time. Bit 0 corresponds to data bus bit D0.
48
Brooktree
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INTERNAL REGISTERS
VIDCLK* Cycle Control Register
Bt445
Bit(s)
Field Name
Reset
Value
Field Description
7
Pixel Clock PLL Enable
(0)
PLL Disable
(1)
PLL Enable
1
This bit determines whether the PLL used to generate the pixel
clock should be enabled or disabled. Should the PLL be disabled, the pixel clock must be input via CLOCK and CLOCK*.
6
MCLK Enable
(0)
MCLKs Disabled
(1)
MCLKs Enabled
1
This bit disables the PLL used to synthesize the master clock
which eventually generates the CPU clock, 20 MHz and 25 MHz
clock. A logical zero written to this bit disables (i.e., three-states)
PLL operation for these clocks only.
5,4
CPU Clock Selection
(00)
50 MHz
(01)
40 MHz
(10)
33 MHz
(11)
25 MHz
S(1,0)
These bits select the CPU frequency for CPUCLK output. When
RESET* is active, S1 and S0 select the initial values of these
two bits; when RESET* rises, these bits are latched.
3–0
VCO Gain Control
(0000)–Range 0
(0001)–Range 1
(0010)–Range 2
:
(0111)–Range 7
(1000)–Range 8
:
(1001)–Reserved
:
(1111)–Reserved
1000
PLL VCO Gain Control.
VIDCLK* Cycle Control Register
The command register may be written to or read by the MPU at any time. Bit 0 corresponds to data bus bit D0.
Bit(s)
Field Name
7, 6
Reserved
5–0
VIDCLK Cycle Time Select
(000000) Reserved
(000001) CLOCK/2
(000010) CLOCK/3
(000011) CLOCK/4
:
(111101) CLOCK/62
(111110) CLOCK/63
(111111) CLOCK/64
Brooktree
®
Reset
Value
00
000011
Field Description
Reserved for future expansion.
These bits select the VIDCLK* cycle time in pixel clock units.
49
INTERNAL REGISTERS
Bt445
Pixel Load Control Register
Pixel Load Control Register
The command register may be written to or read by the MPU at any time. Bit 0 corresponds to data bus bit D0.
Bit(s)
7, 6
Field Name
Reset
Value
Field Description
Reserved
00
Reserved
5
SCLK* Number
0
A logic zero specifies that the number of pulses output at pin
“SCLK*” is fixed at TACTIVE/TSCLK, where TACTIVE is the time
of one horizontal scan line (BLANK de-asserted) and TSCLK is
one SCLK period. With a logic one, several additional SCLKs
will be output at the end of the horizontal scan line. These are
needed for non-integral ratios of MPX rate to VIDCLK* cycle
rate.
4
SCLK* Control
(0)
Extra pulse not needed
(1)
Extra pulse needed
0
This bit specifies whether the first SCLK* pulse after a blanked
time is needed (logical one) to read the first pixel item. A logical
zero indicates that the system has externally provided the first
VRAM shift clock, and the Bt445 may register valid pixel data
with the first SCLK*.
3
SCLK* Enable
(0)
SCLK* Disabled
(1)
SCLK* Enabled
0
A logical one must be written to this bit to enable SCLK*. A logical zero written to this bit three-states the SCLK* output and the
system should use VIDCLK* to generate LD/SCLKI.
2
VIDCLK* Enable
(0)
VIDCLK* Disabled
(1)
VIDCLK* Enabled
1
A logical one must be written to this bit to enable VIDCLK*. A
logical zero written to this bit three-states the VIDCLK* output.
Reserved (logical zero)
00
Reserved.
1, 0
Digital Output Control Register
The command register may be written to or read by the MPU at any time. Bit 0 corresponds to data bus bit D0.
50
Brooktree
®
INTERNAL REGISTERS
Bt445
MPX Rate Register
Bit(s)
Field Name
Reset
Value
Field Description
7
Operating Mode
(0)
4-4-4 True Color
(1)
8-8-8 True Color
0
This bit selects the 4-4-4 or 8-8-8 true-color mode. When this bit is a
logical zero, the 4-4-4 mode of operation is selected. In this mode the
appropriate PCLK edge delivers the high-order nibble of the data being
delivered to the DAC inputs. When this bit is a logical one, the 8-8-8
mode of operation is selected. In this mode the high-order nibble of
each pixel is delivered on each PCLK rising edge, and the low-order
nibble of each pixel is delivered on the falling edge of PCLK. In 8-8-8
mode, the PCLK edge select control is not used.
6
Reserved
0
Reserved.
5
OR, OG, OB(3–0)
Output Enable
(0)
Disable
(1)
Enable
0
This bit enables the red, green, and blue digital outputs. These outputs
should not be enabled when the pixel rate exceeds that specified by the
AC timing parameters for this output. A logical zero in this bit disables
(i.e., three-states) the red, green, and blue digital outputs. When
three-stated, these outputs will float to valid TTL levels since internal
pullup resistors are provided.
4
PVSYNC*, PHSYNC*
Output Enable
(0)
Disable
(1)
Enable
0
This bit enables the separate pipelined sync outputs. A logical one
enables the outputs; a logical zero causes these outputs to be
three-stated. When three-stated, an internal pullup resistor maintains
this output at a logical one, provided that it is lightly loaded.
3
PSYNC* Output Enable
(0)
Disable
(1)
Enable
0
This bit enables the pixel-synchronized, pipelined sync output signal. It
may be used to generate the TTL sync signal required by monitors having separate sync. A logical one enables the output; a logical zero
causes this output to be three-stated. When three-stated, an internal
pullup resistor maintains this output at a logical one, provided that it is
lightly loaded.
2
PBLANK* Output Enable
(0)
Disable
(1)
Enable
0
This bit enables the pixel-synchronized, pipelined blank output signal. A
logical one enables the output; a logical zero causes this output to be
three-stated. When three-stated, an internal pullup resistor maintains
this output at a logical one, provided that it is lightly loaded.
1
PCLK Edge Select
(0)
Rising edge
(1)
Falling edge
0
This bit selects the edge of PCLK to which the digital output changes
will be synchronized. A logical zero causes the AC timing parameters
for the digital pixel outputs to be referenced to the rising edge of PCLK.
A logical one causes the AC timing parameters for the digital pixel outputs to be referenced to the falling edge of PCLK. This bit is not used
when the 8-8-8 mode of operation is selected.
0
PCLK Output Enable
(0)
Disable
(1)
Enable
0
This bit enables the PCLK output of the digital pixel output port. This
output should not be enabled when the pixel rate exceeds that specified by the AC timing parameters for this output. A logical one enables
the outputs; a logical zero causes this output to be three-stated. When
three-stated, an internal pullup resistor maintains this output at a logical
one, provided that it is lightly loaded.
MPX Rate Register
Brooktree
®
51
INTERNAL REGISTERS
Bt445
Blink Enable Register
Bit(s)
Field Name
Reset
Value
Field Description
7, 6
Reserved
00
Reserved for future expansion
5–0
MPX Rate
($00) Reserved
($01) 2:1
($02) 3:1
($03) 4:1
:
($3E) 63:1
($3F) 64:1
$03
Number of pixels loaded per input pixel load cycle. The value
specified should be consistent with the pixel depth; i.e. the number
of pixels multiplied by the pixel depth less than or equal to the
number of bits for which the input port is configured.
ID Register
This 8-bit register may be read by the MPU to determine the type of RAMDAC being used in the system. The value
is different for each RAMDAC. For the Bt445, the value read by the MPU will be $3A. Data written to this register
is ignored.
Revision Register
This 8-bit register is a read-only register, specifying the revision of the Bt445. The four most significant bits signify
the revision letter, D, in hexadecimal form. The four least significant bits do not represent any value and should be ignored.
Read Enable Register
Writing this Bt458-compatible register location causes the red, green, and blue read enable registers to be simultaneously written with the MPU data. Each read enable register is used to enable (logical one) or disable (logical zero)
red, green, and blue planes from addressing the color palette RAM. D(7–0) correspond to bits 7–0 of the red, green,
and blue fields of each pixel, respectively. Each register bit is logically ANDed with the corresponding field bit input.
These registers may be written to or read by the MPU at any time and are initialized to $FF. An MPU read of this register reads the contents of the green read enable register.
Blink Enable Register
52
Brooktree
®
INTERNAL REGISTERS
Blink Enable Register
Bt445
Writing this Bt458-compatible register location causes the red, green, and blue read blink registers to be simultaneously written with the MPU data. The blink enable register is used to enable (logical one) or disable (logical zero)
individual bits in the red, green, and blue color fields from blinking at the blink rate and duty cycle specified by the
command register. D(7–0) correspond to field bits 7–0, respectively. In order for a bit plane to blink, the corresponding bit in the read enable register must be a logical one. This register may be written to or read by the MPU at any time
and is initialized to $00. An MPU read of this register reads the contents of the green blink enable register.
Signature Analysis Registers (SAR)
Signature Analysis Operation
The three 8-bit SARs may be read by the MPU while BLANK* is a logical zero. While BLANK* is a logical one, the
signatures are being acquired. The MPU may write to the output SARs while BLANK* is a logical zero to load the
seed value. The output SARs use data being loaded into the output DACs to calculate the signatures. JTAG logic can
access the output SAR independently of the MPU operation. MPU accesses to the SARs require one address register
load followed by three reads or writes to the red, green, and blue signature registers, respectively. D0 corresponds to
R0, G0, and B0.
By loading a test display into the frame buffer, a given value for the red, green, and blue signature registers will be
returned if all circuitry is working properly.
It is imperative that the MPU adhere to conditions required to prevent the disruption of pixel data during signature
acquisition to ensure consistent results. See the AC Characteristics section for further information.
Test Register 0
The test register provides Bt458-compatible diagnostic capability by enabling the MPU to read the inputs to the D/A
converters. It may be written to or read by the MPU at any time, and is initialized to DAC-select equals none. When
writing to the register, the upper four bits (D4–D7) are ignored. The contents of the test register are defined in Table 8.
To use test register 0, the host MPU writes to it, selecting the nibble and the DAC input to be read. This specifies
which four bits of color information the MPU wishes to read (R(3–0), G(3–0), B(3–0), R(7–4), G(7–4), or B(7–4)).
When the MPU reads test register 0, the 4 bits of color information from the DAC inputs are contained in the upper
four bits of the MPU data bus, and the lower four bits contain the red, green, blue, low, or high nibble selection information previously written. Note that either the pixel clock must be as slow as the MPU cycle time, or the same pixel and overlay data must be presented to the device during the entire MPU read cycle.
For example, to read the upper four bits of red color information being presented to the D/A converters, the MPU
writes to test register 0, setting the DAC select field to 001 and the low nibble select to 0. The MPU then reads test
register 0, keeping the pixel data stable, which results in D(7–4) containing the R(7–4) DAC input bits, and D(3–0)
containing the red, green, blue, low, or high nibble enable information, as illustrated in Table 9. The comparator,
which may be accessed in Test Register 1 (see Table 10), enables the MPU to determine whether the CRT monitor is
connected to the analog RGB outputs or not, and whether the DACs are functional. When the monitor is not connected
or one of the analog cables connecting the monitor is open (i.e., broken), the voltage present at the corresponding
DAC output would be higher than predicted, as one of the termination resistors would not be present.
Brooktree
®
53
INTERNAL REGISTERS
Bt445
Blink Enable Register
Table 8. Test Register 0
Bit(s)
7–4
3
2–0
Reset
Value
Field Name
DAC Input Data
Low Nibble Select
(0)
High Nibble
(1)
Low Nibble
N/A
Color information at DAC input (four bits of red, green, or blue).
Data written to this field is ignored.
0
Writing a logical one to this field enables the low nibble (i.e., bits
3–0) of the selected DAC input to be read from bits 7–4 of this
test register. Writing a logical zero to this field enables the high
nibble (i.e., bits 7–4) of the selected DAC inputs to be read from
bits 7–4 of this test register.
000
DAC Select
(000) None
(001) Red
(010) Green
(100) Blue
All other decodes are reserved.
Field Description
Blue enable
Green enable
Red enable
Table 9. Test Register 0 Example
MPU Bus Bits
Value Read
7–4
R(7–4)
3–0
0001
Table 10. Test Register 1
Reset
Value
Bit(s)
Field Name
7, 6
Operand 1 Select
(00)
Normal Operation
(01)
Select Green DAC Output
(10)
Select Red DAC Output
(11)
Reserved
00
This field selects Operand 1 of the comparator. For normal
operation, the operand 1 and 2 fields should both contain 00.
5, 4
Operand 2 Select
(00)
Normal Operation
(01)
Select 145 mV Reference
(10)
Select Blue DAC Output
(11)
Reserved
00
This field selects Operand 2 of the comparator. For normal
operation, the operand 1 and 2 fields should both contain 00.
Comparison Result
(0)
Op1 < Op2
(1)
Op1 > Op2
N/A
This field yields the result of the comparison of the DAC and/or
reference output. Comparing operands whose values lie within
a few LSBs will yield unpredictable results. Data written to this
bit are ignored, as this field is read only. This result is valid only
after the required comparison settling time is reached (i.e., 5 µs
after the operand becomes constant).
Reserved
000
Reserved.
3
2–0
54
Field Description
Brooktree
®
PC BOARD CONSIDERATIONS
The Bt445 layout should be optimized for lowest noise on the Bt445 power and
ground lines by shielding the digital inputs and providing good decoupling. The
trace length between groups of VAA and GND pins should be as short as possible
to minimize inductive ringing.
A well-designed power distribution network is critical to eliminating digital
switching noise. The ground planes must provide a low-impedance return path for
the digital circuits. A PC board with a minimum of six layers is recommended. The
ground layer should be used as a shield to isolate noise from the analog traces with
layer 1 (top) the analog traces, layer 2 the ground plane (preferable analog ground
plane), layer 3 the analog power plane, and the remaining layers used for digital
traces and digital power supplies.
The optimum layout enables the Bt445 to be located as close as possible to the
power supply connector and the video output connector.
Power and
Ground Planes
The power and ground planes need isolation gaps to minimize digital switching
noise effects on the analog signals and components. These gaps need to be at least
1/8” wide. They are placed so that digital currents cannot flow through a peninsula
that contains the analog components, signals, and video connector. A sample layout is shown in Figure 13.
Device Decoupling
For optimum performance, all capacitors should be located as close to the device
as possible, using the shortest leads possible (consistent with reliable operation) to
reduce the lead inductance. Chip capacitors are recommended for low lead inductance. Radial lead ceramic capacitors may be substituted for chip capacitors and
are better than axial lead capacitors for self-resonance. Values are chosen to have
self-resonance above the pixel clock.
Power Supply
Decoupling
Best power supply decoupling performance is obtained by providing a 0.1 µF ceramic capacitor in parallel with a 0.01 µF chip capacitor to decouple each group of
VAA pins to GND. The capacitors should be placed as close as possible to the device VAA and GND pins.
The 33 µF capacitor shown in Figure 14 is for low-frequency power supply ripple; the 0.1 µF and 0.01 µF capacitors are for high-frequency power supply noise
rejection. The decoupling capacitors should be connected at the VAA and GND
pins, using short, wide traces.
Brooktree
®
55
PC BOARD CONSIDERATIONS
COMP Decoupling
Bt445
A linear regulator is recommended to filter the power supply if the power supply
noise is more than 200 mV. This is especially important when a switching power
supply is used and the switching frequency is close to the raster scan frequency.
Note that about 10 percent of power supply hum and ripple noise less than 1 MHz
will couple onto the analog outputs.
56
COMP Decoupling
The COMP pin must be decoupled to COMP 2, typically using a 0.1 µF ceramic
capacitor. Low-frequency supply noise will require a larger value. The COMP capacitor must be as close as physically possible to the COMP and COMP2 pins. A
surface-mount ceramic chip capacitor is preferred for minimal lead inductance,
which degrades the noise rejection of the circuit. Short, wide traces will also reduce lead inductance.
If the display has a ghosting problem, additional capacitance in parallel with the
COMP capacitor may help fix the problem.
Digital Signal
Interconnect
The digital inputs to the Bt445 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay
the analog power and output signals.
Most noise on the analog outputs will be caused by excessive edge rates (less
than 3 ns), overshoot, undershoot, and ringing on the digital inputs.
The digital edge rates should be no faster than necessary, as feedthrough noise
is proportional to the digital edge rates. Lower speed applications will benefit using lower speed logic (3–5 ns edge rates) to reduce data-related noise on the analog
outputs.
Transmission lines will mismatch if the lines do not match the source and destination impedance. This will degrade signal fidelity if the line length reflection
time is greater than one fourth the signal edge time. Line termination or line length
reduction is the solution. For example, logic edge rates of 2 ns require line lengths
of less than 4 inches without using termination. Ringing may be reduced by damping the line with a series resistor (30–300 Ω).
Radiation of digital signals can also be picked up by the analog circuitry. This
is prevented by reducing the digital edge rates (rise/fall time), minimizing ringing
by using damping resistors, and minimizing coupling through PC board capacitance by routing 90 degrees to any analog signals.
The clock driver and all other digital devices on the circuit board must have adequate decoupling to prevent the noise generated by the digital devices from coupling into the analog circuitry.
Brooktree
®
PC BOARD CONSIDERATIONS
Bt445
Analog Signal Interconnect
Figure 13. Representative Power/Ground Analog Area Layout.
AAAA
AAAA
AAA
AAAA
AA
AA
AA
A
AA
AAA
AA
AAAA
AAAA
AAAA
Digital
Area
Bt445
Video
C onnector
Analog
Area
Digital
Area
Board Edge
Brooktree
®
Analog Signal
Interconnect
The Bt445 should be located as close as possible to the output connectors to minimize noise pickup and reflections due to impedance mismatch.
The video output signals should not overlay the analog power plane, to maximize the high-frequency power supply rejection.
For maximum performance, the analog video output impedance, cable impedance, and load impedance should be the same.
Analog output video edges exceeding the CRT monitor bandwidth can be reflected, producing cable-length dependent ghosts. Simple pulse filters can reduce
high-frequency energy, reducing EMI and noise. The filter impedance must match
the line impedance.
Analog Output
Protection
The Bt445 analog outputs should be protected against high-energy discharges,
such as those from monitor arc-over or from “hot-switching” AC-coupled monitors.
The diode protection circuit shown in Figure 14 can prevent latchup under severe discharge conditions without adversely degrading analog transition times.
The 1N4148/9 are low-capacitance, fast-switching diodes, which are also available
in multiple-device packages (FSA250X or FSA270X) or surface-mountable pairs
(BAV99 or MMBD7001).
57
PC BOARD CONSIDERATIONS
Bt445
Analog Output Protection
Figure 14. Typical Connection Diagram and Parts List.
Locate as close as
possible to Bt445
Bt445
C12
+
C11
VAA
(@ pin 23)
+5 (VCC)
VAA
R4
C9
+
RANGE
C1
C10
VREF
C2-C4
C5-C7
Z1
XTALI
GROUND
GND
X1
RSET
R1
R2
R3
XTAL2
FS ADJUST
IOR
IOG
IOB
COMP2
COMP
C8
TO
MONITOR
VAA
1N4148/9
DAC
OUTPUT
TO
MONITOR
1N4148/9
GND
Diode Protection Circuit
Location
Vendor Part Number
0.1 µF ceramic capacitor
Erie RPE112Z5U104M50V
0.01 µF ceramic chip capacitor
AVX 12102T103QA1018
C10
33 µF tantalum capacitor
Mallory CSR13F336KM
C12
4.7 µF tantalum capacitor
C1–C4, C8, C9
C5–C7, C11
R1, R2, R3
R4
RSET
58
Description
75 Ω 1% metal film resistor
Dale CMF-55C
1000 Ω 5% Resistor
523 Ω 1% metal film resistor
X1
20 MHz crystal
Z1
1.2 voltage reference
Dale CMF-55C
National Semiconductor LM385Z-1.2
Brooktree
®
APPLICATION INFORMATION
Test Features of the Bt445
The Bt445 contains a dedicated test register and an analog output comparator that
assist the user in evaluating the performance and functionality of the part. This section is intended to explain the operating usage of these test features.
Signature Register
Brooktree
®
When enabled, the output signature registers operate with the 24 bits of data that
are presented to the DAC inputs. These 24-bit vectors represent a single pixel-color, and are presented as inputs simultaneously to the red, green, and blue SARs, as
well as the three on-chip DACs.
The SARs act as a wide linear feedback shift register on each succeeding DAC
input. It is important to note that in all the multiplexed modes the SARs register every pixel.
The Bt445 will only generate signatures while in active-display (BLANK* negated). The SARs are available for reading and writing via the MPU port when the
Bt445 is in a blanking state (BLANK* asserted). Specifically, it is safe to access
the SARs after the DAC outputs are in the blanking state (up to 24 pixel clock periods after BLANK* is asserted).
Typically, the user will write a specific 24-bit seed value into the SARs. Then,
a known pixel stream will be input to the chip, for example, one scan-line or one
frame buffer of pixels. Then, at the succeeding blank state, the resultant 24-bit signature can be read by the MPU. The 24-bit signature register data is a result of the
same captured data that are fed to the DACs. Thus, overlay, cursor, and palette bypass data validity is also tested using the signature registers.
The SAR configuration is shown in Figure 15.
Experienced users have developed tables of specific seeds and pixel streams,
and recorded the signatures that result from those inputs applied to known-good
parts. Note that a good signature from one given pixel stream can be used as the
seed for the succeeding stream to be tested. Any signature is deterministically created from a starting seed, and the succeeding pixel stream fed to the SARs.
59
APPLICATION INFORMATION
Test Features of the Bt445
Bt445
When performing system tests that use the signature analysis registers, it is recommended that the pipeline delay be reset prior to the test to provide optimal allowance for input clock drift. This prevents the disruption of pixel data because of
pipeline auto-reset, which may occur as the phase relation of the input clock drifts,
with respect to the output clocks. Excessive input clock drift may require that signatures be acquired over shorter periods when the maximum drift may be more
tightly controlled. This is especially recommended during environmental and power supply variation testing.
Analog Comparator
The other dedicated test structure in the Bt445 is the analog comparator. It allows
the user to measure the DACs against each other, as well as against a specific reference voltage.
Four combinations of tests are selected via the Test Register. With a given setting, the respective signals (DAC outputs or the 145 mV reference) will be continuously input to the comparator. The result of the comparator is latched into the Test
Register. The capture occurs over one LD/SCLKI period. Pin P0 must be set to a
logical one for capture to occur.
Due to the simple design of the comparator, it is recommended that the DAC
outputs be stable for 5 µs before capture. At a display rate of 100 MHz, 5 µs corresponds to 500 pixels. Furthermore, either the color palette RAM or the pixel inputs (or both) should be configured to guarantee a single continuous output from
the DACs under test, until capture.
Figure 15. Signature Analysis Register Circuit
G0–G7
B0–B7
8
8
8
Red
IN
0
R0–R7
1 2
3 4
5 6
7
IN
0 1
Green
2 3
4 5
6 7
IN
0 1
Blue
2 3
4 5
6 7
Q
D
DFF
60
Brooktree
®
APPLICATION INFORMATION
Bt445
Initializing the Bt445
Initializing the Bt445
Following the assertion of the reset signal, the Bt445 pixel unpacking logic and pixel formatting logic are initialized
to the Bt458 4:1 MPX mode of operation. See Table 11.
Table 11. Reset Initialization
Control Register
Value
Description
Pixel Port Start Position
$40
4 pixels, each with 8-bit pseudo color and 2-bit overlay.
Pixel Depth
$10
8-bit pseudo color and 2-bit overlay.
Pixel Multiplex Rate
$04
4:1 Multiplexed.
Red, Green, Blue MSB Position
$07
8-bit pseudo-color sources Red, Green, and Blue from
same field starting from low-order bit of pixel.
Red, Green, Blue Width
$08
Represents pixel width of 8 for Red, Green, and Blue
Red, Green, Blue Enable
$FF
All planes used.
Red, Green, Blue Blink
$00
Pixel blinking disabled.
Overlay MSB Position
$09
Overlay comes in on next high-order pixels above 8-bit
pseudo-color bits.
Overlay Width
$02
2-bit overlay supported in Bt458.
Overlay Enable
$03
Bit planes 0 and 1 enabled.
Overlay Blink
$00
Overlay blinking disabled.
Brooktree
®
61
APPLICATION INFORMATION
Bt445
Color Palette Initialization
Color Palette Initialization
Table 12 shows the sequence of MPU writes required to load the color palette entries:
Table 12. Color Palette Initialization
Operation
Description
C(2_0)
Internal
Address
Register
MPU Data
Color Palette RAM Initialization
Write $00 to address register
Write red data to RAM (location $00)
Write green data to RAM (location $00)
Write blue data to RAM (location $00)
Write red data to RAM (location $01)
Write green data to RAM (location $01)
Write blue data to RAM (location $01)
:
Write red data to RAM (location $FF)
Write green data to RAM (location $FF)
Write blue data to RAM (location $FF)
000
001
001
001
001
001
001
:
001
001
001
–
$00
$00
$00
$01
$01
$01
:
$FF
$FF
$FF
$00
$rr
$gg
$bb
$rr
$gg
$bb
:
$rr
$gg
$bb
Overlay Color Palette Initialization
Write $00 to address register
Write red data to overlay (location $0)
Write green data to overlay (location $0)
Write blue data to overlay (location $0)
Write red data to overlay (location $1)
Write green data to overlay (location $1)
Write blue data to overlay (location $1)
:
Write red data to overlay (location $F)
Write green data to overlay (location $F)
Write blue data to overlay (location $F)
000
011
011
011
011
011
011
:
011
011
011
–
$00
$00
$00
$01
$01
$01
:
$0F
$0F
$0F
$00
$rr
$gg
$bb
$rr
$gg
$bb
:
$rr
$gg
$bb
Cursor Palette Initialization
Write $00 to address register
Write red data to cursor (location $0)
Write green data to cursor (location $0)
Write blue data to cursor (location $0)
Write red data to cursor (location $1)
Write green data to cursor (location $1)
Write blue data to cursor (location $1)
:
Write red data to cursor (location $3)
Write green data to cursor (location $3)
Write blue data to cursor (location $3)
000
111
111
111
111
111
111
:
111
111
111
–
$00
$00
$00
$01
$01
$01
:
$03
$03
$03
$00
$rr
$gg
$bb
$rr
$gg
$bb
:
$rr
$gg
$bb
62
Brooktree
®
APPLICATION INFORMATION
Bt445
Pipeline Delay Initialization
Pipeline Delay Initialization
The Bt445 employs a variable pipeline delay to allow for easier system implementation. This scheme allows the LD/SCLKI and VIDCLKI signals to drift relative to
the pixel clock (as would occur with varying environmental conditions such as
warm-up and power supply fluctuations) without corrupting the output pixel data
stream. The amount of allowable drift depends on the MPX Rate. This compares
favorably with fixed-pipeline delay devices where the drift is necessarily less than
one pixel clock to the point of pixel loss or duplication.
For optimum performance, the pipeline depth should be initialized away from
the extremes of the drift window to allow for subsequent drift. This is accomplished under the MPUs control by the transition of the RESET PIPELINE field in
the Command Register 1 from 0 to 1. The MPU should reset the pipeline whenever
any of the following registers or fields are changed: the Pixel Port Start Position
Register, the Pixel Unpacking Order Field, the MPX Rate Register, the Pixel Depth
Control Register, the PLL Rate Registers, the Pixel Clock PLL Enable Field, The
VCO Gain Control Field, or the SCLK* Enable field.
Additionally, when changing any controls affecting the pixel PLL rate or VCO
gain, sufficient time should be allowed for the PLL to stabilize to the new rate prior
to the MPU issuing the pipeline delay initialization.
PLL Initialization
Crystal Frequency
Selection
The crystal frequency should be selected based on the required pixel rate(s), the
display pixel rate tolerance, and the required system clock outputs. When using the
Bt445-generated system clocks, because the system clock ratios are fixed, the crystal reference frequency is usually dictated by required system clock rates. The desired ratio for the PLL can then be computed by dividing the required pixel rate by
the crystal frequency, looking up the M and N values in Table 13 for the closest ratio, and ensuring that the display can still satisfactorily operate within the best-fit
pixel rate and associated CRT timings.
Ratio Selection
The PLL clock ratio is set by programming the M and N values through the MPU
port. Reset M and N values are $19 and $04, respectively, yielding a pixel rate of
5 times the crystal reference.
Table 13 shows the complete range of M/N ratios for M ranges from 24–63 and
N ranges from 4–15 and L = 1, for 20.0 and 14.318 MHz crystals.
For PCLK frequencies below 80 MHz it is recommended to use the L divider to
obtain the slower frequency.
Brooktree
®
63
APPLICATION INFORMATION
Bt445
PLL Initialization
Table 13. Sample Pixel Clock Rates (1 of 7)
Reference Crystal (MHz):
M/N
64
M
N
20
14.31818
PCLK
PCLK
3.75
30
8
75
N/A
3.769
49
13
75.385
N/A
3.778
34
9
75.556
N/A
3.786
53
14
75.714
N/A
3.8
38
10
76
N/A
3.818
42
11
76.364
N/A
3.833
46
12
76.667
N/A
3.846
50
13
76.923
N/A
3.857
27
7
77.143
N/A
3.867
58
15
77.333
N/A
3.875
31
8
77.5
N/A
3.889
35
9
77.778
N/A
3.9
39
10
78
N/A
3.909
43
11
78.182
N/A
3.917
47
12
78.333
N/A
3.923
51
13
78.462
N/A
3.929
55
14
78.571
N/A
3.933
59
15
78.667
N/A
4
24
6
80
N/A
4.067
61
15
81.333
N/A
4.071
57
14
81.429
N/A
4.077
53
13
81.538
N/A
4.083
49
12
81.667
N/A
4.091
45
11
81.818
N/A
4.1
41
10
82
N/A
4.111
37
9
82.222
N/A
4.125
33
8
82.5
N/A
4.133
62
15
82.667
N/A
4.143
29
7
82.857
N/A
4.154
54
13
83.077
N/A
4.167
25
6
83.333
N/A
Brooktree
®
APPLICATION INFORMATION
Bt445
PLL Initialization
Table 13. Sample Pixel Clock Rates (2 of 7)
Reference Crystal (MHz):
M/N
Brooktree
®
M
N
20
14.31818
PCLK
PCLK
4.182
46
11
83.636
N/A
4.2
42
10
84
N/A
4.214
59
14
84.286
N/A
4.222
38
9
84.444
N/A
4.231
55
13
84.615
N/A
4.25
34
8
85
N/A
4.273
47
11
85.455
N/A
4.286
30
7
85.714
N/A
4.3
43
10
86
N/A
4.308
56
13
86.154
N/A
4.333
26
6
86.667
N/A
4.357
61
14
87.143
N/A
4.364
48
11
87.273
N/A
4.375
35
8
87.5
N/A
4.385
57
13
87.692
N/A
4.4
44
10
88
N/A
4.417
53
12
88.333
N/A
4.429
31
7
88.571
N/A
4.444
40
9
88.889
N/A
4.455
49
11
89.091
N/A
4.462
58
13
89.231
N/A
4.5
27
6
90
N/A
4.538
59
13
90.769
N/A
4.545
50
11
90.909
N/A
4.556
41
9
91.111
N/A
4.571
32
7
91.429
N/A
4.583
55
12
91.667
N/A
4.6
46
10
92
N/A
4.615
60
13
92.308
N/A
4.625
37
8
92.5
N/A
4.636
51
11
92.727
N/A
65
APPLICATION INFORMATION
Bt445
PLL Initialization
Table 13. Sample Pixel Clock Rates (3 of 7)
20
14.31818
PCLK
PCLK
Reference Crystal (MHz):
M/N
66
M
N
4.667
28
6
93.333
N/A
4.692
61
13
93.846
N/A
4.7
47
10
94
N/A
4.714
33
7
94.286
N/A
4.727
52
11
94.545
N/A
4.75
38
8
95
N/A
4.769
62
13
95.385
N/A
4.778
43
9
95.556
N/A
4.8
24
5
96
N/A
4.818
53
11
96.364
N/A
4.833
29
6
96.667
N/A
4.846
63
13
96.923
N/A
4.857
34
7
97.143
N/A
4.875
39
8
97.5
N/A
4.889
44
9
97.778
N/A
4.9
49
10
98
N/A
4.909
54
11
98.182
N/A
4.917
59
12
98.333
N/A
5
25
5
100
N/A
5.083
61
12
101.667
N/A
5.091
56
11
101.818
N/A
5.1
51
10
102
N/A
5.111
46
9
102.222
N/A
5.125
41
8
102.5
N/A
5.143
36
7
102.857
N/A
5.167
31
6
103.333
N/A
5.182
57
11
103.636
N/A
5.2
26
5
104
N/A
5.222
47
9
104.444
N/A
5.25
42
8
105
75.17
5.273
58
11
105.455
75.496
Brooktree
®
APPLICATION INFORMATION
Bt445
PLL Initialization
Table 13. Sample Pixel Clock Rates (4 of 7)
20
14.31818
PCLK
PCLK
Reference Crystal (MHz):
M/N
Brooktree
®
M
N
5.286
37
7
105.714
75.682
5.3
53
10
106
75.886
5.333
32
6
106.667
76.364
5.364
59
11
107.273
76.798
5.375
43
8
107.5
76.96
5.4
27
5
108
77.318
5.429
38
7
108.571
77.727
5.444
49
9
108.889
77.955
5.455
60
11
109.091
78.099
5.5
33
6
110
78.75
5.545
61
11
110.909
79.401
5.556
50
9
111.111
79.545
5.571
39
7
111.429
79.773
5.6
28
5
112
80.182
5.625
45
8
112.5
80.54
5.636
62
11
112.727
80.702
5.667
34
6
113.333
81.136
5.7
57
10
114
81.614
5.714
40
7
114.286
81.818
5.727
63
11
114.545
82.004
5.75
46
8
115
82.33
5.778
52
9
115.556
82.727
5.8
29
5
116
83.045
5.833
35
6
116.667
83.523
5.857
41
7
117.143
83.864
5.875
47
8
117.5
84.119
5.889
53
9
117.778
84.318
5.9
59
10
118
84.477
6
24
4
120
85.909
6.1
61
10
122
87.341
6.111
55
9
122.222
87.5
6.125
49
8
122.5
87.699
6.143
43
7
122.857
87.955
6.167
37
6
123.333
88.295
6.2
31
5
124
88.773
67
APPLICATION INFORMATION
Bt445
PLL Initialization
Table 13. Sample Pixel Clock Rates (5 of 7)
20
14.31818
PCLK
PCLK
Reference Crystal (MHz):
M/N
68
M
N
6.222
56
9
124.444
89.091
6.25
25
4
125
89.489
6.286
44
7
125.714
90
6.3
63
10
126
90.205
6.333
38
6
126.667
90.682
6.375
51
8
127.5
91.278
6.4
32
5
128
91.636
6.429
45
7
128.571
92.045
6.444
58
9
128.889
92.273
6.5
26
4
130
93.068
6.556
59
9
131.111
93.864
6.571
46
7
131.429
94.091
6.6
33
5
132
94.5
6.625
53
8
132.5
94.858
6.667
40
6
133.333
95.455
6.714
47
7
134.286
96.136
6.75
27
4
135
96.648
6.778
61
9
135.556
97.045
6.8
34
5
136
97.364
6.833
41
6
136.667
97.841
6.857
48
7
137.143
98.182
6.875
55
8
137.5
98.437
6.889
62
9
137.778
98.636
7
28
4
140
100.227
7.125
57
8
142.5
102.017
7.143
50
7
142.857
102.273
7.167
43
6
143.333
102.614
7.2
36
5
144
103.091
7.25
29
4
145
103.807
7.286
51
7
145.714
104.318
7.333
44
6
146.667
105
7.375
59
8
147.5
105.597
7.4
37
5
148
105.955
7.429
52
7
148.571
106.364
7.5
30
4
150
107.386
Brooktree
®
APPLICATION INFORMATION
Bt445
PLL Initialization
Table 13. Sample Pixel Clock Rates (6 of 7)
20
14.31818
PCLK
PCLK
Reference Crystal (MHz):
M/N
Brooktree
®
M
N
7.571
53
7
151.429
108.409
7.6
38
5
15.2
108.818
7.625
61
8
152.5
109.176
7.667
46
6
153.333
109.773
7.714
54
7
154.286
110.455
7.75
31
4
155
110.966
7.8
39
5
156
111.682
7.833
47
6
156.667
112.159
7.857
55
7
157.143
112.5
7.875
63
8
157.5
112.756
8
32
4
160
114.545
8.143
57
7
N/A
116.591
8.167
49
6
N/A
116.932
8.2
41
5
N/A
117.409
8.25
33
4
N/A
118.125
8.286
58
7
N/A
118.636
8.333
50
6
N/A
119.318
8.4
42
5
N/A
120.273
8.429
59
7
N/A
120.682
8.5
34
4
N/A
121.705
8.571
60
7
N/A
122.727
8.6
43
5
N/A
123.136
8.667
52
6
N/A
124.091
8.714
61
7
N/A
124.773
8.75
35
4
N/A
125.284
8.8
44
5
N/A
126
8.833
53
6
N/A
126.477
8.857
62
7
N/A
126.818
9
36
4
N/A
128.864
9.167
55
6
N/A
131.25
9.2
46
5
N/A
131.727
9.25
37
4
N/A
132.443
69
APPLICATION INFORMATION
Bt445
PLL Initialization
Table 13. Sample Pixel Clock Rates (7 of 7)
Reference Crystal (MHz):
M/N
M
N
20
14.31818
PCLK
PCLK
9.333
56
6
N/A
133.636
9.4
47
5
N/A
134.591
9.5
38
4
N/A
136.023
9.6
48
5
N/A
137.455
9.667
58
6
N/A
138.409
9.75
39
4
N/A
139.602
9.8
49
5
N/A
140.318
9.833
59
6
N/A
140.795
10
40
4
N/A
143.182
10.167
61
6
N/A
145.568
10.2
51
5
N/A
146.045
10.25
41
4
N/A
146.761
10.333
62
6
N/A
147.955
10.4
52
5
N/A
148.909
10.5
42
4
N/A
150.341
10.6
53
5
N/A
151.773
10.75
43
4
N/A
153.92
10.8
54
5
N/A
154.636
11
44
4
N/A
157.5
Table 14. Recommended VCO Gain Control
Note:
70
Pixel Frequency Range
Pre L-Divider
VCO Gain Control Range
75–89
7
90–100
6, 7
101–109
5, 6, 7
110–119
4, 5, 6, 7
120–129
3, 4, 5, 6
130–140
2, 3, 4, 5
140–150
0, 1, 2, 3
Various applications may select one of the recommended VCO Gain numbers depending on temperature and board conditions.
Brooktree
®
APPLICATION INFORMATION
Frame Buffer Interface Configurations
Bt445
Frame Buffer Interface Configurations
The Bt445 may be operated with an internal PLL or an external clock generator.
Additionally, the Bt445 may be used to generate the VRAM serial shift clock signal, or this signal may be generated externally. The following figures show examples of the frame buffer interface when using the Bt445 in various modes.
Externally Generated
Pixel Clock with
Externally Generated
VRAM Serial Shift Clock
In this configuration, neither the SCLK* nor VIDCLK* outputs of the Bt445 are
used, and thus they should be disabled via the command registers. The pixel clock,
load clock, and VRAM serial shift clock are externally generated by a device such
as the Bt438. Figure 16 illustrates this configuration.
The multiplex rates supported are limited by the modes for which the external
clock divider can be configured. The SYNC* and BLANK* information loaded
correspond to the pixel data loaded on the same LD clock rising edge. The maximum pixel clock rate is 150 MHz.
Figure 16. Frame Buffer Interface, External Pixel Clock, and Serial Clock Generation
Crystal/
Oscillator
Shift
Enable
ENAB(S)
Bt445
OSC*
OSC
CLK
CLK*
Bt438
LDA
LDC
IOR
IOG
IOB
LD
SCLK
VIDCLKI
LD/SCKLI
Controls
System Bus or
Graphics Pipeline
Memory
Controller
Address
Data
VRAM
Frame
Buffer
Serial Data
P(63–0)
SYNC*
BLANK*
Brooktree
®
71
APPLICATION INFORMATION
Bt445
Frame Buffer Interface Configurations
PLL-Generated Pixel
Clock with Externally
Generated VRAM Shift
Clock
In this configuration, the Bt445 generates the pixel clock internally from the M and
N values contained in the control registers. The VRAM shift clock is still externally generated, but the system must use the Bt445's VIDCLK* output, as there is no
other system reference that is phase related to the pixel clock. The memory controller produces a clock gate signal for generating the VRAM shift clock from
VIDCLK*. Figure 17 illustrates this configuration.
The inverting drivers used to generate LD/SCLKI and the VRAM shift clock
should ideally have correlated delays and high-impedance, low capacitance inputs.
Figure 17. Frame Buffer Interface, with PLL Pixel Clock and no Bt445-Provided Shift Clock
Crystal
XTAL1
XTAL2
VIDCLKI
LD/SCKLI
LD
VIDCLK*
SCLK Enable
IOR
IOG
IOB
SCLK
System Bus or
Graphics Pipeline
Memory
Controller
Controls
Address
Data
Bt445
VRAM
Frame
Buffer
Serial Data
P(63–0)
SYNC*
BLANK*
72
Brooktree
®
APPLICATION INFORMATION
Frame Buffer Interface Configurations
Bt445
Bt445-Generated VRAM
Shift Clock, Externally
Generated Pixel Clock
In this configuration, the pixel clock is generated in an external oscillator. The
Bt445 provides two clocks to the system: VIDCLK* and SCLK*. VIDCLK* is always free running and is used to control the CRT timing generator, usually part of
the controller. VIDCLKI is used to register the SYNC*, and BLANK* signals.
LD/SCLKI is used to register the pixel data. Figure 18 illustrates this configuration.
SCLK* is asserted as needed to shift out pixel data from the VRAMs, according
to the MPX rate specified by a control register. Generally, VIDCLK* and SCLK*
do not run at the same rate; hence, the granularity with which SYNC* and
BLANK* are specified is not the same as the MPX rate. As a result, the last group
of pixels loaded with LD/SCLKI at the end of an active scan line, may not all be
displayed. It should be noted that in this configuration, the SYNC* and BLANK*
information does not correlate to the data on the Bt445's pixel input port; however,
the Bt445 internally aligns the CRT timing controls with the pixel data for output.
Also, the buffer delays for VIDCLK* and SCLK* need not be correlated.
The SCLK control signal supplied by the memory controller is used only to insert shift clocks for the purpose of loading the shift register tap address required by
VRAMs supporting split-shift register operations.
The pixel rate in this configuration may be up to 150 MHz.
Figure 18. Frame Buffer Interface with Externally Generated Pixel Clock and Bt445-Generated SCLK
Pixel Rate
Oscillator
CLOCK
CLOCK*
Mid-line Xfer Control
SCLK*
LD/SCLKI
SCLK
IOR
IOG
IOB
Controls
System Bus or
Graphics Pipeline
Memory
Controller
Data
VIDCLK
Brooktree
®
Address
VRAM
Frame
Buffer
Bt445
Serial Data
P(63–0)
VIDCLKI
VIDCLK*
SYNC*
BLANK*
73
APPLICATION INFORMATION
Bt445
Frame Buffer Interface Configurations
The Bt445-Generated
VRAM Shift Clock and
PLL-Generated Pixel
Clock
This configuration is very similar to the previous one without the PLL generated
pixel clock. Here, a relatively low frequency crystal is connected to the XTAL1,
XTAL2 inputs, instead of using an ECL oscillator operated on a pseudo-ECL supply (i.e., +5 V and GND) connected to the CLOCK and CLOCK* inputs of the
Bt445. See Figure 19.
Figure 19. Frame Buffer Interface for Bt445-Generated VRAM Serial Clock and Pixel Clock
Crystal
XTAL1
XTAL2
SCLK Control
SCLK*
LD/SCLKI
IOR
IOG
IOB
SCLK
Controls
System Bus or
Graphics Pipeline
Memory
Controller
Data
VIDCLK
74
Address
VRAM
Frame
Buffer
Bt445
Serial Data
P(63–0)
VIDCLKI
VIDCLK*
SYNC*
BLANK*
Brooktree
®
APPLICATION INFORMATION
Bt445
Digital Output Port
Digital Output Port
Figure 20 shows a simplified typical connection between the Bt445, a CRT display, and a typical VGA resolution TFT flat-panel display. The VSYNC* input to
the Bt445 is not internally used; it is only synchronized with the pixel data and presented on the PVSYNC* output. This allows for variations between CRT and
flat-panel SYNC signal timings and durations. However, the horizontal line rates
and pixel rates must be identical if both displays are to be driven simultaneously.
Figure 20. Typical Connection diagram for digital Output Port to 640 x 480 TFT Flat-Panel Display
Crystal
Analog
Interface
Signals
IOR
IOG
IOB
VIDCLK
Generic Analog
Monitor
Memory
Controller
Data and
Controls
VRAM
Array
P(63–0)
PCLK
Bt445
SCLK
PBLANK*
PVSYNC*
PHSYNC*
OR[3–0]
OG[3–0]
OB[3–0]
SYNC*, BLANK*, VSYNC*, HSYNC*
Brooktree
®
Digital
Interface
Signals
Hitachi
TM26D50VC2AA
TFT Flat-Panel
75
APPLICATION INFORMATION
Bt445
Digital Output Port
Interfacing to
High-Resolution
Flat-Panel Displays
Preliminary information suggests that high-resolution flat-panel displays will
achieve the required pixel rates without using excessive clock speeds if more than
1 pixel per clock cycle is provided, in the same fashion that high-resolution Brooktree RAMDACs accept pixels at the input pixel port. The Bt445's digital output
port may operate up to 55 MHz, providing the bandwidth required, for example,
for a 1024 x 768 active matrix panel. However, to provide 2 pixels at half the clock
rate, some intervening logic may be used. Refer to Figure 21.
For proper operation, the control signals PBLANK*, PVSYNC*, and PHSYNC* should only change on an even pixel. The sample logic shown resets the
generated clock and pixel data on each edge of PBLANK*. Also note that the
clock-to-Q delay on the flip-flop, which generates LD Clock to the panel, should
be faster than the clock-to-Q delay of the pixel data registers.
Figure 21. Interfacing the Bt445 with a 1024 x 768 TFT Active Matrix Flat Panel
Bt445
PCLK
PBLANK*
PVSYNC* PHSYNC*
OR
3 2 1 0
RED
RED
GREEN
BLUE
3 2 1 0 3 2 1 0 3 2 1 0
D D D D D D D D D D D D D D D
Even Pixel Register
G
Q Q Q QQ Q QQ Q QQ Q QQ Q
3 2 1 0 3 2 1 0 3 2 1 0
RED
GREEN
BLUE
D
Q
Q
D
OG
OB
3 2 1 0
GREEN
3 2 1 0
BLUE
RED
GREEN
BLUE
3 2 1 0 3 2 1 0 3 2 1 0
D D D D D D D D D D D D
Odd Pixel Register
G
Q Q Q Q Q Q Q Q Q Q Q Q
3 2 1 0 3 2 1 0 3 2 1 0
RED
GREEN
BLUE
Q
Q
RED
GREEN
BLUE
3 2 1 0 3 2 1 0 3 2 1 0
LDClock
BLANK* VSYNC* HSYNC*
PA(RGB)[3–0]
RED
GREEN
BLUE
3 2 1 0 3 2 1 0 3 2 1 0
PB(RGB)[3–0]
1024 X 768 TFT Active Matrix
76
Brooktree
®
APPLICATION INFORMATION
Bt445
Digital Output Port
Digital Output
Connection in 8-8-8
True-Color Mode
Figure 22 shows a simplified typical connection diagram using 8-8-8 true-color
mode, to a Bt858 video encoder.
The registers are used to hold the data presented in the first half of the PCLK cycle; data presented during the second half of the PCLK cycle are held in the transparent latches, which are open during the clock high level. The configuration
shown assumes that the external CRT timing generator provides the appropriate
SYNC* and BLANK* signals at the input of the Bt445 for running the Bt858 in
master mode 0. The PCLK may need to be re-driven and/or delayed to minimize
PCLK loading and to meet hold time requirements of the Bt858.
Figure 22. Interfacing the Bt445 to a Bt858 Video Encoder
Bt445
PCLK PBLANK* PVSYNC* PHSYNC*
OR
OG
3 2 1 0
3 2 1 0
3 2 1 0
3 2 1 0
OB
3 2 1 0
3 2 1 0
3 2 1 0
3 2 1 0
D D D D D D D D
Octal Register
Q Q Q Q Q Q Q Q
7 6 5 4
D D D D D D D D
G Octal Latch
Q Q Q Q Q Q Q Q
D D D D D D D D
Octal Register
Q Q Q Q Q Q Q Q
3 2 1 0
D D D D D D D D
Octal Latch
G
Q Q Q Q Q Q Q Q
7 6 5 4
3 2 1 0
7 6 5 4
3 2 1 0
3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Clock_IN
BLANK* VSYNC* HSYNC*
Red
Green
Blue
Bt858
Brooktree
®
77
PARAMETRIC INFORMATION
DC Electrical Parameters
Table 15. Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Units
VAA
4.75
5.00
5.25
V
Ambient Operating Temperature
TA
0
+ 70
˚C
Output Load
RL
Power Supply
Reference Voltage
VREF
FS ADJUST Resistor
RSET
Junction Temperature
Tjmax
Ω
37.5
1.20
1.235
1.26
V
Ω
523
+125
˚C
Table 16. Absolute Maximum Ratings
Parameter
Symbol
Min
Typ
VAA (measured to GND)
Voltage on any Signal Pin
(1)
GND–0.5
Max
Units
7.0
V
VAA + 0.5
V
+150
˚C
Analog Output Short Circuit Duration to any Power
Supply or Common
ISC
Storage Temperature
TS
Junction Temperature
TJ
+125
°C
TSOL
260
˚C
TVSOL
220
˚C
Soldering Temperature (5 seconds, 1/4” from pin)
Vapor Phase Soldering (1 minute)
indefinite
–65
Notes: (1). This device employs high-impedance CMOS device on all signal pins. It should be handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V can induce destructive latchup.
2. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those
listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Brooktree
®
79
PARAMETRIC INFORMATION
Bt445
DC Electrical Parameters
Table 17. DC Characteristics (1 of 2)
Parameter
Analog Outputs
Resolution (each DAC)
Accuracy (each DAC)
Integral Linearity Error
Differential Linearity Error
Gray-Scale Error
Monotonicity
Coding
Symbol
Min
Typ
Max
Units
8
8
8
Bits
±1
±1
±5
LSB
LSB
% Gray Scale
IL
DL
guaranteed
Binary
Digital Inputs (except CLOCK and CLOCK*)
Input High Voltage
Input Low Voltage
Input High Current (Vin = 2.4 V)
Input Low Current (Vin = 0.4 V)
Input Capacitance (f = 1 MHz, Vin = 2.4 V)
VIH
VIL
IIH
IIL
CIN
2.0
GND–0.5
Digital Inputs with Internal Pullups (Pixel Inputs
and JTAG Pins)
Input High Voltage
Input Low Voltage
Input High Current (Vin = 2.4 V)
Input Low Current (Vin = 0.4 V)
Input Capacitance (f = 1 MHz, Vin = 2.4 V)
VIH
VIL
IIH
IIL
CIN
2.0
GND–0.5
∆VIN
VKIH
VKIL
IKIH
IKIL
CKIN
.6
VAA–1.0
GND–0.5
Pixel Clock Inputs (CLOCK, CLOCK*)
Differential Input Voltage
Input High Voltage
Input Low Voltage
Input High Current (Vin = 4.0 V)
Input Low Current (Vin = 0.4 V)
Input Capacitance (f = 1 MHz, Vin = 4.0 V)
Digital Outputs (except D(7–0), PCLK, VIDCLK*,
SCLK*)
Output High Current (Voh=2.4 V)
Output Low Current (Vol=0.4 V)
Three-state Current
Load Capacitance (includes board wiring and
capacitance at buffer input)
Digital Outputs with Internal Pullups (except
D(7–0), VIDCLK*, SCLK*)
Output High Current (Voh=2.4 V)
Output Low Current (Vol=0.4 V)
Three-state Current
Load Capacitance (includes board wiring and
capacitance at buffer input)
80
4
VAA+0.5
0.8
1
–1
10
V
V
µA
µA
pF
4
VAA+0.5
0.8
60
–60
10
V
V
µA
µA
pF
4
VAA+0.5
VAA–1.6
1
–1
10
V
V
V
µA
µA
pF
IOH
IOL
IOZ
CL
1
1
10
10
mA
mA
µA
pF
IOH
IOL
IOZ
CL
1
1
60
10
mA
mA
µA
pF
Brooktree
®
PARAMETRIC INFORMATION
Bt445
DC Electrical Parameters
Table 17. DC Characteristics (2 of 2)
Parameter
Symbol
Min
Typ
Max
Units
Digital Outputs (VIDCLK*, SCLK*)
Output High Current (Voh=2.4 V)
Output Low Current (Vol=0.4 V)
Three-state Current
Load Capacitance (includes board wiring and
capacitance at buffer input)
IOH
IOL
IOZ
CL
5
1
10
20
mA
mA
µA
pF
Digital Output (PCLK)
Output High Current (Voh=2.4 V)
Output Low Current (Vol=0.4 V)
Three-state Current
Load Capacitance (includes board wiring and
capacitance at buffer input)
IOH
IOL
IOZ
CL
1
1
60
20
mA
mA
µA
pF
0.4
10
V
V
µA
pF
Digital Outputs (D(7–0))
Output High Voltage (Ioh = –800 µA)
Output Low Voltage (Iol = 6.4 mA)
Three-state Current
Output Capacitance
Analog Outputs
Output Current
White Level Relative to Blank
White Level Relative to Black
Black Level Relative to Blank
Blank Level on IOR, IOB
Blank Level on IOG
Sync Level on IOG
LSB Size
DAC- to-DAC Matching
Output Compliance
Output Impedance
Output Capacitance (f = 1 MHz, IOUT = 0 mA)
VOH
VOL
IOZ
CDOUT
2.4
10
17.69
16.74
0.95
0
6.29
0
VOC
RAOUT
CAOUT
19.05
17.62
1.44
5
7.62
5
69.1
2
–0.6
50
13
20.40
18.50
1.90
50
8.96
50
5
+1.2
20
mA
mA
mA
µA
mA
µA
µA
%
V
kΩ
pF
Voltage Reference Input Current
IREF
100
µA
Power Supply Rejection Ratio
(COMP = 0.1 µF, f = 1 kHz)
PSRR
0.5
% / % VAA
Note: Test conditions (unless otherwise specified): “Recommended Operating Conditions” with RSET = 523 Ω, VREF
= 1.235 V. As the above parameters are guaranteed over the full temperature range, temperature coefficients are
not specified or required.
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PARAMETRIC INFORMATION
Bt445
AC Characteristics
AC Characteristics
Table 18. MPU Port
150 MHz Devices
Parameter
135 MHz Devices
Symbol
Units
Min
Typ
Max
Min
Typ
Max
R/W, C0, C1 Setup
R/W, C0, C1 Hold
1
2
0
15
0
15
ns
ns
CE* Low Time
CE* High Time
CE* ↓ to Data Driven
CE* ↓ to Data Valid
CE* ↑ to Data Three-Stated
3
4
5
6
7
50
25
7
50
25
7
ns
ns
ns
ns
ns
8(1)
9
35
3
Write Data Setup Time
Write Data Hold Time
80
25
80
25
35
3
ns
ns
Notes: (1). The parameter shown guarantees write data capture. To prevent unnecessary pixel disturbances when writing control registers, the write data should be valid throughout the CE* active duration.
Table 19. Input Pixel
150 MHz Devices
Parameter
Units
Min
LD/SCLKI
Pixel and Control Setup
Pixel and Control Hold
135 MHz Devices
Symbol
LDmax
10
11
Typ
Max
Min
Typ
75
Max
67.5
2
3
2
3
150 MHz Devices
135 MHz Devices
MHz
ns
ns
Table 20. VIDCLKI
Parameter
Symbol
Units
Min
VIDCLKI Cycle Time
VIDCLKI Pulse Width High
VIDCLKI Pulse Width Low
BLANK*, HSYNC*/SYNC*, VSYNC* Setup
BLANK*, HSYNC*/SYNC*, VSYNC* Hold
82
12
13
14
13.3
5.33
5.33
2
3
Typ
Max
Min
14.8
5.93
5.93
2
3
Typ
Max
ns
ns
ns
ns
ns
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PARAMETRIC INFORMATION
Bt445
AC Characteristics
Table 21. INPUT CLOCK
150 MHz Devices
Parameter
Units
Min
Clock Rate
Clock Cycle Time
Clock Pulse Width High
Clock Pulse Width Low
135 MHz Devices
Symbol
Fmax
15
16
17
Typ
Max
Min
Typ
150
Max
135
6.7
3
3
7.4
3.33
3.33
MHz
ns
ns
ns
Table 22. Analog Output
150 MHz Devices
Parameter
Units
Min
Analog Output Delay
Analog Output Rise/Fall
Analog Output Settling (1)
Clock/Data Feedthrough (2)
Glitch Impulse (3)
Analog Output Skew (4)
Pipeline Delay
18
19
20
Typ
Min
Typ
474
2
ns
ns
ns
pV–sec
pV–sec
ns
58
Clocks
446
mA
8
35
50
0
2
58
430
Max
25
2
8
8
IAA
Max
25
2
35
50
0
(5)
VAA Supply Current (6)
135 MHz Devices
Symbol
8
395
Notes: (1). Output settling time measured from 50% point of full-scale transition to output settling within ±1 LSB.
(2). Clock and data feedthrough is a function of the amount of edge rates, overshoot, and undershoot on the digital inputs. For this test, the TTL digital inputs have a 1 kΩ resistor to GND and are driven by 74 HC logic. Settling time does not include clock and data feedthrough.
(3). Glitch impulse includes clock and data feedthrough, –3 dB test bandwidth = 2x clock rate.
(4). Output delay time measured from 50% point of the rising clock edge to 50% point of full-scale transition.
(5). Pipeline delay is dependent upon the pixel port mux rate.
(6). At Fmax. IAA (typ) at VAA = 5.0 V, TA = 20°C. IAA (max) at VAA = 5.25 V, TA = 0°C, 4:1 mux mode.
7. Test conditions (unless otherwise specified): “Recommended Operating Conditions” with RSET = 523 Ω,
VREF = 1.235 V. TTL input values are 0–3 V, with input rise/fall times ≤ 3 ns, measured between the 10% and
90% points. ECL input values are VAA – 0.8 to VAA – 1.8 V, with input rise/fall times ≤ 2 ns, measured between the 20% and 80% points. Timing reference points at 50% for inputs and outputs. Analog output load
≤ 10 pF, D0–D7 output load ≤ 40 pF. See timing notes in Figures 22–26. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required.
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PARAMETRIC INFORMATION
AC Characteristics
Bt445
Table 23. System Clock Generation AC Timing Parameters
Parameter
Symbol
Min
Typ
Max
Units
VAA valid to VIDCLK stable
45
ms
VAA valid to CPUCLK stable
2
ms
VAA valid to MCLK stable
2
ms
15
ns
RESET* active pulse width
21
S0, S1 to RESET* setup time
22
3
ns
S0, S1 to RESET* hold time
23
10
ns
CE* rise to new VIDCLK/Pixel rate (1)
24
.008
26
ms
CE* rise to new CPUCLK rate (1)
25
0.5
1
µs
RESET* to new CPUCLK rate
26
µs
7
CPUCLK
Fmax
50
MHz
MCLK20
Fmax
20
MHz
MCLK25
Fmax
25
MHz
CPUCLK, MCLK20, MCLK25 rise/fall time
7
CPUCLK, MCLK20, MCLK25 duty cycle
40
CPUCLK, MCLK20, MCLK25 Jitter (peak to peak)
50
ns
60
400
%
ps
Notes: (1). Time to new frequencies is dependent upon the delta between the current frequency and desired new frequency. Larger changes in frequency require longer times. This specification is guaranteed by characterization and is not tested.
Table 24. PLL Clock Generation Timing Parameters
Parameter
Symbol
Min
Typ
Max
Units
Crystal/Oscillator Frequency
6
20
25
MHz
PLL M/N Generated Pixel Clock Rate
75
160
MHz
PLL M/N Generated Pixel Clock Accuracy
99
%
PLL M/N Generated Pixel Clock Jitter (peak to peak)
400
ps
Note: Above parameters apply to predivided (i.e., before applying 1/L) pixel clock generation.
84
Brooktree
®
PARAMETRIC INFORMATION
Bt445
AC Characteristics
Figure 23. MPU Read/Write Timing
1
3
RD, C[2:0]
2
4
8
CE*
9
D[7:0], WRITE
Data In (RD=0)
7
5
D[7:0], READ
Data Out (RD=0)
6
Figure 24. Input Pixel Timing
10
LD/SCLKI
11
P[63:0]
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PARAMETRIC INFORMATION
Bt445
AC Characteristics
Figure 25. Input Control Timing
13
14
10
VIDCLKI
12
11
BLANK*, VSYNC*,
HSYNC*/SYNC*
Figure 26. Video Output Timing
19
IOR
IOG
IOB
20
18
CLOCK
17
16
15
86
Brooktree
®
PARAMETRIC INFORMATION
Bt445
AC Characteristics
Figure 27. Reset, CPU Clock, and VIDCLK* Output Timing
25
CE*
24
VIDCLK*
26
CPUCLK
22
23
S1,0
21
RESET*
Table 25. Digital Pixel Output Port AC Timing Parameters
Parameter
Symbol
Min
PCLK Cycle Time (1)
4-4-4 Mode
8-8-8 Mode
28
PCLK Edge to Data, Control Delay
29
PCLK Edge to Data, Control Hold
30
8
PCLK Pulse High Duty Cycle
31
40
Typ
Max
Units
ns
18.2
36.4
18
ns
ns
60
%
PCLK, VIDCLK*, SCLK* rise/fall time
3
ns
PSYNC*, PBLANK*, PVSYNC*, PHSYNC* rise/fall time
7
ns
O(R,G,B)(3–0) cycle time
O(R,G,B)(3–0) rise/fall time
36.4
ns
7
ns
Notes: (1). The cycle time parameters apply only when the PCLK output is enabled.
2. All digital pixel and control outputs should be redriven through a non-inverting buffer prior to connection to the
next stage.
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®
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PARAMETRIC INFORMATION
Bt445
AC Characteristics
Figure 28. Pixel Output Port Timings
31
28
PCLK
29
29
OR[3:0]
OG[3:0]
OB[3:0]
30
30
PSYNC*, PBLANK*,
PHSYNC*, PVSYNC*
88
Brooktree
®
PARAMETRIC INFORMATION
Bt445
Package Drawing
Package Drawing
160-pin Plastic Quad Flatpack (PQFP)
Brooktree
®
89
PARAMETRIC INFORMATION
Bt445
Revision History
Revision History
Revision
A
Advance Release
B
PLL adjustments and register redefinitions.
C, D
90
Change From Previous Revision
Corrected the Ordering Information model number from KPF to KHF. PLL pixel frequency increased to 150
MHz. Eliminated the 1:1 mux rate support throughout document. Address Register Table revised.
E
In Table 11, changed Pixel Frequency Range to 110–119. In AC Characteristics, changed Symbol 16 and
17’s value for all three speed grades
F
In Circuit Description section, expanded Multiplex Rate Selection and Pixel Output Interface information. In
Application Information section, added buffers to Figure 22 Interfacing the Bt445 to a Bt858 Video Encoder.
In Parametric Information section, removed Output Short Circuit Current from DC Characteristics, added
pipleline delay note to Table 22 Analog Output, and added frequency note to Table 23 System Clock Generation AC Timing Parameters. Removed 110 MHz operation information throughout document.
Brooktree
®
Brooktree
®
Brooktree Corporation
9868 Scranton Road
San Diego, CA 92121-3707
(619) 452-7580
1(800) 2-BT-APPS
FAX: (619) 452-1249
Internet: apps@brooktree.com
L445001 Rev. F
printed on
recycled paper