ETC HT24LC08-8DIP-A

HT24LC08
CMOS 8K 2-Wire Serial EEPROM
Features
· Operating voltage: 2.2V~5.5V
· Partial page write allowed
· Low power consumption
· 16-byte Page Write Mode
- Operation: 5mA max.
- Standby: 5mA max.
· Write operation with built-in timer
· Hardware controlled write protection
· Internal organization: 1024´8
· 40-year data retention
· 2-wire Serial Interface
· 106 rewrite cycles per word
· Write cycle time: 5ms max.
· Commerical temperature range (0°C to +70°C)
· Automatic erase-before-write operation
· 8-pin DIP/SOP package
General Description
The HT24LC08 is an 8K-bit serial read/write non-volatile
memory device using the CMOS floating gate process.
Its 8192 bits of memory are organized into 1024 words
and each word is 8 bits. The device is optimized for use
in many industrial and commercial applications where
low power and low voltage operation are essential. Up
to two HT24LC08 devices may be connected to the
same 2-wire bus. The HT24LC08 is guaranteed for 1M
erase/write cycles and 40-year data retention.
Block Diagram
Pin Assignment
I/O
C o n tro l
L o g ic
S C L
S D A
H V P u m p
X
D
M e m o ry
C o n tro l
L o g ic
W P
A 0
1
8
V C C
A 1
2
7
W P
A 2
3
6
S C L
V S S
4
5
S D A
H T 2 4 L C 0 8
8 D IP -A /S O P -A
E E P R O M
A rra y
E
C
P a g e B u ffe r
Y D E C
A d d re s s
C o u n te r
A 0 ~ A 2
S e n s e A M P
R /W C o n tro l
V C C
V S S
Pin Description
Pin Name
A0~A2
I/O
I
Description
Address input
SDA
I/O
SCL
I
Serial clock input
WP
I
Write protect
VSS
¾
Negative power supply, ground
VCC
¾
Positive power supply
Rev. 1.10
Serial data
1
March 27, 2002
HT24LC08
Absolute Maximum Ratings
Operating Temperature (Commercial) ........................................................................................................ 0°C to 70°C
Storage Temperature ............................................................................................................................ -50°C to 125°C
Applied VCC Voltage with Respect to VSS ............................................................................................... -0.3V to 6.0V
Applied Voltage on any Pin with Respect to VSS ........................................................................................................ -0.3V to VCC+0.3V
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol
Ta=0°C to 70°C
Test Conditions
Parameter
VCC
Conditions
¾
Min.
Typ.
Max.
Unit
2.2
¾
5.5
V
VCC
Operating Voltage
¾
ICC1
Operating Current
5V
Read at 100kHz
¾
¾
2
mA
ICC2
Operating Current
5V
Write at 100kHz
¾
¾
5
mA
VIL
Input Low Voltage
¾
¾
-1
¾
0.3VCC
V
VIH
Input High Voltage
¾
¾
0.7VCC
¾
VCC+0.5
V
VOL
Output Low Voltage
2.4V
IOL=2.1mA
¾
¾
0.4
V
ILI
Input Leakage Current
5V
VIN=0 or VCC
¾
¾
1
mA
ILO
Output Leakage Current
5V
VOUT=0 or VCC
¾
¾
1
mA
ISTB1
Standby Current
5V
VIN=0 or VCC
¾
¾
5
mA
2.4V
VIN=0 or VCC
¾
¾
4
mA
Input Capacitance (See Note)
¾
f=1MHz 25°C
¾
¾
6
pF
Output Capacitance (See Note)
¾
f=1MHz 25°C
¾
¾
8
pF
ISTB2
CIN
COUT
Standby Current
Note: These parameters are periodically sampled but not 100% tested
A.C. Characteristics
Symbol
Ta=0°C to 70°C
Parameter
Remark
Standard Mode*
VCC=5V±10%
Min.
Max.
Min.
Max.
Unit
fSK
Clock Frequency
¾
¾
100
¾
400
kHz
tHIGH
Clock High Time
¾
4000
¾
600
¾
ns
tLOW
Clock Low Time
¾
4700
¾
1200
¾
ns
tR
SDA and SCL Rise Time
Note
¾
1000
¾
300
ns
tF
SDA and SCL Fall Time
Note
¾
300
¾
300
ns
tHD:STA
START Condition Hold Time
After this period the first
clock pulse is generated
4000
¾
600
¾
ns
tSU:STA
START Condition Setup Time
Only relevant for repeated
START condition
4000
¾
600
¾
ns
tHD:DAT
Data Input Hold Time
¾
0
¾
0
¾
ns
tSU:DAT
Data Input Setup Time
¾
200
¾
100
¾
ns
tSU:STO
STOP Condition Setup Time
¾
4000
¾
600
¾
ns
Rev. 1.10
2
March 27, 2002
HT24LC08
Symbol
Parameter
Standard Mode*
Remark
VCC=5V±10%
Unit
Min.
Max.
Min.
Max.
¾
¾
3500
¾
900
ns
4700
¾
1200
¾
ns
¾
100
¾
50
ns
¾
5
¾
5
ms
tAA
Output Valid from Clock
tBUF
Bus Free Time
Time in which the bus
must be free before a new
transmission can start
tSP
Input Filter Time Constant
(SDA and SCL Pins)
Noise suppression time
tWR
Write Cycle Time
¾
Notes: These parameters are periodically sampled but not 100% tested
* The standard mode means VCC=2.2V to 5.5V
For relative timing, refer to timing diagrams
Functional Description
· Serial clock (SCL)
· Start condition
The SCL input is used for positive edge clock data into
each EEPROM device and negative edge clock data
out of each device.
A high-to-low transition of SDA with SCL high is a start
condition which must precede any other command
(refer to Start and Stop Definition Timing diagram).
· Serial data (SDA)
· Stop condition
The SDA pin is bidirectional for serial data transfer.
The pin is open drain driven and may be write-OR with
any number of other open drain or open collector devices.
A low-to-high transition of SDA with SCL high is a stop
condition. After a read sequence, the stop command
will place the EEPROM in a standby power mode (refer to Start and Stop Definition Timing Diagram).
· A0, A1, A2
· Acknowledge
The HT24LC08 uses the A2 input for hard wire addressing and a total of two 8K devices may be addressed on a single bus system. The A0 and A1 pins
have no connection.
All addresses and data words are serially transmitted
to and from the EEPROM in 8-bit words. The
EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock
cycle.
· Write protect (WP)
D a ta a llo w e d
to c h a n g e
The HT24LC08 has a write protect pin that provides
hardware data protection. The write protect pin allows
normal read/write operations when the connection is
grounded. When the write protect pin is connected to
VCC, the write protection feature is enabled and operates as shown in the following table.
WP Pin Status
S D A
S C L
S ta rt
c o n d itio n
Protect Array
At VCC
Full Array (8K)
At VSS
Normal Read/Write Operations
S to p
c o n d itio n
Device addressing
The 8K EEPROM device requires an 8-bit device address word following a start condition to enable the chip
for a read or write operation. The device address word
consist of a mandatory one, zero sequence for the first
four most significant bits (refer to the diagram showing
the Device Address). This is common to all the
EEPROM device.
Memory organization
Internally organized with 1024 8-bit words, the 8K requires a 10-bit data word address for random word addressing.
Device operations
The 8K EEPROM uses the A2 device address bit with
the next two bits for memory page addressing. The A2
bit must compare its corresponding hard-wired input
pin. The A1 and A0 pins have no connection.
· Clock and data transition
Data transfer may be initiated only when the bus is not
busy. During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
data line while the clock line is high will be interpreted
as a START or STOP condition.
Rev. 1.10
A d d re s s o r
a c k n o w le d g e
v a lid
These page addressing bits on the 8K device should be
considered the most significant bits of the data word ad3
March 27, 2002
HT24LC08
cremented following the receipt of each data word.
The higher data word address bits are not incremented, retaining the memory page row location.
dress which follows. The A0, A1 and A2 pins have no
connection.
The 8th bit device address is the read/write operation
select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
· Acknowledge polling
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master
sending a start condition followed by the control byte
for a write command (R/W=0). If the device is still busy
with the write cycle, then no ACK will be returned. If
the cycle is completed, then the device will return the
ACK and the master can then proceed with the next
read or write command.
If the comparison of the device address succeed the
EEPROM will output a zero at ACK bit. If not, the chip will
return to a standby state.
1
0
1
0
A 2
A 1
A 0
R /W
D e v ic e A d d r e s s
Write operations
· Byte write
A write operation requires an 8-bit data word address
following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will
again respond with a zero and then clock in the first
8-bit data word. After receiving the 8-bit data word, the
EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the
write sequence with a stop condition. At this time the
EEPROM enters an internally-timed write cycle to the
nonvolatile memory. All inputs are disabled during this
write cycle and EEPROM will not respond until write is
complete (refer to Byte write timing).
S e n d W r ite C o m m a n d
S e n d S to p C o n d itio n
to In itia te W r ite C y c le
S e n d S ta rt
S e n d C o n tro l B y te
w ith R /W = 0
· Page write
The 8K EEPROM is capable of a 16-byte page write.
A page write is initiated in the same way as a byte
write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges the receipt of the first
data word, the microcontroller can transmit up to 15
more data words. The EEPROM will respond with a
z e ro a f t e r e a c h d a t a w o r d r e c e i v e d . T h e
microcontroller must terminate the page write sequence
with a stop condition (refer to Page write timing).
The data word address lower four bits are internally in-
N o
Y e s
N e x t O p e r a tio n
Acknowledge polling flow
W o rd a d d re s s
D e v ic e a d d r e s s
S D A
(A C K = 0 )?
D A T A
A 2 A 1 A 0
S
S ta rt
P
R /W
A C K
A C K
A C K
S to p
Byte write timing
D e v ic e a d d r e s s
S D A
W o rd a d d re s s
D A T A n + x
P
S
S ta rt
A C K
A C K
A C K
Page write timing
Rev. 1.10
D A T A n + 1
D A T A n
4
A C K
S to p
March 27, 2002
HT24LC08
· Write protect
· Random read
The HT24LC08 can be used as a serial ROM when
the WP pin is connected to VCC . Programming will be
in h ib i t ed and t he ent i r e m em or y w i l l b e
write-protected.
A random read requires a dummy byte write sequence
to load in the data word address which is then clocked
in and acknowledged by the EEPROM. The
microcontroller must then generate another start condition. The microcontroller now initiates a current address read by sending a device address with the
read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the
data word. The microcontroller does not respond with
a zero but does generate a following stop condition
(refer to Random read timing).
· Read operations
Read operations are initiated in the same way as write
operations with the exception that the read/write select bit in the device address word is set to one. There
are three read operations: current address read, random address read and sequential read.
· Current address read
· Sequential read
The internal data word address counter maintains the
last address accessed during the last read or write operation, incremented by one. This address stays valid
between operations as long as the chip power is maintained. The address roll over during read from the last
byte of the last memory page to the first byte of the first
page. The address roll over during write from the last
byte of the current page to the first byte of the same
page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by
the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond
with an input zero but does generate a following stop
condition (refer to Current read timing).
Sequential reads are initiated by either a current address read or a random address read. After the
microcontroller receives a data word, it responds with
an acknowledgment. As long as the EEPROM receives an acknowledgment, it will continue to increment the data word address and serially clock out
sequential data words. When the memory address
limit is reached, the data word address will roll over
and the sequential read continues. The sequential
read operation is terminated when the microcontroller
does not respond with a zero but does generate a following stop condition.
D e v ic e a d d r e s s
S D A
D A T A
S to p
A 2 A 1 A 0
S
S ta rt
P
N o A C K
A C K
Current read timing
W o rd a d d re s s
D e v ic e a d d r e s s
S
S D A
A 2
S
A 1 A 0
S ta rt
D A T A
D e v ic e a d d r e s s
P
A C K
S ta rt
A C K
S to p
A C K
N o A C K
Random read timing
D e v ic e a d d r e s s
S D A
D A T A n
D A T A n + 1
P
S
S ta rt
D A T A n + x
A C K
A C K
A C K
S to p
Sequential read timing
Rev. 1.10
5
March 27, 2002
HT24LC08
Timing Diagrams
tF
tR
S C L
tS
S D A
U :S T A
tS
tL
O W
tH
D :S T A
tH
IG H
tH
tS
D :D A T
U :D A T
P
tA
S D A
A
V a lid
O U T
tS
U :S T O
tB
U F
V a lid
S C L
S D A
8 th b it
A C K
W o rd n
tW
S to p
c o n d itio n
R
S to p
c o n d itio n
Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the valid start condition of sequential command.
Rev. 1.10
6
March 27, 2002
HT24LC08
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Copyright Ó 2002 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most
up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.10
7
March 27, 2002