XPressArray 0.18µ Hybrid Gate Array 1.0 Key Features • Supports LVTTL, LVCMOS, PCI, PCI-X, AGP-2X, HSTL, SSTL, GTL/+, LVPECL, LVDS, BLVDS • 1.8V, 2.5V and 3.3V capable I/O • True 3.3V and 5V tolerance with no external resistor necessary • Up to 832 user I/Os • Comprehensive clock management circuitry • Up to 12 digital DLLs and 4 PLLs • Variety of package options • Integrated scan-test and JTAG support for high-fault coverage • Next-generation 0.18µ hybrid gate array • Platform for high-performance 1.8V ASICs and FPGA-toASIC conversions • NRE and production cost savings • Significant time-to-market advantages • Drop-in replacement for cost-reducing Xilinx Virtex-E and Altera APEX-E designs • 47K to 2.6M ASIC gates, 240K to 11M FPGA system gates • 250MHz system, 350MHz local clock speeds • Low power consumption (0.020µW/MHz/gate) • 23Kbits to 1.4Mbits of embedded configurable memory • Single-port/dual-port, RAM/CAM, initializable • Flexible I/O technology • Configurable signal, core and I/O power supply pad locations 2.0 Product Description with 1.8V, 2.5V, 3.3V and 5.0V I/O schemes. High fault coverage is provided through integrated scan-test and JTAG support. Targeted at medium-density, high-speed, 1.8V ASIC applications and high-density FPGA-to-ASIC conversions, the XPressArray 0.18µ hybrid gate array is an innovative next-generation technology platform that reduces time-to-market for system-onchip (SoC) applications while delivering significant NRE and unit cost savings. For FPGA conversions rapid access to XPressArray technology can be achieved via AMI Semiconductor’s NETRANS® FPGA-toASIC design flow. Alternatively, the availability of XPressArray synthesis libraries for leading commercial synthesizers allows conversion of FPGA designs to ASICs by simply re-targeting from an FPGA library to an XPressArray library. XPressArray offers a true drop-in replacement for Xilinx Virtex-E and Altera APEX-E FPGAs, making it the industry’s lowest cost ASIC conversion solution. The result is a simplified route to cost reductions for OEMs looking to combine the flexibility of FPGA prototyping with a path to ASICs for final production. Operating with system clock speeds up to 250MHz and local clocks up to 350MHz and available in a variety of package options, XPressArray 0.18µ devices deliver high-performance, low power ASIC solutions with densities to 2.6M ASIC gates. Embedded configurable memory ranges from 23Kbits to 1.4Mbits, while flexible I/O technology includes support for a comprehensive array of common standards and compatibility AMI Semiconductor www.amis.com 1 XPressArray 0.18µ Hybrid Gate Array Table 1: XPressArray 0.18µ Hybrid Gate Array Family XPressArray Base XP164E XP220E XP270E XP368E XP440E XP560E XP704E XP832E System Gates1 240K 616K 988K 1972K 3048K 4970K 7942K 11100K Usable ASIC Gates2 44K 136K 226K 456K 718K 1181K 1895K 2664K Usable RAM Bits3 23K 71K 119K 240K 378K 622K 998K 1403K DLL 4 4 4 8 8 8 12 12 PLL 2 2 2 2 2 4 4 4 Bond Pads4 164 220 270 368 440 560 704 8325 (1) Equivalent FPGA system gates. (4) Total combined signal, power/ground and test bond pads. (2) Usable 2-NAND gate array equivalent gates, assumes full RAM utilization. (5) Flip-chip power pads not included in bond pad count. (3) Usable 2RW RAM bits, assumes full logic utilization. Package offerings include traditional plastic TQFP/PQFP, as well as plastic and super BGA in 0.80mm, 1.00mm and 1.27mm pitches. Traditional wire-bond technology is used. Flip-chip technology is used on the largest array. Because XPressArray devices consume significantly less power than equivalent FPGAs, lower cost plastic packaging can be used in most cases. Table 2 shows the supported package configurations. Packaging options exist to optimize individual conversions. Table 2: XPressArray Package Options XPressArray Base XP164E XP220E XP270E XP368E XP440E XP560E XP704E XP832E CS F T Q PQ/Q FG F BG B BG FG F BG B F FG FG FG FG F F/CG 144 144 144 208 240 256 324 352 356 432 456 484 560 652 672 676 680 860 900 1020 1156 * * * * * AMI Semiconductor www.amis.com * * * * * * * * * * * * * * * * * * * * * * * * * * * Supported package configuration Packaging option 2 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * XPressArray 0.18µ Hybrid Gate Array 3.0 The Advantages of XPressArray Access to XPressArray devices is via FPGA netlist conversion using AMI Semiconductor's NETRANS FPGA-to-ASIC flow. Or the re-synthesis route can be employed using AMI Semiconductors RTL hand-off flow. FPGA devices are using ever smaller process geometries in the quest for higher density, higher performance and lower power. A consequence of this trend is that operating voltages have dropped with each new FPGA process introduction. To match operating voltage and still provide better performance and power consumption characteristics, an equivalent ASIC needs to be fabricated in a similar process technology. Another consequence of this process trend is that ASIC mask tooling costs have exploded. As a result, non-recurring engineering (NRE) charges for cell-based ASIC designs have priced out all but the highest volume applications. The XPressArray architecture offers a unique solution to the challenges of maintaining FPGA process compatibility while delivering ASIC technology with reasonable NREs and low piece price. Compared to equivalent FPGAs, XPressArray devices operate at the same low voltage, offer higher densities, better performance and consume less power. Figure 1 compares volume pricing for FPGA, cell-based ASIC and XPressArray devices. Figure 2 compares power consumption of these devices. Fig. 1: Price vs. Volume (Amortized NRE) XPressArray provides a FPGA conversion platform combining advanced process capability with virtually all the features of the Xilinx Virtex-E and Altera APEX-E devices. Support for a comprehensive array of I/O standards, abundant configurable memory, high-density logic and advanced high-performance clock management and frequency synthesis circuits round out the offering. XPressArray devices can be fabricated as pin-forpin compatible FPGA drop-in replacements. Alternatively, multiple FPGAs can be combined into one XPressArray device, or die and package configurations can be optimized for specific requirements. 0.18µ FPGA 0.18µ XPressArray 0.18µ Standard Cell Fig. 2: XPressArray power consumption 4.0 XPressArray Architecture Figure 3 shows the XPressArray device organization based around a sea-of-gates architecture with embedded RAM, DLLs, PLLs and support for a full compliment of I/O standards. Fig. 3: XPressArray Architecture AMI Semiconductor www.amis.com 3 XPressArray 0.18µ Hybrid Gate Array 5.0 I/O Description High-speed serial I/O operating at up to 622Mbps is supported with LVDS transceivers in conjunction with DLL/PLL clock management circuits and DDR (double data rate) circuitry. The XPressArray I/O ring is composed of uniform I/O pad sites. Each pad site may be customized to operate as a signal pad, or a power supply pad for either the core or the I/O ring. The I/O power ring may be cut into virtually an unlimited number of segments. In most cases, the I/O power ring is divided into eight segments, making it compatible with the FPGA products and power supply rings built into the packages. Signal pads are available for a wide variety of standards as listed in Table 3. Signal pads operate at 1.8V, 2.5V and 3.3V. In addition 3.3V and 5V tolerant pads are also available. Differential signaling standards typically require two pad sites. Signaling standards requiring a reference voltage typically share a common reference voltage within an I/O power ring segment, with the reference voltage being supplied through a pad from an off-chip source. Table 3: Supported I/O Standards I/O Standards LVTTL LVCMOS33 LVCMOS25 LVCMOS18 PCI33_33 PCI66 PCI-X AGP-2X ATA33 GTL GTL+ CTT SSTL-3 Type I SSTL-3 Type II SSTL-2 Type I SSTL-2 Type II HSTL Type I HSTL Type II HSTL Type III HSTL Type IV LVPECL33 LVPECL25 Xilinx LVDS LVDS33 LVDS25 LVDS18 Xilinx LVDS18 BLVDS33 BLVDS25 Type1 S S S S S S S S S V V V V V V V V V V V V V D D D D D D D VddIO 3.3 3.3 2.5 1.8 3.3 3.3 3.3 3.3 3.3 N/A N/A 3.3 3.3 3.3 2.5 2.5 1.5 1.5 1.5 1.5 3.3 2.5 2.5 3.3 2.5 1.8 1.8 3.3 2.5 Notes 1-24mA, 5V-tolerant 1-24mA, 5V-tolerant 1-16mA, 3.3V/5V-tolerant (1-12mA) 1-24mA, 2.5V/3.3V-tolerant (1-8mA) Standard; 5V-tolerant requires external diode Standard; 5V-tolerant requires external diode Contact factory for availability Output only Input only; does not meet EIA/TAI LVDS spec I/O Types: S: Single ended input and outputs. V: Inputs are differential with respect to an external voltage reference, may share a reference pin. Outputs are single ended. D: Fully differential input and output, requires two signal pins. 1 AMI Semiconductor www.amis.com 4 XPressArray 0.18µ Hybrid Gate Array 6.0 Memory Description The XPressArray architecture supports abundant embedded RAM. Each RAM is individually port configurable as 512x1, 256x2, 128x4, 64x8 and 32x16 as shown in table 4. XPressArray embedded RAM blocks may be configured as single-port (1RW), dual-port (1R1W) or true dual-port (2RW). Synchronous and asynchronous modes are available. Synchronous-write asynchronous-read mode is supported for 1RW and 1R1W configurations. Each RAM bit is initializable by a late metal mask option. Table 4: Available RAM Configurations I/O Standard RAM512X1_RW RAM512X1_2RW RAM512X1_256X2_2RW RAM512X1_128X4_2RW RAM512X1_64X8_2RW RAM512X1_32X16_2RW Port A Width 1 1 1 1 1 1 Port B Width N/A 1 2 4 8 16 The XPressArray memories also supports CAM by combining logic and embedded RAM functions together to form singlecycle, stackable binary or ternary 32x4 CAM blocks. RAM256X2_1RW RAM256X2_2RW RAM256X2_128X4_2RW RAM256X2_64X8_2RW RAM256X3_32X16_2RW 2 2 2 2 2 N/A 2 4 8 16 RAM128X4_1RW RAM128X4_2RW RAM128X4_64X8_2RW RAM128X4_32X16_2RW 4 4 4 4 N/A 4 8 16 RAM64X8_1RW RAM64X8_2RW RAM64X8_32X16_2RW 8 8 8 N/A 8 16 RAM32X16_2RW RAM32X16_2RW 16 16 N/A 16 7.0 Delay-Locked Loop (DLL) Description Fig. 4: DLL XPressArray devices employ clock tree synthesis to route a virtually unlimited number of clock and reset signals to the flip-flop groups. Synthesized clock trees deliver high speed clock signals with minimal skew and power. DLLs are embedded into the XPressArray bases to minimize clock insertion delay, perform limited clock frequency synthesis and generate phase taps. Applications include double data rate (DDR) serial I/O and clock data recovery (CDR). 8.0 Phase-Locked Loop (PLL) Description Figure 5 shows the general purpose PLL configuration. All dividers have a range of 1 to 2049. In normal mode, the PLL performs classical “M over N” frequency synthesis application. When the output frequency is an integer multiple or division of the input frequency precise phase control allows fine adjustment of the phase relationship of the output to the PLLs are embedded into the XPressArray bases to perform advanced clock frequency synthesis operations, minimize clock insertion delay and generate phase taps. Applications include double data rate (DDR) serial I/O and clock data recovery (CDR). Each PLL can be configured as a general purpose or LVDS PLL. AMI Semiconductor www.amis.com 5 XPressArray 0.18µ Hybrid Gate Array Fig. 5: General Purpose PLL REFCLK ÷N Phase Compare ÷A FOUTA ÷B FOUTB Figure 9 shows the general purpose PLL used in clock tree mode. This mode supports integer multiply or divide for both outputs. Locations A and B are phase matched, C is phase controlled with respect to D. Phase Shift ÷M Fig. 9: General Purpose PLL in Clock Tree Mode FBFCLK LOCK General Purpose PLL B PAD ÷N ÷A A Phase Compare Phase Shift Fig. 6: General Purpose PLL in Normal Mode ÷B ÷N B ÷A A Phase Compare D General Purpose PLL Phase Shift ÷B PAD C ÷M Figure 10 shows the LVDS PLL configuration which supports high-speed serial I/O applications. The reference divider supports a range of 1 to 2049 while the feedback divider is limited to a range of 1 to 33. General Purpose PLL input. In this example, locations B and C are phase controlled with respect to A. The phase relationship of A and D is inferred. Fig. 10: LVDS PLL ÷N RFFCLK Figure 7 shows the general purpose PLL used in zero delay mode. This mode supports integer multiply or divide for both outputs. Locations A and B are phased matched. ÷M DFF ÷N ÷A A Phase Compare FOUT90 FOUT180 FOUT270 FOUT360 Phase Compare Fig. 7: General Purpose PLL in Zero Delay Mode PAD C ÷M DFF PAD DFF D LVDS PLL LOCK C Phase Shift ÷B PAD B The PLL contains integral test hardware to facilitate silicon testing and in-circuit PLL tuning. The PLL requires a dedicated power and ground pad pair. ÷M General Purpose PLL Figure 8 shows the general purpose PLL used in external feedback mode. This mode supports integer multiply or divide for both outputs. Locations A and B are phase matched. Fig. 8: General Purpose PLL in External Feedback Mode DFF PAD ÷N A ÷A Phase Compare C Phase Shift ÷B PAD ÷M General Purpose PLL PAD B AMI Semiconductor www.amis.com 6 XPressArray 0.18µ Hybrid Gate Array 9.0 NETRANS ® Conversion Flow Xilinx, Virtex and Altera APEX mapping libraries are fully verified by a process which includes formal verification of each primitive function. Support is also available for other FPGA device from Xilinx, Altera, Actel, Lattice, etc. Support for ASIC conversions from LSI, NEC, Toshiba, etc. to AMIS ASICs is available also. XPressArray devices are fully supported by AMI Semiconductor's proven NETRANS flow. AMIS has over 15 years experience using NETRANS to convert over 1500 FPGA and third party ASIC designs to AMIS ASICs. Inputs to the NETRANS flow include the FPGA or ASIC netlist, test benches and timing constraints. Over 70 different device types and netlist formats are supported. 10.0 RTL Hand-Off Flow check, synthesize, layout and achieve timing closure on your design. Typically if Synplify Pro was used for the FPGA design, then Synplify ASIC will be used for the ASIC design. Likewise is FPGA Express was used, then Design Compiler is used for the ASIC re-synthesis. XPressArray synthesis libraries are available for leading commercial synthesizers, including Synplicity Synplify ASIC and Synopsys Design Compiler. With the RTL Hand-Off flow, you can submit your RTL description, scripts and timing constraints to AMIS. AMIS will 11.0 Electrical Specifications Absolute Maximum Ratings DC Characteristics Symbol VDDINT Parameter Internal Supply Voltage Min. -0.3 Max. 2.2 Units V VDDIO I/O Supply Voltage -0.3 4.0 V VREF Input Reference Voltage -0.3 4.0 V VIN, VOUT DC Input, Output -0.3 4.0 V TJ Junction Temperature -55 125 °C TL Lead Temperature (Soldering 10s) 250 °C Symbol ICCINT ICCIO IL CIN Parameter Quiescent VDDINT supply current Quiescent VDDIO supply current Input or output leakage current Input capacitance Min. 1.62 Max. 1.98 Units V VDDIO 1.2 3.6 V I/O Supply Voltage Parameter General Purpose Operation Operating Modes VCO Frequency Range PFD Frequency Range Max Input Frequency Reference Divider Feedback Divider Post Dividers Phase Shift Resolution Phase Shift Range Available Outputs DLL Specifications Parameter Low Frequency Version Frequency Range Available Outputs Clock Doubler Range Clock Divider Range High Frequency Version Frequency Range Available Outputs Clock Divider Range Overall Characteristics Operating Voltage Temperature Jitter Phase offset between outputs AMI Semiconductor www.amis.com Max. Units µA µA µA pF PLL Specifications Recommended Operating Conditions Symbol Parameter VDDINT Internal Supply Voltage Min. Value 20-200MHz CLK90, CLK180, CLK270, CLK360, CLKDV, CLK2X 40-400MHz 1.5-16 in 0.5 steps, 16-32 in 1.0 steps LVDS Operation VCO Frequency Range PFD Frequency Range Max Input Frequency Reference Divider Feedback Divider Post Dividers Available Outputs 200-350MHz CLK180, CLK360, CLKDV 2-32 in 1.0 steps 1.8V ± 5% Commercial ±85ps cycle-to-cycle 200ps estimated Overall Characteristics Operating Voltage Temperature Jitter 7 Value • Normal with Phase Shift • Zero Delay Buffer • External Feedback • Clock Tree 200-500MHz 1-50MHz 500MHz 1-2049 1-2049 1-2049 1/[FVCO*5] 0-360O FOUTA, FOUTB 200-800MHz 1-50MHz 500MHz 1-2049 1-33 1, with 4 quadrature outputs FOUT90, FOUT180, FOUT270, FOUT360 1.8V +/- 5% Commercial +/-100ps peak-to-peak XPressArray 0.18µ Hybrid Gate Array 12.0 FPGA Cross Reference Xilinx Device XPressArray Device Altera Device XPressArray Device XCV50E-CS144 XCV50E-PQ240 XCV50E-FG256 XCV100E-CS144 XCV100E-PQ240 XCV100E-FG256 XCV100E-BG352 XCV200E-CS144 XCV200E-PQ240 XCV200E-FG256 XCV200E-BG352 XCV200E-FG456 XCV300E-PQ240 XCV300E-FG256 XCV300E-BG352 XCV300E-BG432 XCV300E-FG456 XCV400E-PQ240 XCV400E-BG432 XCV400E-BG560 XCV400E-FG676 XCV600E-HQ240 XCV600E-BG432 XCV600E-BG560 XCV600E-FG676 XCV600E-FG680 XCV600E-FG900 XCV1000E-HQ240 XCV1000E-BG560 XCV1000E-FG680 XCV1000E-FG860 XCV1000E-FG900 XCV1000E-FG1156 XCV1600E-BG560 XCV1600E-FG680 XCV1600E-FG860 XCV1600E-FG900 XCV1600E-FG1156 XCV2000E-BG560 XCV2000E-FG680 XCV2000E-FG860 XCV2000E-FG1156 XCV2600E-FG1156 XCV3200E-CG1156 XP164E-CSP144 * XP270E-PQFP240 XP270E-PBGA256 XP164E-CSP144 * XP270E-PQFP240 XP270E-PBGA256 XP270E-SBGA352 XP164E-CSP144 * XP270E-PQFP240 XP270E-PBGA256 XP368E-SBGA352 XP440E-PBGA456 XP270E-PQFP240 XP270E-PBGA256 XP368E-SBGA352 XP440E-PBGA432 XP440E-PBGA456 XP270E-PQFP240 XP440E-PBGA432 XP560E-SBGA560 XP560E-PBGA676 XP220E-PQFP240 XP440E-PBGA432 XP560E-SBGA560 XP704E-PBGA676 XP704E-FBGA680 * XP560E-FBGA900 * XP270E-PQFP240 XP560E-SBGA560 XP704E-FBGA680 * XP704E-FBGA860 * XP704E-FBGA900 * XP704E-FBGA1156 * XP560E-SBGA560 XP704E-FBGA680 * XP704E-FBGA860 * XP832E-FBGA900 * XP832E-FBGA1156 * XP560E-SBGA560 XP704E-FBGA680 * XP704E-FBGA860 * XP832E-FBGA1156 * XP832E-FBGA1156 * XP832E-FBGA1156 * EP20K30E-F144 EP20K30E-T144 EP20K30E-Q208 EP20K30E-F324 EP20K60E-F144 EP20K60E-T144 EP20K60E-Q208 EP20K60E-Q240 EP20K60E-F324 EP20K60E-B356 EP20K100E-F144 EP20K100E-T144 EP20K100E-Q208 EP20K100E-Q240 EP20K100E-F324 EP20K100E-B356 EP20K160E-T144 EP20K160E-Q208 EP20K160E-Q240 EP20K160E-R240 EP20K160E-B356 EP20K160E-F484 EP20K200E-Q208 EP20K200E-Q240 EP20K200E-B356 EP20K200E-F484 EP20K200E-B652 EP20K200E-F672 EP20K300E-Q240 EP20K300E-B652 EP20K300E-F672 EP20K400E-B652 EP20K400E-F672 EP20K600E-B652 EP20K600E-F672 EP20K600E-F1020 EP20K1000E-B652 EP20K1000E-F672 EP20K1000E-F1020 EP20K1500E-B652 EP20K1500E-F1020 XP164E-FBGA144 * XP164E-LQFP144 XP220E-PQFP208 XP220E-FBGA324 * XP164E-FBGA144 * XP164E-LQFP144 XP220E-PQFP208 XP220E-PQFP240 XP270E-FBGA324 * XP270E-PBGA356 XP164E-FBGA144 * XP164E-LQFP144 XP220E-PQFP208 XP270E-PQFP240 XP368E-FBGA324 * XP368E-PBGA356 XP164E-LQFP144 XP220E-PQFP208 XP270E-PQFP240 XP270E-PQFP240 XP440E-PBGA356 XP440E-FBGA484 * XP220E-PQFP208 XP270E-PQFP240 XP440E-PBGA356 XP560E-FBGA484 * XP560E-PBGA652 * XP560E-FBGA672 * XP270E-PQFP240 XP560E-PBGA652 * XP560E-FBGA672 * XP704E-PBGA652 * XP704E-FBGA672 * XP704E-PBGA652 * XP704E-FBGA672 * XP704E-FBGA1020 * XP704E-PBGA652 * XP704E-FBGA672 * XP832E-FBGA1020 * XP704E-PBGA652 * XP832E-FBGA1020 * * Consult factory. * Consult factory. AMI Semiconductor www.amis.com 8