ETC AHA3210B

Product Specification
AHA3210B
10 MBytes/sec DCLZ
Data Compression Coprocessor IC
2365 NE Hopkins Court
Pullman, WA 99163-5601
tel: 509.334.1000
fax: 509.334.9000
sales@aha.com
www.aha.com
advancedhardwarearchitectures
PS3210B-1299
advancedhardwarearchitectures
Table of Contents
1.0 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.0 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1 Port A and B Port Data Bus Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1.1 Dual Data Bus Mode: In-Line Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1.2 Single Data Bus Mode: Look-Aside Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1.3 Port A Peripheral Chip Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Data Processing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.1 Compression Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.2 Compression Flush Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2.3 Decompression Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2.4 Decompression Output Disabled Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.5 Pass Through A to B Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.6 Pass Through B to A Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.0 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 DCLZ Control: Address 00 Hex - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 DCLZ Status: Address 01 Hex - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Comp Ratio Optimization: Address 02 Hex - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4 DMA Configuration: Address 03 Hex - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5 Port A Control 0: Address 04 Hex - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6 Port A Control 1: Address 05 Hex - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.7 Port A Status: Address 06 Hex - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.8 Port A Byte Count: Address 07,08,09 Hex - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.9 Port B Control 0: Address 0A Hex - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.10 Port B ControL 1: Address 0B Hex - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.11 Port B Status: Address 0C Hex - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12 Port B Byte Count: Address 0D,0E,0F Hex - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.13 Port B Byte Comparator: Address 10,11,12 Hex - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14 Record Length: Address 13,14,15 Hex - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.15 Record Count: Address 16,17,18 Hex - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.16 Interrupt Status: Address 19 Hex - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.17 Interrupt Clear: Address 19 Hex - Write Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.18 Interrupt Disable: Address 1A Hex - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.19 Identification: Address 1F Hex - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1 Processor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2 Port A Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.3 Port B Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.0 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.0 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.2.1 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.2.2 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.2.3 Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.0 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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8.0 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.0 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.1 Available Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.2 Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10.0 AHA Related Technical Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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Figures
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Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Dual Data Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Single Data Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Port A Peripheral Chip Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Compression Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Compression Flush Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Decompression Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Decompression Output Disabled Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pass Through A to B Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pass Through B to A Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Dynamic Current - Idd vs. Compression Ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Reset Timing - Power Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Processor Read Cycle - DSN, RWN Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Processor Write Cycle - DSN, RWN Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Processor Read Cycle - IORDN Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Processor Write Cycle - IOWRN Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Processor Read Cycle from Port A Peripheral - DSN, RWN Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Processor Write Cycle to Port A Peripheral - DSN, RWN Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Processor Read Cycle from Port A Peripheral - IORDN Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Processor Write Cycle to Port A Peripheral - IOWRN Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
DMA Slave Transfer Timing for Data Into Port A,B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DMA Slave Transfer Timing for Data Out of Port A,B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DMA Master Transfer Timing for Data Into Port A,B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
DMA Master Transfer Timing for Data Out of Port A,B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
AHA3210B Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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Tables
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Table 21:
iv
Data Bus Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Register Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
DCLZ Mode Bit Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Supported Modes for DCLZ Control Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
DATA BUS MODE Bit Decode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Port A DMA Bus Master/Slave Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Port B DMA Bus Master/Slave Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Clock Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Reset Timing Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Processor Read Cycle Timings - DSN, RWN Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Processor Write Cycle Timings - DSN, RWN Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Processor Read Cycle Timings - IORDN Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Processor Write Cycle Timings - IOWRN Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Processor Read Cycle Timings from Port A Peripheral - DSN, RWN Controlled . . . . . . . . . . . . . . . . . . . 36
Processor Write Cycle to Port A Peripheral Timings - DSN, RWN Controlled. . . . . . . . . . . . . . . . . . . . . . 37
Processor Read Cycle from Port A Peripheral Timings - IORDN Controlled . . . . . . . . . . . . . . . . . . . . . . . 38
Processor Write Cycle to Port A Peripheral Timings - IOWRN Controlled. . . . . . . . . . . . . . . . . . . . . . . . . 39
DMA Slave Transfer Timing for Data Into Port A,B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DMA Slave Transfer Timing for Data Out of Port A,B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DMA Master Transfer Timing for Data Into Port A,B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
DMA Master Transfer Timing for Data Out of Port A,B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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1.0
INTRODUCTION
The AHA3210B is a single-chip CMOS
lossless compression and decompression integrated
circuit under development implementing the
industry standard Data Compression Lempel Ziv
(DCLZ) adaptive compression algorithm. The
device processes data in compression,
decompression or pass-through modes. The
AHA3210B is based on the earlier 10 MBytes/sec
introduction, AHA3210. It maintains the same
pinout, performance, flexibility and I/O interface as
AHA3210.
Content Addressable Memory within the DCLZ
engine eliminates external SRAMs typically
required for dictionary storage in a compression
system. Other supporting system features include
two 24-bit counters, automatic multiple-record
transfer, compression ratio optimization and DCLZ
error detection logic.
The DCLZ algorithm is approved by several
standards organizations including QIC, DAT, ANSI,
ISO and ECMA. DCLZ has been accepted by
Hewlett-Packard and other system companies
worldwide as their standard of choice in their tape
storage peripherals. The algorithm exhibits an
average compression ratio of 2 to 1 over typical
computer data.
This specification contains a functional
overview, operation modes, register descriptions,
DC and AC Electrical characteristics, ordering
information and Related Technical Publications. It
is intended for hardware and software engineers
designing a compression system using AHA3210B.
AHA designs and develops lossless
compression, forward error correction and data
storage formatter/controller ICs. Technical
publications are available upon request from us or
our sales representatives/agents worldwide.
1.1
FEATURES
PERFORMANCE:
• 10 MBytes/sec data compression, decompression
or pass-through rate with a 20 MHz clock
• 2 to 1 average compression ratio
• High compression of small records
• Automatic multiple-record transfers without
microprocessor intervention
• Dynamic compression ratio monitoring
• Error checking in decompression mode
reportable via an interrupt
PS3210B-1299
FLEXIBILITY:
• In-Line and Look-Aside architectures supported
• Polled or interrupt driven I/O
• Two independent DMA ports programmable for
8 or 16-bit transfers; master or slave mode
SYSTEM INTERFACE:
• Single chip data compression solution
• No SRAM required
• Programmable interrupts
• Interfaces directly with AHA’s tape format
controller, AHA5140, and industry standard
SCSI controllers
OTHERS:
• Open standard DCLZ adaptive lossless
compression algorithm
• Standards include: QIC DDS/DAT, ANSI, ISO
and ECMA
• Low power stand-by operation
• EIAJ-standard 100 pin plastic quad flat package
• Software emulation of the algorithm available
1.2
APPLICATIONS
• DDS-DAT, QIC, 8mm or DLT tape drives
• High performance laser printers
1.3
FUNCTIONAL OVERVIEW
The AHA3210B Data Compression
Coprocessor IC is a high performance, single chip
data compression solution, for use in tape drives,
disk drives and embedded controller applications.
The processor interface is used to transfer data
to the registers inside the chip. The PROCMODE
strapping pin selects between a Motorola and an
Intel style processor interface.
The DCLZ Engine implements the DCLZ
lossless data compression algorithm. It contains a
compressor, which inputs uncompressed data from
the Port A interface, compresses it, and sends the
compressed codes to the Port B interface. The
DCLZ Engine also contains a decompressor, which
inputs compressed codes from the Port B interface,
decompresses it, and sends the uncompressed data
to the Port A interface. The Record Length register
and Record Count register allow uncompressed data
to be partitioned into fixed sized blocks, and then
compressed and decompressed automatically.
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Figure 1:
Functional Block Diagram
AHA3210B Compression Chip
PORT A INTERFACE
PORT B INTERFACE
SINGLE DATA
BUS ARBITER
ACSN
DREQA
DACKA
AOE
AWE
DAPTY[1:0]
PORT A
DMA
STATE
MACHINE
PORT A
BYTE
COUNTER
PORT B
DMA
STATE
MACHINE
RECORD COUNT
REGISTER
RECORD LENGTH
REGISTER
PORT A
FIFO
(8 Bytes)
DCLZ
ENGINE
PORT B
FIFO
(8 Bytes)
DREQB
DACKB
BOE
BWE
DBPTY[1:0]
PORT B
BYTE
COUNTER
DA[15:0]
DB[15:0]
PASS THROUGH
CONTROLLER
INTERRUPT
LOGIC
PROCESSOR INTERFACE
STATE MACHINE
A[4:0]
PORTACSN
CSN
RWN/IOWRN
DSN/IORDN
PROCMODE
TRISTATEN
TEST
RESTN
CLK
DTACKN/READY
D[7:0]
INTN/INT
PROCESSOR
INTERFACE
The Pass Through Controller block allows data
to be transferred between Port A and Port B without
being compressed or decompressed.
Port A and Port B are two independent DMA
interfaces. For compression and decompression
operations, Port A transfers uncompressed data and
Port B transfers compressed codes. Each port has a
byte counter, which counts the number of bytes that
are transferred through the port. The configuration
of the DMA interface on each port is programmable.
These functions include DMA master or slave, eight
or sixteen bit transfers, and control pin enabling and
polarity. The Port B Byte Count register has a Port B
Byte Comparator register, allowing the chip to
interrupt after a programmed amount of data has
been transferred on the Port B data bus, DB[15:0].
Register accesses to a peripheral chip connected to
Port A are also supported.
Page 2 of 45
2.0
MODES OF OPERATION
There are two classes of the modes of operation
for this chip. The first class is determined by the
Port A and Port B DMA data bus configurations.
Port A and Port B can be dual independent data
buses, or Port A and Port B can be connected to
create a single data bus. The second class is
determined by the method data is processed through
the chip in compression, decompression or pass
through modes.
2.1
PORT A AND B PORT DATA BUS
CONFIGURATION
Port A and Port B data bus configuration is
controlled by the DATA BUS MODE[2:0] bits in
the DMA Configuration register. These bits control
the single and dual data bus modes, as well as Port
A and Port B being the DMA bus master or slave
(see Table 1).
PS3210B-1299
advancedhardwarearchitectures
Table 1:
Data Bus Modes
DATA BUS DATA BUS DATA BUS
MODE[2] MODE[1] MODE[0]
0
0
0
0
1
1
1
1
2.1.1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
FUNCTION
Dual data bus: Port B slave, Port A slave
Dual data bus: Port B slave, Port A master
Dual data bus: Port B master, Port A slave
Dual data bus: Port B master, Port A master
Dual data bus: Port B slave, Port A slave with peripheral access
Reserved
Dual data bus: Port B master, Port A slave with peripheral access
Single data bus: Port B master, Port A master
DUAL DATA BUS MODE: IN-LINE
APPLICATION
expanding). The data rate during decompression,
pass through A to B, and pass through B to A modes
is sustained at 10 MBytes/sec (see Figure 3).
In dual data bus mode, Port A and Port B
transfer data on unique, independent data buses.
This is used for in-line applications, when data is
transferred from the host interface, through the data
compression coprocessor, and into the system
buffer (see Figure 2).
In dual data bus mode, the data rate during
compression is sustained at 10 MB/sec, except
when the compression ratio is less than 1 (which
occurs briefly when a compression dictionary is
first being built, or when data is actually
Figure 2:
2.1.2
SINGLE DATA BUS MODE: LOOK-ASIDE
APPLICATION
In single data bus mode, Port A and Port B
transfer data on a common data bus. This
connection is made external to the chip, on the PC
board. This is used in a look aside application, when
the data compression coprocessor transfers data into
and out of the system buffer.
Dual Data Bus Mode
SINGLE DATA
BUS ARBITER
HOST
INTERFACE
BUS
BUS
INTERFACE
CONTROLLER
PORT A
INTERFACE
PORT B
INTERFACE
DCLZ
ENGINE
SYSTEM
BUFFER
TAPE
DRIVE
INTERFACE
PROCESSOR INTERFACE
Figure 3:
Single Data Bus Mode
HOST
INTERFACE
BUS
BUS
INTERFACE
CONTROLLER
SYSTEM
BUFFER
TAPE
DRIVE
INTERFACE
SINGLE DATA
BUS ARBITER
PORT A
INTERFACE
PORT B
INTERFACE
DCLZ
ENGINE
PROCESSOR INTERFACE
PS3210B-1299
Page 3 of 45
Advanced
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Hardware Architectures, Inc.
2.1.3
PORT A PERIPHERAL CHIP INTERFACE
inserted into the compressed data. The end of record
codewords are then used during decompression, to
control data flow.
Multiple records can be compressed without
processor intervention. The Record Count register
inside the chip stores the number of records to
compress. A compression sequence has been
completed after the last byte of the last record has
been compressed and transferred out of Port B. This
event sets the Port B End of Transfer interrupt.
Compression ratio is defined as the number of
uncompressed bytes divided by the number of
compressed bytes. The Port A Byte Counter counts
the number of uncompressed bytes. The Port B Byte
Counter counts the number of compressed bytes.
The compression ratio can also be automatically
controlled, by programming the Comp Ratio
Optimization register.
The following sequence is used to program the
chip to compress multiple, fixed size records:
A peripheral chip can be connected to Port A,
and have its registers accessed through the
processor interface of the data compression chip
(see Figure 4). This is used in in-line applications,
for peripheral chips with a common DMA and
processor data bus (such as the NCR 53C90A/B and
the NCR 53C94/5/6 SCSI controllers).
It is the firmware’s responsibility to ensure
accesses to the peripheral chip’s registers do not
occur while DMA transfers are occurring on Port A.
This mode is only supported when Port A is a DMA
slave, in dual data bus mode.
2.2
DATA PROCESSING MODES
The data processing modes are controlled by the
DCLZ MODE[2:0] bits in the DCLZ Control
register.
2.2.1
- Program Record Length register
- Program Record Count register
- Program Interrupt Disable register
Enable PORT B END OF TRANSFER Interrupt
- Program Comp Ratio Optimization register
- Program DCLZ Control register
DCLZ MODE[2:0]
Compression
COMP RATIO OPT ENABLE
1
RESET DICT AFTER EOR
0
RESET DICT
0
PAUSE AFTER EOR
0
PAUSE
0
COMPRESSION MODE
During compression mode, uncompressed data
flows into Port A. It is then compressed by the
DCLZ engine. The resulting compressed data is
then transferred out of Port B (see Figure 5).
The uncompressed data is partitioned into fixed
sized records. The size is stored in the Record
Length register inside the chip. After a record has
been compressed, an end of record codeword is
Figure 4:
- The PORT B END OF TRANSFER interrupt signals
compression completed
Port A Peripheral Chip Interface
PERIPHERAL
CHIP
PORT A
INTERFACE
PORT B
INTERFACE
ACSN
DREQA
DACKA
AOE
AWE
DAPTY[1:0]
DA[15:0]
DCLZ
ENGINE
DREQB
DACKB
BOE
BWE
DBPTY[1:0]
DB[15:0]
PROCESSOR INTERFACE
A[4:0]
PORTACSN
CSN
RWN/IOWRN
DSN/IORDN
PROCMODE
TRISTATEN
TEST
RESETN
CLK
DTACKN/READY
D[7:0]
INTN/INT
A[3:0]
CS/
DREQ
DACK/
DBWR/
WR/
RD/
DBP[1:0]
DB[15:0]
AHA3210B Compression Chip
Page 4 of 45
PS3210B-1299
advancedhardwarearchitectures
Figure 5:
Compression Mode
AHA3210B Compression Chip
PORT A INTERFACE
PORT B INTERFACE
SINGLE DATA
BUS ARBITER
ACSN
DREQA
DACKA
AOE
AWE
DAPTY[1:0]
PORT A
DMA
STATE
MACHINE
PORT A
BYTE
COUNTER
PORT B
DMA
STATE
MACHINE
RECORD COUNT
REGISTER
RECORD LENGTH
REGISTER
PORT A
FIFO
(8 Bytes)
DCLZ
ENGINE
PORT B
FIFO
(8 Bytes)
DREQB
DACKB
BOE
BWE
DBPTY[1:0]
PORT B
BYTE
COUNTER
DB[15:0]
DA[15:0]
PASS THROUGH
CONTROLLER
PROCESSOR INTERFACE
STATE MACHINE
INTERRUPT
LOGIC
A[4:0]
PORTACSN
CSN
RWN/IOWRN
DSN/IORDN
PROCMODE
TRISTATEN
TEST
RESTN
CLK
DTACKN/READY
D[7:0]
INTN/INT
PROCESSOR
INTERFACE
2.2.2
COMPRESSION FLUSH MODE
Normal compression operations complete when
the Record Length register and the Record Count
register both decrement to zero. All data in the chip
is then compressed, and transferred out of Port B.
There is no data in the chip, and the chip is said to be
flushed (see Figure 6).
Consider the scenario when a compression
operation is required to complete prematurely (i.e.,
before the Record Length register and the Record
Count register have both decremented to zero). In
this scenario, Port A DMA is inactive, because there
is no more uncompressed data to transfer into the
chip. Due to the DCLZ data compression algorithm,
there may be partially compressed data in the DCLZ
engine at this time.
PS3210B-1299
Compression flush mode is used to complete
the compression operation, transfer all compressed
data out of Port B, and get the chip into the flushed
state. Note that the compression flush operation
inserts an end of record code word at the appropriate
location, near the end of the compressed data
stream.
The chip should only be programmed into
compression flush mode when the Port A Interface
is empty (i.e., when the Port Interface Byte Count in
the Port A Status register is zero) and the DCLZ
engine contains data (i.e., when the DCLZ Engine
Flushed bit in the DCLZ Status register is zero) and
the DCLZ Engine is not already in the process of
flushing (i.e., The DCLZ EOR COUNT bit in the
DCLZ Status register is zero).
Page 5 of 45
Advanced
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The following sequence is used to program the
chip for Compression Flush mode for the scenario
described above:
- Program DCLZ Control register
DCLZ MODE[2:0]
COMP RATIO OPT ENABLE
RESET DICT AFTER EOR
RESET DICT
PAUSE AFTER EOR
PAUSE
Compression
1
0
0
0
1
DCLZ MODE[2:0]
COMP RATIO OPT ENABLE
RESET DICT AFTER EOR
RESET DICT
PAUSE AFTER EOR
PAUSE
- Wait until the PAUSED bit in the DCLZ Status register is set
- Program Record Count register to 000000 hex
- Program Interrupt Disable register
Enable PORT B END OF TRANSFER Interrupt
- If the DCLZ Engine Flushed bit is zero and the DCLZ EOR
COUNT bit is zero, then there is data in the DCLZ Engine to
transfer out via compression flush mode.
-
The PORT B END OF TRANSFER interrupt signals
compression completed
END
- If the DCLZ Engine Flushed bit is one and the Port B Interface
Byte Count is not zero, then there is data in the Port B Interface
to transfer out.
BEGIN
Program DCLZ Control register
Compression flush
1
0
0
0
0
The PORT B END OF TRANSFER interrupt signals
compression completed
END
Figure 6:
Compression
1
0
0
0
0
-
BEGIN
Program DCLZ Control register
DCLZ MODE[2:0]
COMP RATIO OPT ENABLE
RESET DICT AFTER EOR
RESET DICT
PAUSE AFTER EOR
PAUSE
-
- If the DCLZ Engine Flushed bit is zero and the DCLZ EOR
COUNT bit is one, then the DCLZ Engine is already in the
process of flushing.
BEGIN
Program DCLZ Control register
DCLZ MODE[2:0]
COMP RATIO OPT ENABLE
RESET DICT AFTER EOR
RESET DICT
PAUSE AFTER EOR
PAUSE
Compression
1
0
0
0
0
-
The PORT B END OF TRANSFER interrupt signals
compression completed
END
- If the DCLZ Engine Flushed bit is one and the Port B Interface
Byte Count is zero, then the DCLZ Engine and the Port B
Interface are already flushed.
Compression Flush Mode
AHA3210B Compression Chip
PORT A INTERFACE
PORT B INTERFACE
SINGLE DATA
BUS ARBITER
ACSN
DREQA
DACKA
AOE
AWE
DAPTY[1:0]
PORT A
DMA
STATE
MACHINE
PORT A
BYTE
COUNTER
PORT B
DMA
STATE
MACHINE
RECORD COUNT
REGISTER
RECORD LENGTH
REGISTER
PORT A
FIFO
(8 Bytes)
DCLZ
ENGINE
PORT B
FIFO
(8 Bytes)
DREQB
DACKB
BOE
BWE
DBPTY[1:0]
PORT B
BYTE
COUNTER
DA[15:0]
DB[15:0]
PASS THROUGH
CONTROLLER
PROCESSOR INTERFACE
STATE MACHINE
INTERRUPT
LOGIC
A[4:0]
PORTACSN
CSN
RWN/IOWRN
DSN/IORDN
PROCMODE
TRISTATEN
TEST
RESTN
CLK
DTACKN/READY
D[7:0]
INTN/INT
PROCESSOR
INTERFACE
Page 6 of 45
PS3210B-1299
advancedhardwarearchitectures
2.2.3
DECOMPRESSION MODE
The following sequence is used to program the
chip to decompress multiple records:
During decompression mode, compressed data
flows into Port B. It is then uncompressed by the
DCLZ engine. The resulting uncompressed data is
then transferred out of Port A.
The compressed data is partitioned into records,
with End of Record codewords embedded in the
compressed data. Multiple records can be
automatically decompressed, by programming the
number of records into the Record Count register. A
decompression sequence has been completed after
the last byte of the last record has been
uncompressed and then transferred out of Port A.
This event sets the Port A End of Transfer interrupt.
Figure 7:
- Program Record Count register
- Program Interrupt Disable register
Enable PORT A END OF TRANSFER Interrupt
- Program DCLZ Control register
DCLZ MODE[2:0]
COMP RATIO OPT ENABLE
RESET DICT AFTER EOR
RESET DICT
PAUSE AFTER EOR
PAUSE
Decompression
0
0
0
0
0
- The PORT A END OF TRANSFER Interrupt signals
decompression completed
Decompression Mode
AHA3210B Compression Chip
PORT A INTERFACE
PORT B INTERFACE
SINGLE DATA
BUS ARBITER
ACSN
DREQA
DACKA
AOE
AWE
DAPTY[1:0]
PORT A
DMA
STATE
MACHINE
PORT A
BYTE
COUNTER
PORT B
DMA
STATE
MACHINE
RECORD COUNT
REGISTER
RECORD LENGTH
REGISTER
PORT A
FIFO
(8 Bytes)
DCLZ
ENGINE
PORT B
FIFO
(8 Bytes)
DREQB
DACKB
BOE
BWE
DBPTY[1:0]
PORT B
BYTE
COUNTER
DB[15:0]
DA[15:0]
PASS THROUGH
CONTROLLER
PROCESSOR INTERFACE
STATE MACHINE
INTERRUPT
LOGIC
A[4:0]
PORTACSN
CSN
RWN/IOWRN
DSN/IORDN
PROCMODE
TRISTATEN
TEST
RESTN
CLK
DTACKN/READY
D[7:0]
INTN/INT
PROCESSOR
INTERFACE
PS3210B-1299
Page 7 of 45
Advanced
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2.2.4
DECOMPRESSION OUTPUT DISABLED
MODE
The DCLZ algorithm allows the compression
dictionary to be shared between multiple records.
To decompress records in the middle of a multiple
record sequence, the preceding records must first be
decompressed, in order to properly build the
compression dictionary.
Decompression output disabled mode allows
the preceding records to be decompressed, while
discarding the unwanted uncompressed data. Once
this is completed, the chip can be programmed to
decompression mode, to decompress and output the
desired records.
In decompression output disabled mode, the
data is discarded between the Port A Interface and
the Port A pins. Port A DMA remains inactive. The
Port B Byte Counter, the Port A Byte Counter, the
Port B Interface Byte Count, the Port A Interface
Figure 8:
Byte Count, the Record Count register, and the Port
A End of Transfer Interrupt operate as in
decompression mode. It is recommended that the
Port A Interface be empty and the chip paused
before switching between decompression output
disabled and decompression modes.
The following sequence is used to program the
chip to decompress multiple records in output
disabled mode:
- Program Record Count register
- Program Interrupt Disable register
Enable PORT A END OF TRANSFER Interrupt
- Program DCLZ Control register
DCLZ MODE[2:0]
COMP RATIO OPT ENABLE
RESET DICT AFTER EOR
RESET DICT
PAUSE AFTER EOR
PAUSE
Decomp; Output
Disabled Mode
0
0
0
0
0
- The PORT A END OF TRANSFER Interrupt signals
decompression output disabled completed
Decompression Output Disabled Mode
AHA3210B Compression Chip
PORT A INTERFACE
PORT B INTERFACE
SINGLE DATA
BUS ARBITER
ACSN
DREQA
DACKA
AOE
AWE
DAPTY[1:0]
PORT A
DMA
STATE
MACHINE
PORT A
BYTE
COUNTER
PORT B
DMA
STATE
MACHINE
RECORD COUNT
REGISTER
RECORD LENGTH
REGISTER
PORT A
FIFO
(8 Bytes)
DCLZ
ENGINE
PORT B
FIFO
(8 Bytes)
DREQB
DACKB
BOE
BWE
DBPTY[1:0]
PORT B
BYTE
COUNTER
DB[15:0]
DA[15:0]
PASS THROUGH
CONTROLLER
PROCESSOR INTERFACE
STATE MACHINE
INTERRUPT
LOGIC
A[4:0]
PORTACSN
CSN
RWN/IOWRN
DSN/IORDN
PROCMODE
TRISTATEN
TEST
RESTN
CLK
DTACKN/READY
D[7:0]
INTN/INT
PROCESSOR
INTERFACE
Page 8 of 45
PS3210B-1299
advancedhardwarearchitectures
2.2.5
PASS THROUGH A TO B MODE
During pass through A to B mode, data enters
Port A, is transferred through the Port A Interface
and the Port B Interface, and then transferred out of
Port B. The data is not altered as it passes through
the chip.
The Record Length register determines the
number of bytes in a record. The Record Count
register determines the number of records. Multiply
the values of these two registers to determine the
total number of bytes that will be transferred
through the chip. The pass through sequence has
been completed after the last byte of the last record
Figure 9:
has been transferred out of Port B. This event sets
the Port B End of Transfer interrupt.
The following sequence is used to program the
chip to pass through data from Port A to Port B:
- Program Record Length register
- Program Record Count register
- Program Interrupt Disable register
Enable PORT B END OF TRANSFER Interrupt
- Program DCLZ Control register
DCLZ MODE[2:0]
COMP RATIO OPT ENABLE
RESET DICT AFTER EOR
RESET DICT
PAUSE AFTER EOR
PAUSE
Pass through A to B
0
0
0
0
0
- The PORT B END OF TRANSFER interrupt signals pass
through A to B completed
Pass Through A to B Mode
AHA3210B Compression Chip
PORT A INTERFACE
PORT B INTERFACE
SINGLE DATA
BUS ARBITER
ACSN
DREQA
DACKA
AOE
AWE
DAPTY[1:0]
PORT A
DMA
STATE
MACHINE
PORT A
BYTE
COUNTER
PORT B
DMA
STATE
MACHINE
RECORD COUNT
REGISTER
RECORD LENGTH
REGISTER
PORT A
FIFO
(8 Bytes)
DCLZ
ENGINE
PORT B
FIFO
(8 Bytes)
DREQB
DACKB
BOE
BWE
DBPTY[1:0]
PORT B
BYTE
COUNTER
DB[15:0]
DA[15:0]
PASS THROUGH
CONTROLLER
PROCESSOR INTERFACE
STATE MACHINE
INTERRUPT
LOGIC
A[4:0]
PORTACSN
CSN
RWN/IOWRN
DSN/IORDN
PROCMODE
TRISTATEN
TEST
RESTN
CLK
DTACKN/READY
D[7:0]
INTN/INT
PROCESSOR
INTERFACE
PS3210B-1299
Page 9 of 45
Advanced
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2.2.6
PASS THROUGH B TO A MODE
During pass through B to A mode, data enters
Port B, is transferred through the Port B Interface
and Port A Interface, and is then transferred out of
Port A. The data is not altered as it passes through
the chip.
The Record Length register determines the
number of bytes in a record. The Record Count
register determines the number of records. Multiply
the values of these two registers to determine the
total number of bytes that will be transferred
through the chip. The pass through sequence has
been completed after the last byte of the last record
has been transferred out of Port A. This event sets
the Port A End of Transfer interrupt.
The following sequence is used to program the
chip to pass through data from Port B to Port A:
- Program Record Length register
- Program Record Count register
- Program Interrupt Disable register
Enable PORT A END OF TRANSFER Interrupt
- Program DCLZ Control register
DCLZ MODE[2:0]
Pass through B to A
COMP RATIO OPT ENABLE
0
RESET DICT AFTER EOR
0
RESET DICT
0
PAUSE AFTER EOR
0
PAUSE
0
- The PORT A END OF TRANSFER interrupt signals pass
through B to A completed
Figure 10: Pass Through B to A Mode
AHA3210B Compression Chip
PORT A INTERFACE
PORT B INTERFACE
SINGLE DATA
BUS ARBITER
ACSN
DREQA
DACKA
AOE
AWE
DAPTY[1:0]
PORT A
DMA
STATE
MACHINE
PORT A
BYTE
COUNTER
PORT B
DMA
STATE
MACHINE
RECORD COUNT
REGISTER
RECORD LENGTH
REGISTER
PORT A
FIFO
(8 Bytes)
DCLZ
ENGINE
PORT B
FIFO
(8 Bytes)
DREQB
DACKB
BOE
BWE
DBPTY[1:0]
PORT B
BYTE
COUNTER
DA[15:0]
DB[15:0]
PASS THROUGH
CONTROLLER
PROCESSOR INTERFACE
STATE MACHINE
INTERRUPT
LOGIC
A[4:0]
PORTACSN
CSN
RWN/IOWRN
DSN/IORDN
PROCMODE
TRISTATEN
TEST
RESTN
CLK
DTACKN/READY
D[7:0]
INTN/INT
PROCESSOR
INTERFACE
Page 10 of 45
PS3210B-1299
advancedhardwarearchitectures
3.0
REGISTER DESCRIPTION
Table 2:
Register Address Map
ADDRESS
READ
WRITE
HARD
RESET
SOFT**
RESET
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1F
DCLZ Control
DCLZ Status
Comp Ratio Optimization
*DMA Configuration
Port A Control 0
*Port A Control 1
Port A Status
Port A Byte Count [7:0]
Port A Byte Count [15:8]
Port A Byte Count [23:16]
Port B Control 0
*Port B Control 1
Port B Status
Port B Byte Count [7:0]
Port B Byte Count [15:8]
Port B Byte Count [23:16]
Port B Byte Comparator [7:0]
Port B Byte Comparator [15:8]
Port B Byte Comparator [23:16]
Record Length [7:0]
Record Length [15:8]
Record Length [23:16]
Record Count [7:0]
Record Count [15:8]
Record Count [23:16]
Interrupt Status
*Interrupt Disable
Identification
DCLZ Control
Reserved
Comp Ratio Optimization
DMA Configuration
Port A Control 0
Port A Control 1
Reserved
Port A Byte Count [7:0]
Port A Byte Count [15:8]
Port A Byte Count [23:16]
Port B Control 0
Port B Control 1
Reserved
Port B Byte Count [7:0]
Port B Byte Count [15:8]
Port B Byte Count [23:16]
Port B Byte Comparator [7:0]
Port B Byte Comparator [15:8]
Port B Byte Comparator [23:16]
Record Length [7:0]
Record Length [15:8]
Record Length [23:16]
Record Count [7:0]
Record Count [15:8]
Record Count [23:16]
Interrupt Clear
Interrupt Disable
Reserved
1110,0000
0000,0011
0000,0000
0000,0101
0000,0000
x000,00xx
0000,0000
0000,0000
0000,0000
0000,0000
0000,0000
x000,00xx
0000,0000
0000,0000
0000,0000
0000,0000
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000,0000
0011,1111
0100,0001
111U,UUUU
0000,0011
Unchanged
Unchanged
Unchanged
Unchanged
0U00,0000
Unchanged
Unchanged
Unchanged
Unchanged
Unchanged
0U00,0000
Unchanged
Unchanged
Unchanged
Unchanged
Unchanged
Unchanged
Unchanged
Unchanged
Unchanged
Unchanged
Unchanged
Unchanged
Unchanged
Unchanged
0100,0001
Notations:
* These registers have one or more reserved bits set to ‘0’. These registers read back ‘0’ from these reserved bits.
** A soft reset is generated by writing a reset command to DCLZ MODE[2:0].
U - These bits remain unchanged after a soft reset.
x - Indicates undefined bit.
PS3210B-1299
Page 11 of 45
Advanced
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3.1
DCLZ CONTROL: ADDRESS 00 HEX - READ/WRITE
bit7
0x00
bit6
bit5
bit4
bit3
COMP
RESET DICT
RATIO OPT
AFTER EOR
ENABLE
DCLZ MODE[2:0]
bit2
RESET
DICT
bit1
bit0
PAUSE
PAUSE
AFTER EOR
DCLZ MODE[2:0] = DCLZ Control register [7:5]:
The DCLZ MODE bits determine how the chip will process data as follows.
– Pass through modes transfer data through the chip without any compression or decompression
operation. Pass through A to B transfers data into Port A and out of Port B. Pass through B to A
transfers data into Port B and out of Port A.
– Compression mode transfers uncompressed data into Port A, compresses it, and transfers
compressed data out of Port B.
– Compression flush mode causes all data in the DCLZ Engine to be compressed including an end of
record codeword, and then flushed out of the chip through Port B.
– Decompression mode transfers compressed data into Port B, decompresses it, and transfers
uncompressed data out of Port A.
– Decompression output disabled mode transfers compressed data into Port B, decompresses it and
builds the decompression dictionary, but does not transfer any uncompressed data out of Port A.
– Reset mode resets all state machines and data in Port A, Port B, single data bus arbiter, and the
DCLZ engine. It also resets the dictionary. It resets the registers as shown in Table 2.
The DCLZ Control bits should always be programmed to the reset mode, when switching between all
modes, except between compression and compression flush modes and between decompression and
decompression output disabled modes. It is recommended that the Port A Interface be empty and the
chip paused before switching between decompression output disabled and decompression modes. The
DCLZ MODE bits are set to one when the chip is reset from the RESETN pin. The DCLZ MODE bits
are decoded as shown below:
Table 3:
DCLZ Mode Bit Decode
DCLZ
MODE[2]
DCLZ
MODE[1]
DCLZ
MODE[0]
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
FUNCTION
Pass through A to B
Pass through B to A
Compression
Compression flush
Decompression
Decompression output disable
Reserved
Reset
COMP RATIO OPT ENABLE:
The COMPRESSION RATIO OPTIMIZATION ENABLE bit enables the automatic compression ratio
optimizer during compression. This bit enables the THRESH[5:0] and PERIOD[1:0] bits in the Comp
Ratio Optimization register. A one enables optimization, and a zero disables optimization. This bit is
cleared to zero when the chip is reset from the RESETN pin.
RESET DICT AFTER EOR:
During compression, the RESET DICTIONARY AFTER END OF RECORD bit causes the DCLZ
engine to reset the compression dictionary after each end of record, and before the first subsequent byte
which is not designated as an end of record. A one resets the dictionary after end of record, and a zero
has no effect on the dictionary. This bit is cleared to zero when the chip is reset from the RESETN pin.
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RESET DICT
The RESET DICTIONARY bit causes the compression dictionary to be reset after completing the
current byte, and before the next byte which is not designated as an end of record. A one causes the
dictionary to be reset, and a zero has no effect on the dictionary. The RESET DICT bit will be
automatically cleared, once a dictionary reset has occurred. This bit is cleared to zero when the chip is
reset from the RESETN pin.
PAUSE AFTER EOR:
Writing a one to the PAUSE AFTER END OF RECORD bit causes the Port A interface, the DCLZ
Engine and the Port B interface to pause after each end of record has been processed. The PAUSED
status bit in the DCLZ Status register is then set. To allow the chip to continue, a zero must be written
to the PAUSE bit. This bit is cleared to zero when the chip is reset from the RESETN pin.
PAUSE:
Writing a one to the PAUSE bit causes the Port A interface, the DCLZ Engine, and the Port B interface
to pause. The PAUSED status bit in the DCLZ Status register is then set. Writing a zero to the PAUSE
bit allows the chip to resume operation after it has been paused or paused after end of record. PAUSE
bit operation is supported during processor write cycles which program the DCLZ Control bits out of the
Reset state. This bit is cleared to zero when the chip is reset from the RESETN pin.
Table 4:
Supported Modes for DCLZ Control Register Bits
COMP RATIO RESET DICT
OPT ENABLE AFTER EOR
MODE
Compression
Compression flush
Decompression
Decompression output disabled
Pass through A to B
Pass through B to A
3.2
YES
YES
NO
NO
NO
NO
YES
YES
NO
NO
NO
NO
RESET
DICT
YES
YES
NO
NO
NO
NO
PAUSE
PAUSE
AFTER EOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
DCLZ STATUS: ADDRESS 01 HEX - READ ONLY
bit7
0x01
bit6
bit5
res
bit4
bit3
bit2
bit1
bit0
DCLZ EOR DCLZ ENGINE
PAUSED
COUNT
FLUSHED
res Reserved. Bits read back zeros.
DCLZ EOR COUNT:
The DCLZ EOR COUNT bit shows the number of end of records contained in the DCLZ Engine. This
bit operates in compression, compression flush, decompression, and decompression output disabled
mode. This bit is cleared to zero when the reset or pass through A to B or pass through B to A code is
programmed to the DCLZ MODE bits in the DCLZ Control register, or when the chip is reset by the
RESETN pin. The DCLZ EOR COUNT bit can transition frequently when the DCLZ Engine is actively
processing data (i.e., when it is not paused). Therefore, the DCLZ EOR COUNT bit should only be
considered valid when the PAUSED bit is one.
DCLZ ENGINE FLUSHED:
This bit operates in compression, compression flush, decompression, and decompression output
disabled modes only. When the DCLZ ENGINE FLUSHED bit is a one, there is no data in the DCLZ
Engine. This occurs after an end of record has been processed through the DCLZ Engine, and before the
first byte of the next record has entered the DCLZ Engine. Once the first byte of the next record enters
the DCLZ Engine, the DCLZ ENGINE FLUSHED bit is cleared to zero. The DCLZ ENGINE
FLUSHED bit is set to one when the DCLZ MODE bits are programmed to pass through A to B, pass
through B to A, or reset mode. Also, the DCLZ ENGINE FLUSHED bit is set to one when the chip is
reset by the RESETN pin. The DCLZ ENGINE FLUSHED bit can transition frequently when the DCLZ
Engine is actively processing data (i.e., when it is not paused). Therefore, the DCLZ ENGINE
FLUSHED bit should only be considered valid when the PAUSED bit is one.
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PAUSED:
When the PAUSED bit is one, the Port A interface, the DCLZ Engine, and the Port B interface are
paused. The Port A Byte Count registers, the Port B Byte Count registers, the Port A Status register, the
Port B Status register, the Record Length registers, and the Record Count registers are stable at this time.
This bit is set to one when the chip is reset from the RESETN pin, or when the DCLZ Control bits are
programmed to the Reset state.
3.3
COMP RATIO OPTIMIZATION: ADDRESS 02 HEX - READ/WRITE
bit7
bit6
bit5
bit4
bit3
bit2
THRESH[5:0]
0x02
bit1
bit0
PERIOD[1:0]
This register is used to control the compression ratio during compression mode, by automatically
resetting the compression dictionary if the compression ratio is below the programmed threshold. If the
compression dictionary is less than half full the optimization circuit will check the compression ratio and
compare it to the compression ratio programmed in the THRESHOLD parameter every 1024 input bytes
and reset the dictionary if the compression ratio does not meet or exceed this value. After the dictionary is
greater than half full, the optimizer will check the compression ratio against a threshold every n bytes,
where n is determined by the value of the PERIOD bits. The threshold is set by the value of the THRESH
bits. Optimization is enabled by setting COMP RATIO OPT ENABLE bit in the DCLZ Control register.
The compression ratio is specified by the threshold bits according to the following formula:
64
compression ratio = ---------------------------------64 – THRESH
For example, if THRESH is set at 32 the compression ratio is 2. This compression ratio is a target. After
every N number of bytes as specified by the PERIOD field has been input, the actual compression ratio is
checked against the target. If the actual is less than the target, the dictionary is automatically reset. The
THRESH[5:0] and PERIOD[1:0] bits are zero when the chip is reset by the RESETN pin.
PERIOD
bit 1
0
0
1
1
bit 0
0
1
0
1
Size
512 bytes
1024 bytes
2048 bytes
4096 bytes
COMPRESSION RANGES
Compression Ratio
1→2
2→3
3→4
4→8
8 → 64
3.4
Threshold Value
0 → 32
33 → 42
43 → 48
49 → 56
57 → 63
DMA CONFIGURATION: ADDRESS 03 HEX - READ/WRITE
bit7
0x03
bit6
bit5
bit4
res
bit3
bit2
bit1
bit0
DATA BUS MODE[2:0]
res Reserved. Bits must always be written with zeros. They read back zeros.
DATA BUS MODE [2:0]:
The DATA BUS MODE bits determine the data configuration for the Port A and Port B DMA buses. In
dual data bus mode, Port A and Port B are independent, isolated data buses. Data transfers on each bus
may occur simultaneously. In this mode, Port A and Port B can be any combination of DMA bus masters
or slaves. This mode is intended for in line applications. In single bus mode, the Port A and Port B data
buses are connected together on the PC board.
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Both Port A and Port B are DMA bus masters. The Single Data Bus Arbiter circuit inside the chip
resolves all bus contention on this single data bus. Port A and Port B will never simultaneously request
the data bus in this mode. This mode is intended for look aside applications. Note that in single data bus
mode, the DMA port which is transferring data out of the chip has priority over the DMA port which is
transferring data into the chip.
The Port A interface supports register accesses to a peripheral chip on the Port A data bus. register and
DMA accesses between the Port A interface and the peripheral chip occur on a single data bus, DA[7:0].
This mode is only supported when Port A is a DMA slave in dual data bus mode.
Data bus mode bits are set to 101 after the chip is reset by RESETN.
Table 5:
DATA BUS MODE Bit Decode
DATA BUS DATA BUS DATA BUS
MODE[2] MODE[1] MODE[0]
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
FUNCTION
Dual data bus: Port B slave, Port A slave
Dual data bus: Port B slave, Port A master
Dual data bus: Port B master, Port A slave
Dual data bus: Port B master, Port A master
Dual data bus: Port B slave, Port A slave with peripheral access
Reserved
Dual data bus: Port B master, Port A slave with peripheral access
Single data bus: Port B master, Port A master
The Port A and Port B DMA control pins change direction, based on the master or slave mode. The
following table shows the DMA control pin direction for DMA bus master and slave modes: Port A
DMA Bus Master/Slave Pin Configuration
Table 6:
Table 7:
3.5
Port A DMA Bus Master/Slave Pin Configuration
PORT A DMA
BUS MASTER
PORT A DMA
BUS SLAVE
DREQA
DACKA
AOE
AWE
Output
Input
Input
Input
Input
Output
Output
Output
Port B DMA Bus Master/Slave Pin Configuration
PIN NAME
PORT B DMA
BUS MASTER
PORT B DMA
BUS SLAVE
DREQB
DACKB
BOE
BWE
Output
Input
Input
Input
Input
Output
Output
Output
PORT A CONTROL 0: ADDRESS 04 HEX - READ/WRITE
bit7
0x04
PIN NAME
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ENABLE ENABLE
AWE
AOE
AWE
AOE
DREQA
DACKA
DA
DAPTY
ENABLE ENABLE POLARITY POLARITY POLARITY POLARITY
PULLUP PULLUP
ENABLE DA PULLUP:
A one enables the pullups on the DA[15:0] pins. A zero tristates the pullups on the DA[15:0] pins. This
bit is cleared to zero when the chip is reset by the RESETN pin.
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ENABLE DAPTY PULLUP:
A one enables the pullups on the DAPTY[1:0] pins. A zero tristates the pullups on the DAPTY[1:0] pins.
This bit is cleared to zero when the chip is reset by the RESETN pin.
AWE ENABLE:
A one enables the AWE input when Port A is a DMA bus master, and enables the AWE output when Port
A is a DMA bus slave. A zero disables the AWE input when Port A is a DMA bus master, and tristates
the AWE output when Port A is a DMA bus slave. This bit is cleared to zero when the chip is reset by
the RESETN pin.
AOE ENABLE:
A one enables the AOE input when Port A is a DMA bus master, and enables the AOE output when Port
A is a DMA bus slave. A zero disables the AOE input when Port A is a DMA bus master, and tristates
the AOE output when Port A is a DMA bus slave. This bit is cleared to zero when the chip is reset by
the RESETN pin.
AWE POLARITY:
A one makes AWE high active. A zero makes AWE low active. This bit is cleared to zero when the chip
is reset by the RESETN pin.
AOE POLARITY:
A one makes AOE high active. A zero makes AOE low active. This bit is cleared to zero when the chip
is reset by the RESETN pin.
DREQA POLARITY:
A one makes DREQA high active. A zero makes DREQA low active. This bit is cleared to zero when
the chip is reset by the RESETN pin.
DACKA POLARITY:
A one makes DACKA high active. A zero makes DACKA low active. This bit is cleared to zero when
the chip is reset by the RESETN pin.
3.6
PORT A CONTROL 1: ADDRESS 05 HEX - READ/WRITE
bit7
0x05
bit6
DATA
BUS
DATA15TO8
WIDTH
bit5
res
bit4
bit3
PORT A
CLEAR
DISABLE INTERFACE
bit2
bit1
CLEAR
ENABLE
BYTE
PARITY
COUNTER
bit0
ODD
PARITY
DATA BUS WIDTH:
A one makes the Port A data bus 16 bits wide, with data transferred on the DA[15:0] pins. A zero makes
the Port A data bus 8 bits wide, with data transferred on the DA[7:0] pins. This bit should only be
changed after the reset code has been programmed to the DCLZ Control bits in the DCLZ Control
register. This bit is undefined when the chip is reset from the RESETN pin.
DATA15TO8:
The DATA15TO8 bit causes one byte to be transferred on DA[15:8] on the next DMA cycle into or out
of Port A, when Port A is in 16 bit mode. The intended use of this bit is to transfer a single byte on
DA[15:8] only during the first DMA cycle of a contiguous data transfer sequence. The DATA15TO8 bit
only functions when Port A is in 16 bit mode, and is ignored when Port A is in 8 bit mode. The
DATA15TO8 bit should only be changed after the reset code has been programmed into the DCLZ
Control bits in the DCLZ Control register, or after the chip has paused after end of record, or after the
chip has paused because the Port A or Port B end of transfer interrupt has occurred. DATA15TO8 takes
effect only on the next DMA cycle, which is defined as the next occurrence when DACKA pulses active,
and is supported when Port A is a DMA bus master or a DMA bus slave. After the DMA cycle occurs,
the DATA15TO8 bit is automatically cleared. DATA15TO8 is cleared to zero when the chip is reset from
the RESETN pin.
res Reserved. Bit must always be written with a zero. It reads back a zero.
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PORT A DISABLE:
A one disables the Port A control and data buses. The Port A output control signals are made hiimpedance. The Port A input control signals are ignored. The DA[15:0] and DAPTY[1:0] data pins are
put into a hi-impedance state and any transitions on them are ignored. A zero in this bit position places
Port A into normal operational mode. This bit should only be changed while the chip is paused at an End
of Transfer condition. The contents of the DCLZ Control register, the DMA Configuration register, and
the Port A Control 0 register, should not be changed while this bit is a one. This bit is cleared to zero
when the chip is reset from the RESETN pin.
CLEAR INTERFACE:
Writing a one creates a pulse, which clears the Port A Interface. Writing a zero has no effect on the Port
A Interface. This bit is always a zero when it is read. The CLEAR INTERFACE bit is intended to be used
only when the chip has paused after end of record, or paused because the Port A or Port B end of transfer
interrupt has occurred.
CLEAR BYTE COUNTER:
Writing a one creates a pulse, which clears the Port A Byte Count register. Writing a zero has no effect
on the Port A Byte Count register. This bit is always a zero when it is read.
ENABLE PARITY:
A one enables parity on DAPTY[1:0] when Port A is in 16 bit mode, and on DAPTY[0] when Port A is
in 8 bit mode. Writing a zero disables parity on Port A. This bit is undefined when the chip is reset from
the RESETN pin.
ODD PARITY:
A one selects odd parity on Port A. A zero selects even parity on Port A. This bit is undefined when the
chip is reset from the RESETN pin.
3.7
0x06
PORT A STATUS: ADDRESS 06 HEX - READ ONLY
bit7
bit6
res
DATA7TO0
bit5
bit4
EOR COUNT[1:0]
bit3
bit2
bit1
bit0
INTERFACE BYTE COUNT[3:0]
res Reserved. Bit reads back zero.
DATA7TO0:
When Port A is in 16 bit mode, the DATA7TO0 bit shows whether the last DMA cycle of a data transfer
sequence out of Port A contains one or two valid bytes. This occurs for the last byte of the last record,
as determined by the Record Count register. If the last byte of the last record is the first byte in the
sequence to output a word, that byte is output on DA[7:0], the data on DA[15:8] is undefined, and the
DATA7TO0 bit is set. If the last byte of the last record is the second byte in the sequence to output a
word, the second to last byte is output on DA[7:0], the last byte is output on DA[15:8], and the
DATA7TO0 bit is cleared. The DATA7TO0 bit is cleared during all DMA cycles into Port A, during all
DMA cycles when Port A is in 8 bit mode, and when the chip is reset from the RESETN pin.
EOR COUNT[1:0]:
The EOR COUNT[1:0] bits show the number of bytes with active end of record flags contained in the
Port A Interface. These bits operate in compression, compression flush, decompression, decompression
output disabled, pass through A to B, and pass through B to A modes. These bits are cleared to zero when
a one is written to the CLEAR INTERFACE bit in Port A Control 1 register, or when the reset code is
programmed to the DCLZ MODE bits in the DCLZ Control register, or when the chip is reset by the
RESETN pin. During data transfers, these bits should only be read when the PAUSED bit in the DCLZ
Status register is a one.
INTERFACE BYTE COUNT[3:0]:
The INTERFACE BYTE COUNT[3:0] bits show the number of bytes that are held in the Port A
Interface. These bits are cleared to zero when a one is written to the CLEAR INTERFACE bit in Port A
Control 1 register, or when the reset code is programmed to the DCLZ MODE bits in the DCLZ Control
register, or when the chip is reset by the RESETN pin. During data transfers, these bits should only be
read when the PAUSED bit in the DCLZ Status register is a one.
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3.8
PORT A BYTE COUNT: ADDRESS 07,08,09 HEX - READ/WRITE
Least Significant Byte (address 07 hex):
bit7
bit6
bit5
bit4
bit6
bit5
bit4
bit6
bit1
bit0
bit5
bit3
bit2
bit1
bit0
bit2
bit1
bit0
[15:8]
0x08
Most Significant Byte (address 09 hex):
bit7
bit2
[7:0]
0x07
Middle Byte (address 08 hex)
bit7
bit3
bit4
bit3
[23:16]
0x09
The Port A Byte Count register counts the number of bytes that are transferred by the Port A DMA State
Machine. This register counts in compression, compression flush, decompression, decompression output
disabled, pass through A to B, and pass through B to A modes. The register is cleared to zero when a one is
written to the CLEAR BYTE COUNTER bit in Port A Control 1 register, or when the chip is reset by the
RESETN pin. During data transfers, this register should only be written or read when the PAUSED bit in the
DCLZ Status register is a one. The counter rolls over from FFFFFF hex to 000000 hex.
3.9
PORT B CONTROL 0: ADDRESS 0A HEX - READ/WRITE
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ENABLE ENABLE
BWE
BOE
BWE
BOE
DREQB
DACKB
DB
DBPTY
0x0A
ENABLE ENABLE POLARITY POLARITY POLARITY POLARITY
PULLUP PULLUP
ENABLE DB PULLUP:
A one enables the pullups on the DB[15:0] pins. A zero tristates the pullups on the DB[15:0] pins. This
bit is cleared to zero when the chip is reset by the RESETN pin.
ENABLE DBPTY PULLUP:
A one enables the pullups on the DBPTY[1:0] pins. A zero tristates the pullups on the DBPTY[1:0] pins.
This bit is cleared to zero when the chip is reset by the RESETN pin.
BWE ENABLE:
A one enables the BWE input when Port B is a DMA bus master, and enables the BWE output when Port
B is a DMA bus slave. A zero disables the BWE input when Port B is a DMA bus master, and tristates
the BWE output when Port B is a DMA bus slave. This bit is cleared to zero when the chip is reset by
the RESETN pin.
BOE ENABLE:
A one enables the BOE input when Port B is a DMA bus master, and enables the BOE output when Port
B is a DMA bus slave. A zero disables the BOE input when Port B is a DMA bus master, and tristates
the BOE output when Port B is a DMA bus slave. This bit is cleared to zero when the chip is reset by
the RESETN pin.
BWE POLARITY:
A one makes BWE high active. A zero makes BWE low active. This bit is cleared to zero when the chip
is reset by the RESETN pin.
BOE POLARITY:
A one makes BOE high active. A zero makes BOE low active. This bit is cleared to zero when the chip
is reset by the RESETN pin.
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DREQB POLARITY:
A one makes DREQB high active. A zero makes DREQB low active. This bit is cleared to zero when
the chip is reset by the RESETN pin.
DACKB POLARITY:
A one makes DACKB high active. A zero makes DACKB low active. This bit is cleared to zero when
the chip is reset by the RESETN pin.
3.10 PORT B CONTROL 1: ADDRESS 0B HEX - READ/WRITE
bit7
0x0B
bit6
DATA
BUS
DATA15TO8
WIDTH
bit5
res
bit4
bit3
bit2
bit1
bit0
CLEAR
ENABLE
ENABLE ODD
CLEAR
BYTE
PORT B
PARITY PARITY
INTERFACE
COUNTER
COMPARATOR
DATA BUS WIDTH:
A one makes the Port B data bus 16 bits wide, with data transferred on the DB[15:0] pins. A zero makes
the Port B data bus 8 bits wide, with data transferred on the DB[7:0] pins. This bit should only be
changed after the reset code has been programmed to the DCLZ Control bits in the DCLZ Control
register. This bit is undefined when the chip is reset from the RESETN pin.
DATA15TO8:
The DATA15TO8 bit causes one byte to be transferred on DB[15:8] on the next DMA cycle into or out
of Port B, when Port B is in 16 bit mode. The intended use of this bit is to transfer a single byte on
DB[15:8] only during the first DMA cycle of a contiguous data transfer sequence. The DATA15TO8 bit
only functions when Port B is in 16 bit mode, and is ignored when Port B is in 8 bit mode. The
DATA15TO8 bit should only be changed after the reset code has been programmed into the DCLZ
Control bits in the DCLZ Control register, or after the chip has paused after end of record, or after the
chip has paused because the Port A or Port B end of transfer interrupt has occurred. DATA15TO8 takes
effect only on the next DMA cycle, which is defined as the next occurrence when DACKB pulses active,
and is supported when Port B is a DMA bus master or a DMA bus slave. After the DMA cycle occurs,
the DATA15TO8 bit is automatically cleared. DATA15TO8 is cleared to zero when the chip is reset from
the RESETN pin.
res Reserved. Bit must always be written with a zero. It reads back a zero.
ENABLE PORT B COMPARATOR:
A one enables the comparison of the Port B Byte Count register with the Port B Byte Comparator
register, allowing the Port B Comparator Interrupt to be set and the chip to pause. A zero disables the Port
B Byte Comparator register and prohibits the Port B Comparator Interrupt.
CLEAR INTERFACE:
Writing a one creates a pulse, which clears the Port B Interface. Writing a zero has no effect on the Port
B Interface. This bit is always zero when it is read. This bit is intended to be used in Port B slave input
or output and master output modes. The CLEAR INTERFACE bit is intended to be used only when the
chip has paused after end of record, or paused because the Port A or Port B end of transfer has occurred.
CLEAR BYTE COUNTER:
Writing a one creates a pulse, which clears the Port B Byte Count register. Writing a zero has no effect
on the Port B Byte Count register. This bit is always zero when it is read.
ENABLE PARITY:
A one enables parity on DBPTY[1:0] when Port B is in 16 bit mode, and on DBPTY[0] when Port B is
in 8 bit mode. Writing a zero disables parity on Port B. This bit is undefined when the chip is reset from
the RESETN pin.
ODD PARITY:
A one selects odd parity on Port B. A zero selects even parity on Port B. This bit is undefined when the
chip is reset from the RESETN pin.
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3.11 PORT B STATUS: ADDRESS 0C HEX - READ ONLY
bit7
bit6
res
DATA7TO0
0x0C
bit5
bit4
bit3
EOR COUNT[1:0]
bit2
bit1
bit0
INTERFACE BYTE COUNT[3:0]
res -Reserved. Bit must always be written with a zero. It reads back a zero.
DATA7TO0:
When Port B is in 16 bit mode, the DATA7TO0 bit shows whether the last DMA cycle of a data transfer
sequence out of Port B contains one or two valid bytes. This occurs for the last byte of the last record,
as determined by the Record Count register. If the last byte of the last record is the first byte in the
sequence to output a word, that byte is output on DB[7:0], the data on DB[15:8] is undefined, and the
DATA7TO0 bit is set. If the last byte of the last record is the second byte in the sequence to output a
word, the second to last byte is output on DB[7:0], the last byte is output on DB[15:8], and the
DATA7TO0 bit is cleared. The DATA7TO0 bit is cleared during all DMA cycles into Port B, during all
DMA cycles when Port B is in 8 bit mode, and when the chip is reset from the RESETN pin.
EOR COUNT[1:0]:
The EOR COUNT[1:0] bits show the number of bytes with active end of record flags contained in the
Port B Interface. These bits operate in compression, compression flush, pass through A to B modes.
These bits are cleared to zero when a one is written to the CLEAR INTERFACE bit in Port B Control
1 register, or when the reset or decompression or decompression output disabled or pass through B to A
code is programmed to the DCLZ MODE bits in the DCLZ Control register, or when the chip is reset
by the RESETN pin. During data transfers, these bits should only be read when the PAUSED bit in the
DCLZ Status register is a one.
INTERFACE BYTE COUNT[3:0]:
The INTERFACE BYTE COUNT[3:0] bits show the number of bytes that are held in the Port B
Interface. These bits are cleared to zero when a one is written to the CLEAR INTERFACE bit in Port B
Control 1 register, or when the reset code is programmed to the DCLZ MODE bits in the DCLZ Control
register, or when the chip is reset by the RESETN pin. During data transfers, these bits should only be
read when the PAUSED bit in the DCLZ Status register is a one.
3.12 PORT B BYTE COUNT: ADDRESS 0D,0E,0F HEX - READ/WRITE
Least Significant Byte (address 0D hex):
bit7
bit6
bit5
bit4
bit6
bit5
bit4
0x0F
bit6
bit5
bit1
bit0
bit3
bit2
bit1
bit0
bit2
bit1
bit0
[15:8]
0x0E
Most Significant Byte (address 0F hex):
bit7
bit2
[7:0]
0x0D
Middle Byte (address 0E hex):
bit7
bit3
bit4
bit3
[23:16]
The Port B Byte Count register counts the number of bytes that are transferred by the Port B DMA State
Machine. This register counts in compression, compression flush, decompression, decompression output
disabled, pass through A to B, and pass through B to A modes. The register is cleared to zero when a one is
written to the CLEAR BYTE COUNTER bit in Port B Control 1 register, or when the chip is reset by the
RESETN pin. During data transfers, this register should only be written or read when the PAUSED bit in the
DCLZ Status register is a one. This counter rolls over from FFFFFF hex to 000000.
Page 20 of 45
PS3210B-1299
advancedhardwarearchitectures
3.13 PORT B BYTE COMPARATOR: ADDRESS 10,11,12 HEX - READ/WRITE
Least Significant Byte (address 10 hex):
bit7
bit6
bit5
bit4
bit6
bit5
bit4
bit6
bit5
bit1
bit0
bit3
bit2
bit1
bit0
bit2
bit1
bit0
[15:8]
0x11
Most Significant Byte (address 12 hex):
bit7
bit2
[7:0]
0x10
Middle Byte (address 11 hex):
bit7
bit3
bit4
bit3
[23:16]
0x12
The Port B Byte Comparator register is used to pause the chip after a programmed amount of data has
been transferred across the Port B data bus pins, DB[15:0]. This register operates in compression,
compression flush, decompression, decompression output disabled, pass through A to B, and pass through
B to A modes. When the Port B DMA state machine updates the 24 bit Port B Byte Count register, this
updated value is compared to the 24 bit Port B Byte Comparator register. If the updated Port B Byte Count
value equals or exceeds the Port B Comparator value, the Port B Comparator Interrupt is set, and the chip
is immediately paused. This function is enabled by the ENABLE PORT B COMPARATOR bit in Port B
Control 1 register. If the ENABLE PORT B COMPARATOR bit is zero (inactive), the Port B Byte
Comparator register is unused, and the Port B Comparator Interrupt and pause functions are disabled.
During data transfers, this register should only be written or read when the PAUSED bit in the DCLZ Status
register is a one.
3.14 RECORD LENGTH: ADDRESS 13,14,15 HEX - READ/WRITE
Least Significant Byte (address 13 hex):
bit7
bit6
bit5
bit4
bit6
bit5
bit4
0x15
bit6
bit5
bit1
bit0
bit3
bit2
bit1
bit0
bit2
bit1
bit0
[15:8]
0x14
Most Significant Byte (address 15 hex):
bit7
bit2
[7:0]
0x13
Middle Byte (address 14 hex):
bit7
bit3
bit4
bit3
[23:16]
The twenty four bit Record Length register is used to count the number of bytes of uncompressed data
that comprise one record. The counter operates in compression, pass through A to B, and pass through B to
A modes. Note that in decompression, the end of record codewords in the compressed data stream
determine where the end of records occur. The Record Length register contains a binary down counter. The
initial value of the record length is written into the Record Length register. The current value of the down
counter is transferred during read cycles from this register. This register is used in conjunction with the
Record Count register. When the Record Length register reaches zero, the Record Count register is
decremented. If the Record Count register is greater than zero, the Record Length register down counter is
reloaded, to allow another record to be processed automatically. The three bytes of the Record Count
register should be read from, or written to, only after the reset code has been written to the DCLZ Control
bits in the DCLZ Control register, or when the PAUSED bit in the DCLZ Status register is one. The Record
Length register is undefined when the chip is reset by the RESETN pin.
PS3210B-1299
Page 21 of 45
Advanced
advancedhardwarearchitectures
Hardware Architectures, Inc.
3.15 RECORD COUNT: ADDRESS 16,17,18 HEX - READ/WRITE
Least Significant Byte (address 16 hex):
bit7
bit6
bit5
bit4
bit6
bit5
bit4
bit6
bit5
bit1
bit0
bit3
bit2
bit1
bit0
bit2
bit1
bit0
[15:8]
0x17
Most Significant Byte (address 18 hex):
bit7
bit2
[7:0]
0x16
Middle Byte (address 17 hex):
bit7
bit3
bit4
bit3
[23:16]
0x18
The twenty four bit Record Count register is used to count the number of records in a multi-record
transfer. This register is used in compression, compression flush, decompression, decompression output
disabled, pass through A to B, and pass through B to A modes. The Record Count and Record Length
registers allow multiple records to be processed without processor intervention. If only one record is to be
compressed, then the Record Count register should be initialized to one. The initial value of the record
count is written into the Record Count register. The Record Count register is a binary down counter. The
current value of the down counter is transferred during read cycles from this register. The three bytes of the
Record Count register should be read from, or written to, only after the reset code has been written to the
DCLZ Control bits in the DCLZ Control register, or when the PAUSED bit in the DCLZ Status register is
one. The Record Count register is undefined when the chip is reset by the RESETN pin.
3.16 INTERRUPT STATUS: ADDRESS 19 HEX - READ ONLY
bit7
0x19
bit6
res
bit5
bit4
bit3
bit2
bit1
bit0
PORT B
PORT A
PORT B
DCLZ
PORT B
PORT A
END OF
END OF
COMPARATOR ERROR
PARITY
PARITY
TRANSFER TRANSFER
INT
INT
ERROR INT ERROR INT
INT
INT
res -Reserved. Bit reads back a zero.
PORT B COMPARATOR INT:
The PORT B COMPARATOR INTERRUPT bit is set after a byte is transferred over the Port B data bus
pins, when the Port B Byte Count register is updated and then equals or exceeds the value in the Port B
Byte Comparator register. The PORT B COMPARATOR INT bit is cleared to zero when the chip is reset
from the RESETN pin. Note that the PORT B COMPARATOR INTERRUPT bit can only be set when
the ENABLE PORT B COMPARATOR bit in Port B Control 1 register is one (active).
DCLZ ERROR INT:
The DCLZ ERROR INTERRUPT bit is set when any of the following errors occur during
decompression or decompression output disabled modes: a grow codeword was read when the codeword
size was already at the maximum 12 bits in length; an unknown codeword was read; a codeword was
read which corresponded to greater than the maximum limit of 128 uncompressed bytes. Once the DCLZ
ERROR INT bit is set, the reset code should be written to the DCLZ MODE bits in the DCLZ Control
register, followed by writing a one to the CLEAR DCLZ ERROR bit in the Interrupt Clear register. The
DCLZ ERROR INT bit is cleared to zero when the chip is reset from the RESETN pin.
PORT B PARITY ERROR INT:
The PORT B PARITY ERROR INTERRUPT is set when Port B parity is enabled, and erroneous parity
is detected when data is read into Port B. Once the PORT B PARITY ERROR INT bit is set, the reset
code should be written to the DCLZ MODE bits in the DCLZ Control register, followed by writing a one
to the CLEAR PORT B PARITY ERROR bit in the Interrupt Clear register. The PORT B PARITY
ERROR INT bit is cleared to zero when the chip is reset from the RESETN pin.
Page 22 of 45
PS3210B-1299
advancedhardwarearchitectures
PORT A PARITY ERROR INT:
The PORT A PARITY ERROR INTERRUPT is set when Port A parity is enabled, and erroneous parity
is detected when data is read into Port A. Once the PORT A PARITY ERROR INT bit is set, the reset
code should be written to the DCLZ MODE bits in the DCLZ Control register, followed by writing a one
to the CLEAR PORT A PARITY ERROR bit in the Interrupt Clear register. The PORT A PARITY
ERROR INT bit is cleared to zero when the chip is reset from the RESETN pin.
PORT B END OF TRANSFER INT:
The PORT B END OF TRANSFER INTERRUPT is used in compression, compression flush, and pass
through A to B modes. The interrupt occurs when the Record Count register and the Record Length register
are both zero, and the last byte of the last record has been transferred through the Port B interface. The
PORT B END OF TRANSFER INT bit is cleared to zero when the chip is reset from the RESETN pin.
PORT A END OF TRANSFER INT:
The PORT A END OF TRANSFER INTERRUPT is used in decompression, decompression output
disabled, and pass through B to A modes. The interrupt occurs in pass through B to A mode when the
Record Count register and the Record Length register are both zero, and the last byte of the last record
has been transferred through the Port A interface. The interrupt occurs in decompression and
decompression output disabled modes when the Record Count register is zero, and the last byte of the
last record has been transferred through the Port A interface. The PORT A END OF TRANSFER INT
bit is cleared to zero when the chip is reset from the RESETN pin.
3.17 INTERRUPT CLEAR: ADDRESS 19 HEX - WRITE ONLY
bit7
0x19
bit6
res
bit5
bit4
bit3
bit2
bit1
bit0
CLEAR
CLEAR
CLEAR
CLEAR
CLEAR
PORT B
PORT A
CLEAR PORT B
DCLZ
PORT B
PORT A
END OF
END OF
COMPARATOR
ERROR
PARITY
PARITY
TRANSFER TRANSFER
INT
INT
ERROR INT ERROR INT
INT
INT
res -Reserved. Bit reads back a zero.
All other bits in the register clear the interrupt bits in the Interrupt Status register. Writing a one to a
clear bit creates a pulse which clears the corresponding bit in the Interrupt Status register. Writing a zero to
a clear bit has no effect on the corresponding interrupt bit in the Interrupt Status register.
3.18 INTERRUPT DISABLE: ADDRESS 1A HEX - READ/WRITE
bit7
0x1A
bit6
res
bit5
bit4
bit3
bit2
bit1
bit0
DISABLE
DISABLE
DISABLE
DISABLE DISABLE
DISABLE
PORT B
PORT A
PORT B
DCLZ
PORT B
PORT A
END OF
END OF
COMPARATOR ERROR
PARITY
PARITY
TRANSFER TRANSFER
INT
INT
ERROR INT ERROR INT
INT
INT
res -Reserved. Bit reads back a zero.
All other bits in the register gate the interrupts between the Interrupt Status register and the INTN/INT
pin of the chip. Writing a one to a disable bit disables the corresponding interrupt. Writing a zero to a disable
bit enables the corresponding interrupt. Note that software polling is possible by disabling all the interrupts,
and using the Interrupt Status register and Interrupt Clear registers. The disable bits are one when the chip
is reset by the RESETN pin.
3.19 IDENTIFICATION: ADDRESS 1F HEX - READ ONLY
This register provides an identification code for firmware to read. For the AHA3210B, the
identification code is 0x41.
PS3210B-1299
Page 23 of 45
Advanced
advancedhardwarearchitectures
Hardware Architectures, Inc.
4.0
PIN DESCRIPTION
This section describes the function of the pins of the chip. A low active signal has an “N” appended to
the end of the signal name.
4.1
PROCESSOR INTERFACE
NAME
TYPE
PROCMODE
I
A[4:0]
I
RWN/IOWRN
I
CSN
I
PORTACSN
I
DSN/IORDN
I
Page 24 of 45
DESCRIPTION
PROCessor MODE select pin. Connect to VDD to select a processor interface
controlled by a data strobe (DSN), a read/write signal (RWN), with an open
drain data transfer acknowledge output (DTACKN), and an open drain, low
active interrupt (INTN). Connect to GND to select processor interface
controlled by an I/O read strobe (IORDN), an I/O write strobe (IOWRN), with
a high active ready output (READY), and a high active interrupt (INT).
Address for registers accessed through the processor interface.
When the PROCMODE pin is a high voltage this signal functions as
ReadWriteN. A high voltage denotes a processor read cycle. A low voltage
denotes a write cycle. When the PROCMODE pin is a low voltage, this signal
functions as I/O WRiteN. A low voltage denotes a processor I/O write cycle is
occurring, and the rising edge denotes the end of the processor access. As
IOWRN, this signal is used as a strobe signal, and must not glitch.
Chip SelectN. When the PROCMODE pin is a high voltage, a low voltage on
this signal and on the DSN/IORDN signal denotes the start of a processor
access to a register internal to the chip. This signal can glitch when DSN/
IORDN is a high voltage. It must not glitch once DSN/IORDN is a low voltage.
When the PROCMODE pin is a low voltage, a low voltage on CSN and either
DSN/IORDN or RWN/IOWRN denotes the start of a processor access to a
register internal to the chip. The CSN signal can glitch when both DSN/IORDN
and RWN/IOWRN are at high voltage. CSN must not glitch once DSN/IORDN
or RWN/IOWRN are at low voltage. CSN is active low.
Port A Chip SelectN. When the PROCMODE pin is a high voltage, a low
voltage on this signal and on the DSN/IORDN signal denotes the start of a
processor access to a peripheral chip on Port A. This signal can glitch when
DSN/IORDN is a high voltage. It must not glitch once DSN/IORDN is a low
voltage. When the PROCMODE pin is a low voltage, a low voltage on
PORTACSN and either DSN/IORDN or RWN/IOWRN denotes the start of a
processor access to a peripheral chip on Port A. The PORTACSN signal can
glitch when both DSN/IORDN and RWN/IOWRN are at high voltage.
PORTACSN must not glitch once DSN/IORDN or RWN/IOWRN are at low
voltage. PORTACSN is active low.
When the PROCMODE pin is a high voltage, this pin functions as DataStrobeN.
Allow voltage on this signal and on the CSN signal denotes the start of a
processor access. The rising edge of DSN/IORDN denotes the end of a
processor access. This signal is used as a strobe signal. It must not glitch. DSN/
IORDN is active low. When the PROCMODE pin is a low voltage, this pin
functions as I/O ReaDN. A low voltage denotes a processor I/O read cycle is
occurring, and the rising edge denotes the end of the processor access. As
IORDN, this signal is used as a strobe signal, and must not glitch.
PS3210B-1299
advancedhardwarearchitectures
NAME
DTACKN/READY
D[7:0]
TYPE
O
I/O
INTN/INT
O
CLK
RESETN
I
I
TRISTATEN
I
TEST[3:0]
I
PS3210B-1299
DESCRIPTION
When the PROCMODE pin is a high voltage, this signal functions as a Data
Transfer Acknowledge open drain output. A low voltage indicates that
processor data has been latched on processor write cycles. On read cycles, a low
voltage indicates that data is valid on the D[7:0] bus for the processor to latch.
When the PROCMODE pin is a low voltage, this signal functions as a READY
output. At the beginning of processor cycles, this output is driven to a low
voltage, indicating that the chip is not ready. The pin is driven high when data
is valid on the D[7:0] bus during read cycles, and after data has been internally
latched during write cycles. This signal is tristated when processor cycles are
inactive. The reset state of this pin is high impedance.
Bidirectional processor data bus, to access all registers internal to the chip. The
reset state of these pins is high impedance.
When the PROCMODE pin is a high voltage, this signal functions as a low
active interrupt, with an open drain output. A low voltage indicates that an
internal interrupt is active. The reset state of the pin in this mode is tristate.
When the PROCMODE pin is a low voltage, this signal functions as a high
active interrupt. A high voltage denotes that an internal interrupt is active. In this
mode, the pin is never tristated. The reset state of the pin in this mode is low
voltage.
Input Clock.
A low voltage on this pin will reset the chip.
A low voltage on this pin will tristate all I/O and output signal drivers, and will
disable the pad pullup resistors on all other pins. The TRISTATEN pin has a
pullup resistor on the pin. For normal operation, it should be left open circuited
on the PC board.
Test input pins. These pins should always be grounded on the PC board.
Page 25 of 45
Advanced
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Hardware Architectures, Inc.
4.2
PORT A INTERFACE
NAME
TYPE
DREQA
I/O
DACKA
I/O
ACSN
O
AWE
I/O
AOE
I/O
DA[15:0]
I/O
DAPTY[1:0]
I/O
Page 26 of 45
DESCRIPTION
Port A DMA request pin, with programmable polarity. This pin is an output
when Port A is a DMA bus master, and an input when Port A is a DMA bus
slave. This signal pulses once for every DMA transfer into or out of Port A in
master mode. This signal may be held active for multiple transfers in slave
mode. The reset state of this pin is high impedance.
Port A DMA channel DMA acknowledge pin, with programmable polarity. This
pin is an input when Port A is a DMA bus master, and an output when Port A is
a DMA bus slave. This signal pulses once for every DMA transfer into or out of
Port A. The reset state of this pin is high impedance.
Port A peripheral chip select pin. This signal pulses low during read and write
accesses to registers to a peripheral chip connected to Port A. The reset state of
this pin is high voltage.
Port A write enable pin, with programmable polarity. This pin pulses during
each DMA transfer into Port A. AWE is an input pin when Port A is a DMA bus
master, and is used by an external DMA bus slave to strobe data into Port A.
AWE is an output pin when Port A is a DMA bus slave, and is used to enable an
external DMA bus master’s data output drivers. This pin can be enabled/
disabled with the AWE ENABLE bit in Port A Control 0 register. The reset state
of this pin is high impedance.
Port A output enable pin, with programmable polarity. This pin pulses during
each DMA transfer out of Port A. AOE is an input pin when Port A is a DMA
bus master, and is used by an external DMA bus slave to enable Port A data
output drivers. AOE is an output pin when Port A is a DMA bus slave, and is
used to latch data into an external DMA bus master. This pin can be enabled/
disabled with the AOE ENABLE bit in Port A Control 0 register. The reset state
of this pin is high impedance.
Port A bidirectional data bus. These pins have internal 10K ohm pullup
resistors, which are enabled by the ENABLE DA PULLUP bit in Port A Control
0 register. When Port A is in 16 bit mode, data is transferred on DA[15:0]. In
reference to a byte ordered data flow, the first byte is transferred on DA[7:0] and
the second byte on DA[15:8]. When Port A is in 8 bit mode, data is transferred
on DA[7:0]. The reset state of these pins has the output drivers tristated, and the
internal pullup resistors disabled.
Bidirectional parity bits for the DA[15:0] bus. Parity can be enabled/disabled,
and odd/even parity programmed through Port A Control 1 register. DAPTY[1]
provides parity for the DA[15:8] bus. DAPTY[0] provides parity for the
DA[7:0] bus. If Port A parity is disabled, these pins are always tristated. These
pins have an internal 10K ohm pullup resistors, which are enabled with the
ENABLE DAPTY PULLUP bit in Port A Control 0 register. The reset state of
these pins is high impedance, with the internal pullup resistors disabled.
PS3210B-1299
advancedhardwarearchitectures
4.3
PORT B INTERFACE
NAME
TYPE
DREQB
I/O
DACKB
I/O
BWE
I/O
BOE
I/O
DB[15:0]
I/O
DBPTY[1:0]
I/O
PS3210B-1299
DESCRIPTION
Port B DMA request pin, with programmable polarity. This pin is an output
when Port B is a DMA bus master, and an input when Port B is a DMA bus
slave. This signal pulses once for every DMA transfer into or out of Port B in
master mode. This signal may be held active for multiple transfers in slave
mode. The reset state of this pin is high impedance.
Port B DMA channel DMA acknowledge pin, with programmable polarity. This
pin is an input when Port B is a DMA bus master, and an output when Port B is
a DMA bus slave. This signal pulses once for every DMA transfer into or out of
Port B. The reset state of this pin is high impedance.
Port B write enable pin, with programmable polarity. This pin pulses during
each DMA transfer into Port B. BWE is an input pin when Port B is a DMA bus
master, and is used by an external DMA bus slave to strobe data into Port B.
BWE is an output pin when Port B is a DMA bus slave, and is used to enable an
external DMA bus master’s data output drivers. This pin can be enabled/
disabled with the BWE ENABLE bit in Port B Control 0 register. The reset state
of this pin is high impedance.
Port B output enable pin, with programmable polarity. This pin pulses during
each DMA transfer out of Port B. BOE is an input pin when Port B is a DMA
bus master, and is used by an external DMA bus slave to enable Port B data
output drivers. BOE is an output pin when Port B is a DMA bus slave, and is
used to latch data into an external DMA bus master. This pin can be enabled/
disabled with the BOE ENABLE bit in Port B Control 0 register. The reset state
of this pin is high impedance.
Port B bidirectional data bus. These pins have internal 10K ohm pullup
resistors, which are enabled by the ENABLE DB PULLUP bit in Port B Control
0 register. When Port B is in 16 bit mode, data is transferred on DB[15:0]. In
reference to a byte ordered data flow, the first byte is transferred on DB[7:0] and
the second byte on DB[15:8]. When Port B is in 8 bit mode, data is transferred
on DB[7:0]. The reset state of these pins has the output drivers tristated, and the
internal pullup resistors disabled.
Bidirectional parity bits for the DB[15:0] bus. Parity can be enabled/disabled,
and odd/even parity programmed through Port B Control 1 register. DBPTY[1]
provides parity for the DB[15:8] bus. DAPTY[0] provides parity for the
DB[7:0] bus. If Port B parity is disabled, these pins are always tristated. These
pins have an internal 10K ohm pullup resistors, which are enabled with the
ENABLE DBPTY PULLUP bit in Port B Control 0 register. The reset state of
these pins is high impedance, with the internal pullup resistors disabled.
Page 27 of 45
Advanced
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Hardware Architectures, Inc.
5.0
PINOUT
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
GND
DA[8]
DA[9]
DA[10]
VDD
VDD
GND
DA[11]
GND
DA[12]
DA[13]
DA[14]
DA[15]
DAPTY[1]
CLK
VDD
VDD
GND
GND
DREQA
DACKA
AWE
AOE
ACSN
GND
VDD
D[7]
D[6]
D[5]
D[4]
Figure 11: Pinout Diagram
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
AHA3210B-020 PQC
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
D[3]
D[2]
D[1]
GND
VDD
D[0]
INTN/INT
DTACKN/READY
VDD
GND
RESETN
TEST[3]
TEST[2]
TEST[1]
TEST[0]
TRISTATEN
PROCMODE
PORTACSN
DSN/IORDN
RWN/IOWRN
DB[7]
DBPTY[0]
GND
DB[8]
VDD
GND
DB[9]
DB[10]
VDD
DB[11]
GND
DB[12]
DB[13]
DB[14]
DB[15]
DBPTY[1]
VDD
GND
DREQB
DACKB
BWE
BOE
VDD
GND
A[0]
A[1]
A[2]
A[3]
A[4]
CSN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DAPTY[0]
DA[7]
DA[6]
VDD
DA[5]
GND
DA[4]
DA[3]
DA[2]
DA[1]
DA[0]
DB[0]
DB[1]
DB[2]
DB[3]
DB[4]
GND
DB[5]
VDD
DB[6]
Page 28 of 45
PS3210B-1299
advancedhardwarearchitectures
6.0
ELECTRICAL SPECIFICATIONS
6.1
ABSOLUTE MAXIMUM RATINGS
SYMBOL
Vdd
Vpin
PARAMETER
Power supply voltage
Voltage applied to any pin
MIN
MAX
UNITS
-0.5
7.0
7.0
Volts
Volts
Absolute maximum voltage ratings are for voltage excursions which are transitory in nature.
6.2
RECOMMENDED OPERATING CONDITIONS
SYMBOL
Vdd
Ta
6.2.1
PARAMETER
Power supply voltage
Operating temperature
MAX
UNITS
4.75
0
5.25
70
Volts
Degrees C
DC SPECIFICATIONS
SYMBOL
PARAMETER
Vol
Voh
Iil
Iih
Iozl
Iozh
Idd
Idd
Idd
Input low voltage
CLK
All other inputs
Input high voltage
CLK
All other inputs
All output low voltage
Output high voltage
Input low current
Input high current
Output tristate low current
Output tristate high current
Active Idd current, Compression
Active Idd current, Decompression
Supply current (static)
Idd
Standby current
Vil
Vih
CONDITIONS
Ioh
MIN
MAX
UNITS
0.8
Volts
2.0
Iol = 4.0 mAmps
Ioh = 4.0 mAmps
Vin = 0 Volts
Vin = VDD Volts
Vout 0 Volts
Vout VDD Volts
Compression, CR=1:1
Decompression, CR=1:1
Chip paused, 20 MHz
clock
DTACKN/READY, INTN/INT
All other inputs
DTACKN/READY, INTN/INT
All other inputs
Iol
6.2.2
MIN
Volts
0.4
200
150
1.0
Volts
Volts
µAmps
µAmps
µAmps
µAmps
mAmps
mAmps
mAmps
20
mAmps
2.4
-10
10
10
-10
8
4
8
4
mAmps
mAmps
AC SPECIFICATIONS
PIN NAMES
DTACKN/READY, D[7:0], INTN/INT
DREQA, DACKA, AOE, DA[15:0], DAPTY[1:0], ACSN, DREQB,
DACKB, BOE, BWE, DB[15:0], DBPTY[1:0]
PS3210B-1299
MAXIMUM CAPACITIVE LOAD
50 pF
50 pF
Page 29 of 45
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6.2.3
PIN CAPACITANCE
SYMBOL
Cin
Cout
Cio
PARAMETER
Input capacitance
Output capacitance
I/O capacitance
MAX
UNITS
10
10
10
pF
pF
pF
Figure 12: Dynamic Current - Idd vs. Compression Ratio
Compression - 20 MHz clock, Vdd = 5.0V
200.0
180.0
Idd (ma)
160.0
140.0
120.0
100.0
0.0
5.0
10.0
15.0
Comp Ratio
Page 30 of 45
PS3210B-1299
advancedhardwarearchitectures
7.0
TIMING SPECIFICATIONS
Figure 13: Clock Timing
1
3
2
CLOCK
4
Table 8:
Clock Timing Specification
NUMBER
1
2
3
4
5
5
PARAMETER
MIN
CLK period
CLK low pulsewidth
CLK high pulsewidth
CLK rise time
CLK fall time
MAX
50
20
20
5
5
UNITS NOTES
nsec
nsec
nsec
nsec
nsec
1
1
1
2, 3
2, 3
Notes:
1) All AC Timings are referenced to 1.4 Volts.
2) Rise and fall times are between 0.6 Volts and 2.4 Volts.
3) Refer to AHA Application Brief (ABDC15-0798) “AHA3210B Clock Specification Clarification” for rise/fall
conditions.
Figure 14: Reset Timing - Power Up
3
CLK
RESETN
Refer to Table 9 for Timing Specification
Figure 15: Reset Timing
1
CLK
2
2
RESETN
Table 9:
Reset Timing Specifications
NUMBER
1
2
3
PARAMETER
RESETN low pulsewidth
RESETN setup to CLK rise
RESETN power up period
MIN
5
10
5
MAX
UNITS NOTES
clocks
nsec
clocks
1
2
Notes:
1) The RESETN signal can be asynchronous to the CLK signal. It is internally synchronized to the rising edge of CLK.
2) RESETN signal must stay low until a minimum of 5 clocks occur. See Figure 14.
PS3210B-1299
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Figure 16: Processor Read Cycle - DSN, RWN Controlled
t5
t0
t1
t2
t3
t4
t5
CLK
1
3
CSN
1
1
DSN/IORDN
4
1
RWN/IOWRN
1
5
A[4:0]
2
D[7:0]
tristate
DTACKN/READY
tristate
6
tristate
6
2
Table 10:
tristate
Processor Read Cycle Timings - DSN, RWN Controlled
NUMBER
PARAMETER
MIN
1
2
3
4
5
6
CSN, DSN/IORDN, RWN/IOWRN and A[4:0] setup to CLK rise
CLK rise to D[7:0] valid and DTACKN/READY low
CSN hold from DSN/IORDN high
RWN/IOWRN hold from DSN/IORDN high
A[4:0] hold from DSN/IORDN high
DSN/IORDN high to D[7:0] and DTACKN/READY high-Z
10
0
0
0
0
0
MAX
20
20
UNITS
ns
ns
ns
ns
ns
ns
Notes:
1) CSN, DSN/IORDN and RWN/IOWRN are assumed to be asynchronous with respect to the AHA3210B clock. These
signals are synchronized internally to the AHA3210B clock to drive internal state machines.
2) CSN may be held low during back-to-back register access cycles.
3) If a strobe to clock setup is missed at the beginning of an access cycle, then the access cycle begins on the following
clock cycle at which the specification is met.
4) If a strobe to clock setup is missed at the end of an access cycle, then the access cycle terminator is delayed until
the low to high transition of the strobe meets the specified setup time.
Page 32 of 45
PS3210B-1299
advancedhardwarearchitectures
Figure 17: Processor Write Cycle - DSN, RWN Controlled
t5
t0
t1
t3
t2
t4
t5
CLK
3
1
CSN
1
1
DSN/IORDN
4
1
RWN/IOWRN
1
5
1
7
A[4:0]
D[7:0]
tristate
DTACKN/READY
tristate
2
Table 11:
2
3
4
5
6
7
6
tristate
Processor Write Cycle Timings - DSN, RWN Controlled
NUMBER
1
tristate
PARAMETER
CSN, DSN/IORDN, RWN/IOWRN, A[4:0] and D[7:0] setup to
CLK rise
CLK rise to DTACKN/READY low
CSN hold from DSN/IORDN high
RWN/IOWRN hold from DSN/IORDN high
A[4:0] hold from DSN/IORDN high
DSN/IORDN high to DTACKN/READY high-Z
D[7:0] hold from DSN/IORDN high
MIN
MAX
10
0
0
0
0
0
0
UNITS
ns
20
20
ns
ns
ns
ns
ns
ns
Notes:
1) CSN, DSN/IORDN and RWN/IOWRN are assumed to be asynchronous with respect to the AHA3210B clock. These
signals are synchronized internally to the AHA3210B clock to drive internal state machines.
2) CSN may be held low during back-to-back register access cycles.
3) If a strobe to clock setup is missed at the beginning of an access cycle, then the access cycle begins on the following
clock cycle at which the specification is met.
4) If a strobe to clock setup is missed at the end of an access cycle, then the access cycle terminator is delayed until
the low to high transition of the strobe meets the specified setup time.
PS3210B-1299
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Figure 18: Processor Read Cycle - IORDN Controlled
t5
t0
t1
t2
t3
t4
t5
CLK
1
3
CSN
1
1
DSN/IORDN
RWN/IOWRN
1
4
A[4:0]
5
2
D[7:0]
tristate
DTACKN/READY
tristate
tristate
2
Table 12:
NUMBER
1
2
3
4
5
2
5
tristate
Processor Read Cycle Timings - IORDN Controlled
PARAMETER
CSN, DSN/IORDN and A[4:0] setup to CLK rise
CSN and DSN/IORDN low to DTACKN/READY low;
CLK rise to D[7:0] valid and DTACKN/READY high
CSN hold from DSN/IORDN high
A[4:0] hold from DSN/IORDN high
DSN/IORDN high to D[7:0] and DTACKN/READY high-Z
MIN
MAX
10
0
0
0
0
UNITS
ns
20
ns
20
ns
ns
ns
Notes:
1) CSN and DSN/IORDN are assumed to be asynchronous with respect to the AHA3210B clock. These signals are
synchronized internally to the AHA3210B clock to drive internal state machines.
2) CSN may be held low during back-to-back register access cycles.
3) If a strobe to clock setup is missed at the beginning of an access cycle, then the access cycle begins on the following
clock cycle at which the specification is met.
4) If a strobe to clock setup is missed at the end of an access cycle, then the access cycle terminator is delayed until
the low to high transition of the strobe meets the specified setup time.
Page 34 of 45
PS3210B-1299
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Figure 19: Processor Write Cycle - IOWRN Controlled
t5
t0
t1
t2
t3
t4
t5
CLK
1
3
CSN
DSN/IORDN
1
1
RWN/IOWRN
1
4
A[4:0]
D[7:0]
tristate
DTACKN/READY
tristate
1
2
Table 13:
2
3
4
5
6
tristate
6
2
tristate
Processor Write Cycle Timings - IOWRN Controlled
NUMBER
1
5
PARAMETER
CSN, RWN/IOWRN, A[4:0] and D[7:0] setup to CLK rise
CSN and RWN/IOWRN low to DTACKN/READY low;
CLK rise to DTACKN/READY high
CSN hold from RWN/IOWRN high
A[4:0] hold from RWN/IOWRN high
D[7:0] hold from RWN/IOWRN high
RWN/IOWRN high to DTACKN/READY high-Z
MIN
MAX
10
0
0
0
0
0
UNITS
ns
20
ns
20
ns
ns
ns
ns
Notes:
1) CSN and RWN/IOWRN are assumed to be asynchronous with respect to the AHA3210B clock. These signals are
synchronized internally to the AHA3210B clock to drive internal state machines.
2) CSN may be held low during back-to-back register access cycles.
3) If a strobe to clock setup is missed at the beginning of an access cycle, then the access cycle begins on the following
clock cycle at which the specification is met.
4) If a strobe to clock setup is missed at the end of an access cycle, then the access cycle terminator is delayed until
the low to high transition of the strobe meets the specified setup time.
PS3210B-1299
Page 35 of 45
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Figure 20: Processor Read Cycle from Port A Peripheral - DSN, RWN Controlled
t6
t0
t1
t2
t3
t4
t5
t6
CLK
3
1
PORTACSN
1
1
DSN/IORDN
4
1
RWN/IOWRN
1
5
A[4:0]
7
7
7
7
ACSN
AWE
9
DA[7:0]
tristate
D[7:0]
tristate
DTACKN/READY
tristate
8
tristate
6
2
tristate
2
Table 14:
NUMBER
1
2
3
4
5
6
7
8
9
6
tristate
Processor Read Cycle Timings from Port A Peripheral - DSN, RWN Controlled
PARAMETER
PORTACSN, DSN/IORDN, RWN/IOWRN and A[4:0] setup to
CLK rise
CLK rise to D[7:0] valid and DTACKN/READY low
PORTACSN hold from DSN/IORDN high
RWN/IOWRN hold from DSN/IORDN high
A[4:0] hold from DSN/IORDN high
DSN/IORDN high to D[7:0] and DTACKN/READY high-Z
CLK rise to ACSN/AWE Valid
DA[7:0] setup to CLK fall
DA[7:0] hold from CLK fall
MIN
MAX
10
0
0
0
0
0
5
20
UNITS
ns
20
20
25
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1) PORTACSN, DSN/IORDN and RWN/IOWRN are assumed to be asynchronous with respect to the AHA3210B
clock. These signals are synchronized internally to the AHA3210B clock to drive internal state machines.
2) PORTACSN may be held low during back-to-back register access cycles.
3) If a strobe to clock setup is missed at the beginning of an access cycle, then the access cycle begins on the following
clock cycle at which the specification is met.
4) If a strobe to clock setup is missed at the end of an access cycle, then the access cycle terminator is delayed until
the low to high transition of the strobe meets the specified setup time.
Page 36 of 45
PS3210B-1299
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Figure 21: Processor Write Cycle to Port A Peripheral - DSN, RWN Controlled
t6
t0
t1
t2
t3
t4
t5
t6
CLK
1
PORTACSN
3
1
1
DSN/IORDN
4
1
RWN/IOWRN
1
5
1
7
A[4:0]
D[7:0]
tristate
DTACKN/READY
tristate
2
tristate
6
tristate
8
8
ACSN
8
8
AOE
8
DA[7:0]
Table 15:
2
3
4
5
6
7
8
tristate
Processor Write Cycle to Port A Peripheral Timings - DSN, RWN Controlled
NUMBER
1
8
tristate
PARAMETER
PORTACSN, DSN/IORDN, RWN/IOWRN, A[4:0] and D[7:0]
setup to CLK rise
CLK rise to DTACKN/READY low
PORTACSN hold from DSN/IORDN high
RWN/IOWRN hold from DSN/IORDN high
A[4:0] hold from DSN/IORDN high
DSN/IORDN high to DTACKN/READY high-Z
D[7:0] hold from DSN/IORDN high
CLK rise to ACSN/AOE, DA[7:0] valid
MIN
MAX
10
0
0
0
0
0
0
0
UNITS
ns
20
20
25
ns
ns
ns
ns
ns
ns
ns
Notes:
1) PORTACSN, DSN/IORDN and RWN/IOWRN are assumed to be asynchronous with respect to the AHA3210B
clock. These signals are synchronized internally to the AHA3210B clock to drive internal state machines.
2) PORTACSN may be held low during back-to-back register access cycles.
3) If a strobe to clock setup is missed at the beginning of an access cycle, then the access cycle begins on the following
clock cycle at which the specification is met.
4) If a strobe to clock setup is missed at the end of an access cycle, then the access cycle terminator is delayed until
the low to high transition of the strobe meets the specified setup time.
PS3210B-1299
Page 37 of 45
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Figure 22: Processor Read Cycle from Port A Peripheral - IORDN Controlled
t6
t0
t1
t2
t3
t4
t5
t6
CLK
1
3
PORTACSN
1
1
DSN/IORDN
4
1
RWN/IOWRN
1
5
A[4:0]
7
7
7
7
ACSN
AWE
9
8
DA[7:0]
tristate
D[7:0]
tristate
tristate
2
tristate
2
2
DTACKN/READY
Table 16:
NUMBER
1
2
3
4
5
6
7
7
9
6
6
tristate
tristate
Processor Read Cycle from Port A Peripheral Timings - IORDN Controlled
PARAMETER
PORTACSN, DSN/IORDN, RWN/IOWRN and A[4:0] setup to
CLK rise
PORTACSN and DSN/IORDN low to DTACKN/READY low;
CLK rise to D[7:0] valid and DTACKN/READY high
PORTACSN hold from DSN/IORDN high
RWN/IOWRN hold from DSN/IORDN high
A[4:0] hold from DSN/IORDN high
DSN/IORDN high to D[7:0] and DTACKN/READY high-Z
CLK rise to ACSN/AWE Valid
DA[7:0] setup to CLK fall
DA[7:0] hold from CLK fall
MIN
MAX
10
0
0
0
0
0
5
20
UNITS
ns
20
20
25
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1) PORTACSN, DSN/IORDN and RWN/IOWRN are assumed to be asynchronous with respect to the AHA3210B
clock. These signals are synchronized internally to the AHA3210B clock to drive internal state machines.
2) PORTACSN may be held low during back-to-back register access cycles.
3) If a strobe to clock setup is missed at the beginning of an access cycle, then the access cycle begins on the following
clock cycle at which the specification is met.
4) If a strobe to clock setup is missed at the end of an access cycle, then the access cycle terminator is delayed until
the low to high transition of the strobe meets the specified setup time.
Page 38 of 45
PS3210B-1299
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Figure 23: Processor Write Cycle to Port A Peripheral - IOWRN Controlled
t6
t0
t1
t2
t3
t4
t5
t6
CLK
1
3
PORTACSN
DSN/IORDN
1
1
RWN/IOWRN
1
4
A[4:0]
D[7:0]
tristate
DTACKN/READY
tristate
5
1
2
2
tristate
7
tristate
6
6
ACSN
6
6
AOE
6
DA[7:0]
Table 17:
6
tristate
tristate
Processor Write Cycle to Port A Peripheral Timings - IOWRN Controlled
NUMBER
PARAMETER
MIN
1
PORTACSN, RWN/IOWRN, A[4:0] and D[7:0] setup to CLK rise
PORTACSN and RWN/IOWRN low to DTACKN/READY low;
CLK rise to DTACKN/READY high
PORTACSN hold from RWN/IOWRN high
A[4:0] hold from RWN/IOWRN high
D[7:0] hold from RWN/IOWRN high
CLK rise to ACSN/AOE, DA[7:0] valid
RWN/IOWRN high to DTACKN/READY high-Z
10
2
3
4
5
6
7
0
0
0
0
0
0
MAX
UNITS
ns
20
ns
25
20
ns
ns
ns
ns
ns
Notes:
1) PORTACSN and RWN/IOWRN are assumed to be asynchronous with respect to the AHA3210B clock. These
signals are synchronized internally to the AHA3210B clock to drive internal state machines.
2) PORTACSN may be held low during back-to-back register access cycles.
3) If a strobe to clock setup is missed at the beginning of an access cycle, then the access cycle begins on the following
clock cycle at which the specification is met.
4) If a strobe to clock setup is missed at the end of an access cycle, then the access cycle terminator is delayed until
the low to high transition of the strobe meets the specified setup time.
PS3210B-1299
Page 39 of 45
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Figure 24: DMA Slave Transfer Timing for Data Into Port A,B
t1
t2
t3
t4
t1
t2
t3
t4
t1
CLK
CLK
1
1
DREQA
DREQB
2
2
2
2
DACKA
DACKB
3
3
3
3
AWE
BWE
4
DA[15:0]
DAPTY[1:0]
Table 18:
NUMBER
1
2
3
4
5
tristate
5
Data0
4
5
tristate
Data1
DB[15:0]
DBPTY[1:0]
DMA Slave Transfer Timing for Data Into Port A,B
PARAMETER
DREQA valid setup to CLK rise
CLK rise to DACKA valid
CLK rise to AWE valid
DA[15:0], DAPTY[1:0] setup to CLK fall
DA[15:0], DAPTY[1:0] hold from CLK fall
MIN
5
0
0
5
20
MAX UNITS NOTES
25
25
nsec
nsec
nsec
nsec
nsec
1
2
Notes:
1) The DREQA signal can be asynchronous to the CLK signal. It is internally synchronized to the rising edge of CLK.
The DREQA signal is polled at T1. If the setup time number 1 is met, the maximum data transfer rate will be
achieved.
2) If the AWE pin is programmed to be disabled, the pin will be tristated.
Port A and Port B have the same timing for their DMA interfaces. For Port B specifications, substitute
the Port B name for the corresponding Port A name.
The timing diagram is for a transfer of two consecutive DMA cycles. The signals DACKA, and AWE
are chip outputs. DREQA, DAPTY[1:0] and DA[15:0] are chip inputs. DREQA, DACKA, AWE are
programmed to be active high.
Page 40 of 45
PS3210B-1299
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Figure 25: DMA Slave Transfer Timing for Data Out of Port A,B
t1
t2
t3
t4
t1
t2
t3
t4
t1
CLK
CLK
1
1
DREQA
DREQB
2
2
2
2
DACKA
DACKB
3
3
3
3
AOE
BOE
4
DA[15:0]
DAPTY[1:0]
Table 19:
tristate
4
Data0
5
DB[15:0]
DBPTY[1:0]
Data1
DMA Slave Transfer Timing for Data Out of Port A,B
NUMBER
1
2
3
4
5
5
PARAMETER
DREQA valid setup to CLK rise
CLK rise to DACKA valid
CLK rise to AOE valid
CLK rise to DA[15:0], DAPTY[1:0] valid
CLK rise to DA[15:0], DAPTY[1:0] tristate
MIN
5
0
0
0
0
MAX UNITS NOTES
25
25
25
25
nsec
nsec
nsec
nsec
nsec
1
2
3
3, 4
Notes:
1) The DREQA signal can be asynchronous to the CLK signal. It is internally synchronized to the rising edge of CLK.
The signal DREQA is polled at T1. If the setup time number 1 is met, the maximum data transfer rate will be
achieved.
2) If the AOE pin is programmed to be disabled, the pin will be tristated.
3) If the ENABLE PARITY bit in Port A Control 1 register is zero (inactive), the DAPTY[1:0] pins will always be
tristated.
4) This specification has been proven by worst case timing simulations. It is not fully tested in production.
Port A and Port B have the same timing for their DMA interfaces. For Port B specifications, substitute
the Port B name for the corresponding Port A name.
The timing diagram is for a transfer of two consecutive DMA cycles. The signals DACKA, AOE,
DAPTY[1:0], and DA[15:0] are chip outputs. DREQA is a chip input. DREQA, DACKA, AOE are
programmed to be active high.
PS3210B-1299
Page 41 of 45
Advanced
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Figure 26: DMA Master Transfer Timing for Data Into Port A,B
t1
t2
t3
t4
CLK
CLK
1
1
DREQB
DREQA
2
3
4
DACKB
DACKA
6
5
7
8
BWE
AWE
9
DA[15:0]
DAPTY[1:0]
Table 20:
NUMBER
1
2
3
4
5
6
7
8
9
10
tristate
10
tristate
Valid
DB[15:0]
DBPTY[1:0]
DMA Master Transfer Timing for Data Into Port A,B
PARAMETER
CLK rise to DREQA high
DREQA high to DACKA high
DACKA high to DREQA low
DACKA low setup to CLK rise
DACKA high pulsewidth
DACKA high to AWE high
AWE high pulsewidth
AWE low to DACKA low
DA[15:0], DAPTY[1:0] setup to AWE fall
DA[15:0], DAPTY[1:0] hold from AWE fall
MIN
0
0
0
5
25
0
25
0
10
10
MAX UNITS NOTES
25
25
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
1
2
2
Notes:
1) The DACKA signal can be asynchronous to the CLK signal. It is internally synchronized to the rising edge of CLK.
If the setup time number 4 is met at T3, the maximum data transfer rate will be achieved.
2) If the AWE pin is programmed to be disabled, substitute the DACKA pin for the AWE pin in the timing
specifications.
3) If AWE is used as an input to the AHA3210B part it may be valid only during DACKA valid. This restriction also
applies to BWE being valid during DACKB.
Port A and Port B have the same timing for their DMA interfaces. For Port B specifications, substitute
the Port B name for the corresponding Port A name.
The signal DREQA is a chip output. DACKA, AWE, DAPTY[1:0] and DA[15:0] are chip inputs.
DREQA, DACKA, AWE are programmed to be active high.
Page 42 of 45
PS3210B-1299
advancedhardwarearchitectures
Figure 27: DMA Master Transfer Timing for Data Out of Port A,B
t1
t2
t3
t4
CLK
CLK
1
1
DREQB
DREQA
2
3
4
DACKB
DACKA
5
6
7
BOE
AOE
8
DA[15:0]
DAPTY[1:0]
Table 21:
tristate
tristate
Valid
DB[15:0]
DBPTY[1:0]
DMA Master Transfer Timing for Data Out of Port A,B
NUMBER
1
2
3
4
5
6
7
8
9
9
PARAMETER
CLK rise to DREQA high
DREQA high to DACKA high
DACKA high to DREQA low
DACKA low setup to CLK rise
DACKA high pulsewidth
DACKA high to AOE high
DACKA low to AOE low
AOE high to DA[15:0], DAPTY[1:0] valid
AOE low to DA[15:0], DAPTY[1:0] tristate
MIN
0
0
0
5
25
0
0
0
MAX UNITS NOTES
25
25
50
25
25
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
1
2
2
Notes:
1) The DACKA signal can be asynchronous to the CLK signal. It is internally synchronized to the rising edge of CLK.
If the setup time number 4 is met at T3, the maximum data transfer rate will be achieved.
2) If the AOE pin is programmed to be disabled, substitute the DACKA pin for the AOE pin in the timing
specifications.
Port A and Port B have the same timing for their DMA interfaces. For Port B specifications, substitute
the Port B name for the corresponding Port A name.
The signals DREQA, DAPTY[1:0], and DA[15:0] are chip outputs. DACKA, AOE, are chip inputs.
DREQA, DACKA, AOE are programmed to be active high.
PS3210B-1299
Page 43 of 45
Advanced
advancedhardwarearchitectures
Hardware Architectures, Inc.
8.0
PACKAGING
Figure 28: AHA3210B Package Specifications
F
G
AHA3210B-020 PQC
C
B
A
D
E
J
H
I
A
B
C
12.35 14.0±0.1 17.9±0.4
AHA3210B CHIP DIMENSIONS
D
E
F
G
H
18.85 20.0±0.1 23.9±0.4 0.65±0.12 0.15±0.050
I
J
0.3±0.1 2.75±0.10
Notes: All dimensions are in millimeters
Package type is 100 pin quad flat pack
Page 44 of 45
PS3210B-1299
advancedhardwarearchitectures
9.0
ORDERING INFORMATION
9.1
AVAILABLE PARTS
PART NUMBER
DESCRIPTION
AHA3210B-020 PQC 10 MBytes/sec DCLZ Data Compression Coprocessor IC
9.2
PART NUMBERING
AHA
3210
B-
020
P
Q
C
Manufacturer
Device
Number
Revision
Level
Speed
Designation
Package
Material
Package
Type
Test
Specification
Device Number:
3210
Revision Letter:
B
Package Material Codes:
P
Plastic
Package Type Codes:
Q Q - Quad Flat Pack
Test Specifications:
CCommercial0°C to +70°C
10.0 AHA RELATED TECHNICAL PUBLICATIONS
DOCUMENT #
DESCRIPTION
ABDC02
ABDC05
ABDC07
ABSTD1
ANDC01
ANDC04
ANDC05
ANDC07
AHA Application Brief – DCLZ Software Licensing Procedure
AHA Application Brief – Interfacing Requirements to CMOS Devices
AHA Application Brief – Compression Optimization in AHA3101 and AHA3210 Systems
AHA Application Brief – AHA Data Compression and Forward Error Correction Standards
AHA Application Note – Primer: Data Compression Lempel Ziv (DCLZ)
AHA Application Note – Data Management for the AHA3210B
AHA Application Note – AHA3210B Designer’s Guide
AHA Application Note – DCLZ Evaluation Software
AHA Application Note – Error Detection and Recovery in Data Compression System
ANDC09
Using AHA3210B
AHA Application Note – Compression Performance: DCLZ Algorithm on the
ANDC10
Calgary Corpus
GLGEN1
General Glossary of Terms
PB3101
AHA3101 Product Brief – DCLZ 2.5 MBytes/sec Data Compression Coprocessor IC
PB3210B
AHA3210B Product Brief – DCLZ 10 MBytes/sec Data Compression Coprocessor IC
PS3101
AHA3101 Product Specification – DCLZ 2.5 MBytes/sec Data Compression Coprocessor IC
“DCLZ Emerges as an Open Data Compression Standard,” article reprint Computer
RAECMA-0791
Technology Review, Summer 1991
DCEVAL
DCLZ Evaluation Software (Windows 3.1)
PS3210B-1299
Page 45 of 45