ETC AHA3422A

Product Specification
AHA3422 StarLite
16 MBytes/sec Lossless
Decompressor IC
2365 NE Hopkins Court
Pullman, WA 99163-5601
tel: 509.334.1000
fax: 509.334.9000
sales@aha.com
www.aha.com
advancedhardwarearchitectures
PS3422-0600
advancedhardwarearchitectures
Table of Contents
1.0 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Conventions, Notations and Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.0 System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 Data Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 DMA Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.3 Pad Word Handling in Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4 DMA Request Signals and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4.1 FIFO Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4.2 Request During an End-of-Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4.3 Request Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5 Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.6 Odd Byte Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.6.1 Input, Pad Bytes and Error Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.6.2 Output and Pad Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.7 Video Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.7.1 Video Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.8 Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.9 Decompression Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.10 Prearming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.11 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.12 Duplex Printing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.13 Blank Bands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.14 Low Power Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.15 Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.0 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 System Configuration 0, Address 0x00 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 System Configuration 1, Address 0x01 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3 Input FIFO Thresholds, Address 0x02 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.4 Output FIFO Thresholds, Address 0x03 - Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.5 Decompression Ports Status, Address 0x05 - Read Only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.6 Port Control, Address 0x06 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.7 Interrupt Status/Control 0, Address 0x07 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.8 Interrupt Mask 0, Address 0x09 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.9 Version, Address 0x0A - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.10 Decompression Record Length, Address 0x0C, 0x0D, 0x0E, 0x0F - Read/Write. . . . . . . . . . . . . . . . . . . . 18
4.11 Decompression Control, Address 0x18 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.12 Decompression Reserved, Address 0x1A, 0x3A - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.13 Decompression Line Length, Address 0x1C, 0x1D - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.14 Interrupt Status/Control 1, Address 0x27 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.15 Interrupt Mask 1, Address 0x29 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.16 Decompression Record Count, Address 0x2C, 0x2D - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.17 Pattern, Address 0x35 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.18 Decompression Control Prearm, Address 0x38 - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.19 Control, Address 0x3F - Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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5.0 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2 Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3 Video Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.4 System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.0 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.0 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.1 Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.2 Absolute Maximum Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.0 AC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.0 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.0 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.1 Available Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.2 Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
11.0 Related Technical Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Appendix A: Additional Timing Diagrams for DMA Mode Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Appendix B: Sequential Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Microprocessor Port Write (PROCMODE[1:0]=“01”). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Microprocessor Port Read (PROCMODE[1:0]=“01”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Microprocessor Port Write (PROCMODE[1:0]=“11”). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Microprocessor Port Read (PROCMODE[1:0]=“11”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=100 . . . . . . . . . . . . . . . . . . . . . . . 6
DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=100 . . . . . . . . . . . . . . . . . . . . . . . 6
DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition of DSC=100. . . . . . . . 6
DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition of DSC=100 . . . . . . . 7
DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition of DSC=100 . . . . . . . 7
DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition of DSC=100 . . . . . . . 7
FIFO Threshold Example (IFT=4, DSC=2, 1 Word Already in FIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Request vs. End-of-Record, Strobe Condition of DSC=010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Timing Diagram, Video Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Data Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Request Deasserts at EOR, Strobe Condition of DSC=0-3, 6-15; ERC=0 . . . . . . . . . . . . . . . . . . . . . . . 28
Request Deasserts at EOR, Strobe Condition of DSC=0-3, 6-15; ERC=1 . . . . . . . . . . . . . . . . . . . . . . . 29
Request Deasserts at EOR, Strobe Condition of DSC=4 or 5; ERC=0 . . . . . . . . . . . . . . . . . . . . . . . . . 29
Request Deasserts at EOR, Strobe Condition of DSC=4 or 5; ERC=1 . . . . . . . . . . . . . . . . . . . . . . . . . 29
Output Enable Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Video Output Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Microprocessor Interface Timing (PROCMODE[1]=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Microprocessor Interface Timing (PROCMODE[1]=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Power On Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=000 . . . . . . . . . . . . . . . . . . . . . . 37
DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=000 . . . . . . . . . . . . . . . . . . . . . . 37
DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition of DSC=000. . . . . . . 37
DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition of DSC=000 . . . . . . 38
DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition of DSC=000 . . . . . . 38
DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition of DSC=000 . . . . . . 38
DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=010 . . . . . . . . . . . . . . . . . . . . . . 39
DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=010 . . . . . . . . . . . . . . . . . . . . . . 39
DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition of DSC=010. . . . . . . 39
DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition of DSC=010 . . . . . . 40
DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition of DSC=010 . . . . . . 40
DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition of DSC=010 . . . . . . 40
DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=011 . . . . . . . . . . . . . . . . . . . . . . 41
DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=011 . . . . . . . . . . . . . . . . . . . . . . 41
DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition of DSC=011. . . . . . . 41
DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition of DSC=011 . . . . . . 42
DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition of DSC=011 . . . . . . 42
DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition of DSC=011 . . . . . . 42
DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=111 . . . . . . . . . . . . . . . . . . . . . . 43
DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=111 . . . . . . . . . . . . . . . . . . . . . . 43
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Tables
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iv
Data Bus and FIFO Sizes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Connection to Host Microprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Microprocessor Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Internal Strobe Conditions for DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data Port Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Request vs. EOR Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Output Enable Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Video Output Port Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Microprocessor Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Interrupt Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Clock Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Power On Reset Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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1.0
INTRODUCTION
AHA3422 is a lossless decompression
coprocessor IC for hardcopy systems on many
standard platforms. The device is targeted for high
throughput and high resolution hardcopy systems.
Multiple record counters, higher clock
frequency, advanced banding and duplex printing
features enhance this product from the first StarLite
introduction, AHA3410. Identical decompression
algorithm and similar firmware considerations ease
migration to this second generation device.
Blank band generation in real time and
prearming registers between records enable
advanced banding techniques. Bands may be in raw
uncompressed, compressed or blank format in the
frame buffer. The device processes all three formats
and outputs the raster data to the printer engine.
Appropriate registers are prearmed when switching
from one type to the next. Byte ordering allows full
reversal of the image data for duplex printing
support. A system may use multiple record counters
and End-of-Transfer interrupts to easily handle
pages partitioned into smaller records or bands.
This document contains functional description,
system configurations, register descriptions,
electrical characteristics and ordering information.
It is intended for system designers considering a
decompression coprocessor in their embedded
applications. Software simulation and an analysis of
the algorithm for printer and copier images of
various complexity are also available for
evaluation. A comprehensive Designer’s Guide
complements this document to assist with the
system design. Section 11.0 contains a list of related
technical publications.
1.1
CONVENTIONS, NOTATIONS AND
DEFINITIONS
– Active low signals have an “N” appended to the
end of the signal name. For example, CSN and
RDYN.
– A “bar” over a signal name indicates an inverse of
the signal. For example, SD indicates an inverse
of SD. This terminology is used only in logic
equations.
– “Signal assertion” means the output signal is
logically true.
– Hex values are represented with a prefix of “0x”,
such as Register “0x00”. Binary values do not
contain a prefix, for example, DSC=000.
– A range of signal names or register bits is denoted
by a set of colons between the numbers. Most
significant bit is always shown first, followed by
least significant bit. For example, VOD[7:0]
indicates signal names VOD7 through VOD0.
PS3422-0600
– A logical “AND” function of two signals is
expressed with an “&” between variables.
– Mega Bytes per second is referred to as MBytes/
sec or MB/sec.
– In referencing microprocessors, an x, xx or xxx is
used as suffix to indicate more than one
processor. For example, Motorola 68xxx
processor family includes various 68000
processors from Motorola.
– Reserved bits in registers are referred as “res”.
– REQN or ACKN refer to either DI, or DO
Request or Acknowledge signals, as applicable.
– NC in pinout description means “no connect”.
1.2
FEATURES
PERFORMANCE:
• 16 MBytes/sec maximum sustained data
throughput
• 132 MBytes/sec burst data rate over a 32-bit data bus
• 33 MBytes/sec synchronous 8-bit video out port
• Maximum clock speeds up to 33 MHz
• Average 15 to 1 compression ratio for 1200 dpi
bitmap image data
• Advanced banding support: blank bands,
prearming
FLEXIBILITY:
• Big Endian or Little Endian; 32 or 16-bit bus
width and data byte reordering for duplex printing
support
• Prearmable registers
• Scan line length up to 2K bytes
• Interfaces directly with various MIPS, Motorola
68xxx and Cold FIRE, Intel i960 embedded
processors
• Pass-through mode passes raw data through the
decompression engine
• Counter checks errors in decompression
SYSTEM INTERFACE:
• Single chip decompression solution – no external
SRAM required
• Two 16 × 32-bit FIFOs with programmable
threshold counters facilitate burst mode transfers
OTHERS:
• Low power modes
• Software emulation program available
• 128 pin quad flat package
• Test pin tristates outputs
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DOREQN
DIREQN
SD
DOACKN
Functional Block Diagram
DIACKN
Figure 1:
DATA PORT CONTROL
32
D[31:0]
DATA
PORT
DRIVEN
32
32
(To Printer)
DI
FIFO
8
DO
FIFO
8
DECOMPRESSOR
16x32
16x32
FUNCTIONAL OVERVIEW
The coprocessor device has two external high
speed synchronous data ports capable of transferring
once every clock cycle. These are a 32-bit
bidirectional data port and a Video Output Data
(VOD) port. The 32-bit port is capable of
transferring up to 4 bytes per clock. The VOD is
capable of up to one byte per clock.
Decompression data is accepted through the 32bit data port, buffered in the Decompression Input
FIFO (DI FIFO) and decompressed. The output data
Table 1:
INTRN
RDYN
DIR
is made available on the 32-bit data port via the
Decompression Output FIFO (DO FIFO) or the 8bit Video Output port. The decompression engine
runs on the 33 MHz clock and is capable of
processing an uncompressed byte every other clock.
The two FIFOs are organized as 16×32 each.
For data transfers through the two ports, the
“effective” FIFO sizes differ according to their data
bus widths. The table below shows the size of the
data port and the “effective” FIFO size for the
various configurations supported by the device.
Data Bus and FIFO Sizes Supported
OPERATION
DATA BUS WIDTH
Decompression Data In/Out
Decompression Data In/Out
Decompressed Data Out
32
16
8
Table 2:
CSN
6
PA[5:0]
PD[7:0]
8
VOD
PORT
VOEOTN
VOEORN
VOREQN
VOD[7:0]
VOACKN
AHA3422
StarLite
MICROPROCESSOR INTERFACE
PROCMODE[1:0]
RSTN
CLK
TEST
CLOCK
1.3
8
PORT
EFFECTIVE FIFO SIZE
Data Port
Data Port
Video Out
16 x 32
16 x 16
16 x 8
Connection to Host Microprocessors
PIN NAME
i960Cx
i960Kx
IDT3081
Motorola
MCFS102(ColdFIRE)
PA
CSN
DIR
PD
SD
RDYN
DRIVEN
CLOCK
A
CS
W/R
D
WAIT
No Connect
DEN
PCLK
LAD
CS
W/R
LAD
READY
READY
System Dependent
No Connect
Latched Address
System Dependent
WR
A/D
System Dependent
ACK
System Dependent
SYSCLK
Latched Address
Decoded Chip Select
R/W
A/D[7:0]
System Dependent
TA
System Dependent
BCLOCK
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Movement of data for decompression is
performed using synchronous DMA over the 32-bit
data port. The Video port also supports synchronous
DMA mode transfers. The DMA strobe conditions
are configurable for the 32-bit data port depending
upon the system processor and the available DMA
controller.
Data transfer for decompression is synchronous
over the two data ports functioning as DMA
masters. To initiate a transfer out of the Video port,
the device asserts VOREQN, the external device
responds with VOACKN and begins to transfer data
over the VOD bus on each succeeding rising edge of
the clock until VOREQN is deasserted. The 32-bit
port relies on the FIFO Threshold settings to
determine the transfer.
The sections below describe the various
configurations, programming and other special
considerations in developing a decompression
system using AHA3422.
2.0
SYSTEM CONFIGURATION
This section provides information on
connecting the device to various microprocessors.
Data throughput is internally controlled by
writing a control code to the Control register. If this
feature is not used, the system must control data
throughput to remain within the specified limit of 16
MBytes/sec. The control code for this device is 0x0E.
2.1
MICROPROCESSOR INTERFACE
The device is capable of interfacing directly to
various processors for embedded application. Table 2
and Table 3 show how to connect to various host
microprocessors.
All register accesses are performed on the 8-bit
PD bus. The PD bus is the lowest byte of the 32-bit
microprocessor bus. During reads of the internal
registers, the upper 24 bits are not driven. System
designers should terminate these lines with Pullup
resistors.
Table 3:
The part provides four modes of operation for
the microprocessor port. Both active high and active
low write enable signals are allowed as well as two
modes for chip select. The mode of operation is set
by the PROCMODE[1:0] pins. The
PROCMODE[1] signal selects when CSN must be
active and also how long an access lasts.
When PROCMODE[1] is high, CSN
determines the length of the access. CSN must be at
least 5 clocks in length. On a read, valid data is
driven onto PD[7:0] during the 5th clock. If CSN is
longer than 5 clocks, then valid data continues to be
driven out onto PD[7:0]. When CSN goes inactive
(high), PD[7:0] goes tristate (asynchronously) and
RDYN is driven high asynchronously. CSN must be
high for at least two clocks. RDYN is always driven
(it is not tristated when PROCMODE[1] is high). The
mode is typical of processors such as the Motorola
68xxx.
When PROCMODE[1] is low, accesses are
fixed at 5 clocks, PD[7:0] is only driven during the
fifth clock, and RDYN is driven high for the first 4
clocks and low during the fifth clock. RDYN is
tristated at all other times. Write data must be driven
the clock after CSN is sampled low. Accesses may
be back to back with no delays in between. This
mode is typical of RISC processors such as the i960.
PROCMODE[0] determines the polarity of the
DIR pin. If PROCMODE[0] is high, then the DIR
pin is an active low write enable. If PROCMODE[0]
is low, then the DIR pin is an active high write
enable. Figure 2 through Figure 5 illustrate the
detailed timing diagrams for the microprocessor
interface.
For additional notes on interfacing to various
microprocessors, refer to AHA Application Note
(ANDC16), Designer’s Guide for StarLite Family
Products. AHA Applications Engineering is
available to support with other processors not in the
Designer’s Guide.
Microprocessor Port Configuration
PROCMODE[1:0]
DIR
00
01
10
11
Active high write
Active low write
Active high write
Active low write
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CYCLE LENGTH EXAMPLE PROCESSOR
fixed
fixed
variable
variable
i960
68xxx, MIPS R3000
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Figure 2:
Microprocessor Port Write (PROCMODE[1:0]=“01”)
CLOCK
A0
PA[5:0]
A1
CSN
DIR
PD[7:0]
D0
D1
RDYN
Figure 3:
Microprocessor Port Read (PROCMODE[1:0]=“01”)
CLOCK
A0
PA[5:0]
A1
A2
CSN
DIR
PD[7:0]
D0
D1
RDYN
Figure 4:
Microprocessor Port Write (PROCMODE[1:0]=“11”)
CLOCK
PA[5:0]
A0
A1
CSN
DIR
PD[7:0]
D0
RDYN
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Figure 5:
Microprocessor Port Read (PROCMODE[1:0]=“11”)
CLOCK
PA[5:0]
A0
A1
CSN
DIR
PD[7:0]
D0
RDYN
3.0
FUNCTIONAL DESCRIPTION
This section describes the various data ports,
special handling, data formats and clocking structure.
3.1
DATA PORTS
The device contains one data input port, DI, and
one data output port, DO, on the same 32-bit data bus,
D[31:0]. Data transfers are controlled by external
DMA control. The logical conditions under which data
is written to the input FIFO or read from the output
FIFO are set by the DSC (Data Strobe Condition) field
of the System Configuration 1 register.
A strobe condition defines under what logical
conditions the input FIFO is written or the output
FIFO read. DIACKN, DOACKN, and SD pins
combine to strobe data in a manner similar to DMA
controllers. The DMA Mode sub-section describes
the various data strobe options.
3.2
DMA MODE
On the rising edge of CLOCK when the strobe
condition is met, the port with the active
acknowledge either strobes data into or out of the
chip. No more than one port may assert acknowledge
at any one time. Table 4 shows the various conditions
that may be programmed into register DSC.
Figure 6 through Figure 11 illustrate the DMA
mode timings for single, four word and eight word
burst transfers for DSC=100 selection. For other
DSC settings, please refer to Appendix A. Note that
the only difference between odd and even values of
DSC is the polarity of SD. Waveforms are only
shown for polarities of SD corresponding to specific
systems.
Table 4: Internal Strobe Conditions for DMA Mode
DSC[2:0]
LOGIC EQUATION
SYSTEM CONFIGURATION
i960Cx with internal DMA controller. SD is connected to
000
( ACKN ) & ( ACKN delayed ) & ( SD ) WAITN.
001
( ACKN ) & ( ACKN delayed ) & ( SD ) No specific system
010
( ACKN ) & ( SD )
011
( ACKN ) & ( SD )
100
( ACKN delayed ) & ( SD delayed )
General purpose DMA controller
i960Kx with external, bus master type DMA controller.
SD is connected to RDYN.
No specific system
101
( ACKN delayed ) & ( SD delayed )
No specific system
110
( ACKN ) & ( ACKN delayed )
No specific system
111
( ACKN ) & ( ACKN delayed )
No specific system
CKN delayed = ACKN delayed 1 clock
SD delayed = SD delayed 1 clock
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Figure 6:
DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=100
CLOCK
ACKN
SD
DRIVEN
D
Figure 7:
D0
D1
DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=100
CLOCK
ACKN
SD
DRIVEN
D
Figure 8:
D0
D1
DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition
of DSC=100
CLOCK
ACKN
SD
DRIVEN
D
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D0
D1
D2
D3
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Figure 9:
DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition
of DSC=100
CLOCK
ACKN
SD
DRIVEN
D
D0
D1
D2
D3
Figure 10: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition
of DSC=100
CLOCK
ACKN
SD
DRIVEN
D
D0
D1
D2
D3
D4
D5
D6
D7
Figure 11: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition
of DSC=100
CLOCK
ACKN
SD
DRIVEN
D
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D0
D1
D2
D3
D4
D5
D6
D7
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3.3
PAD WORD HANDLING IN
BURST MODE
A method is available to delete pad words during
decompression. Pad words may be deleted by using
the Decompression Pause on Record Boundaries bit
(DPOR), in the Decompression Control register.
After the part is paused, the DI FIFO must be reset by
asserting the DIRST bit in the Port Control register.
Decompressor must also be reset by asserting DDR
bit in Decompression Control register.
3.4
DMA REQUEST SIGNALS
AND STATUS
The part requests data using request pins
(DIREQN, DOREQN). The requests are controlled
by programmable FIFO thresholds. Both input and
output FIFOs have programmable empty and full
thresholds set in the Input FIFO Threshold and
Output FIFO Threshold registers. By requesting
only when a FIFO can sustain a certain burst size, the
bus is used more efficiently.
Operation of these request signals should not be
confused with the request signals on the video port.
DIREQN active indicates space available in the input
FIFO and DOREQN active indicates data is available
in the output FIFO. These request signals being
inactive do not prevent data transfers. The data
transfers are controlled solely with the particular
acknowledge signal being active.
The input request, DIREQN, operates under the
following prioritized rules, listed in order of highest
to lowest:
1) If the FIFO reset in the Port Control
register is active, the request is inactive.
2) If a FIFO overflow interrupt is active, the
request is inactive.
3) If the FIFO is at or below the empty
threshold, the request remains active.
4) If the FIFO is at or above the full threshold,
the request stays inactive.
Page 8 of 44
The output request, DOREQN, operates under
the following prioritized rules, listed in order of
highest to lowest:
1) If the FIFO reset in the Port Control
register is active, the request is inactive.
2) If the output FIFO underflow interrupt is
active, the request is inactive.
3) If an EOR is present in the output FIFO, the
request goes active.
4) If the output FIFO is at or above the full
threshold, the request goes active.
5) If an EOR is read (strobed) out of the FIFO,
the request goes inactive during the same
clock as the strobe (if ERC=0), otherwise it
goes inactive on the next clock.
6) If the output FIFO is at or below the empty
threshold, the request goes inactive.
3.4.1
FIFO THRESHOLD
For maximum efficiency, the FIFO threshold
should be set in such a way that the decompressor
seldom runs out of data from the DI FIFO or
completely fills the output FIFO. The FIFO is 16
words deep.
For example, in a system with fixed 8-word
bursts, good values for the thresholds are:
IET=3, IFT=4, OFT=D, OET=C
Setting the input full threshold to one higher
than the input empty threshold simply guarantees
that the request deasserts as soon as possible. The
latency between a word being strobed in and the
request changing due to a FIFO threshold condition
is 3 clocks. This should be kept in mind when
programming threshold values. Refer to Section 4.0
of AHA Application Note (ANDC16), Designer’s
Guide for StarLite Family Products for a more
thorough discussion of FIFO thresholds. The
following figure shows an example of an input FIFO
crossing its full threshold.
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Figure 12: FIFO Threshold Example (IFT=4, DSC=2, 1 Word Already in FIFO)
CLOCK
D
1
2
3
4
5
6
7
8
2
3
4
5
6
7
CIACKN
CIREQN
Threshold
Counter
Note:
1
8
9
DIREQN deasserted when threshold counter exceeded IFT=4, but additional words are read as long as
ACKN is asserted.
Figure 13: Request vs. End-of-Record, Strobe Condition of DSC=010
CLOCK
CIACKN
D
EOR-2
EOR-1
EOR
REQN
(ERC=0)
REQN
(ERC=1)
EORN
3.4.2
REQUEST DURING AN END-OF-RECORD
The request deasserts at an EOR in one of two
ways. If ERC bit in System Configuration 1 is zero,
the request deasserts asynchronously during the
clock where the EOR is strobed out of the FIFO.
This leads to a long output delay for REQN, but may
be necessary in some systems. For DSC values of 4
or 5, the request deasserts the first clock after the
acknowledge pulse for the EOR. If ERC is set to
one, then the request deasserts synchronously the
clock after the EOR is strobed out. The minimum
low time on the request in this case is one clock.
The request delay varies between the different
strobe conditions. See Section 8.0 AC Electrical
Specifications for further details.
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3.4.3
REQUEST STATUS BITS
An external microprocessor can also read the
value of each request using the DIREQ and DOREQ
bits in the Decompression Port Status register.
Please note the request status bits are active high
while the pins are active low.
3.5
DATA FORMAT
The width of the D bus is selected with the
WIDE bit in System Configuration 0. If WIDE=1,
then D is a 32-bit bus. If WIDE=0, D is a 16-bit bus.
If the bus is configured to be 16-bits wide
(WIDE=0), all data transfers occur on D[15:0] and
the upper 16 bits of the bus, D[31:16], should be
terminated with Pullup resistors. If WIDE=0, the
FIFO is sixteen words deep.
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Since the compression algorithm is byte
oriented, it is necessary for AHA3422 to know the
ordering of the bytes within the word. The
DECOMP BIG bit in System Configuration 0 selects
between big endian and little endian byte ordering.
Little endian stores the first byte in the lower eight
bits of a word (D[7:0]). Big endian stores the first
byte in the uppermost eight bits of a word (D[31:24]
for WIDE=1, D[15:8] for WIDE=0).
3.6
ODD BYTE HANDLING
All data transfers to or from the device are
performed on the D bus on word boundaries. Since
no provision is made for single byte transfers,
occasionally words will contain pad bytes.
Following is a description of when these pad bytes
are necessary for each of the data interfaces.
3.6.1
INPUT, PAD BYTES AND ERROR
CHECKING
The device recognizes the end of a record by the
appearance of a special End-of-Record sequence in
the data stream. Once this is seen, the remaining
bytes in the current word are treated as pad bytes
and discarded. The word following the end of the
record is the beginning of the next record.
The Decompression Record Length (DRLEN)
register can be used to provide error checking. The
expected length of the decompressed record is
programmed into the DRLEN register. The
decompressor then counts down from the value in
DRLEN to zero.
A DERR interrupt is issued if an EOR is not
read out of the decompressor when the counter
expires or if an EOR occurs before the counter
expires (i.e., when the record lengths do not match).
If the DERR interrupt is masked, use of the DRLEN
register is optional.
When operating in pass-through mode, there is
no End-of-Record codeword for the decompressor
to see. In pass-through mode, the user must set the
record length in the DRLEN register.
3.6.2
OUTPUT AND PAD BYTES
When the decompressor detects an End-ofRecord codeword, it will add enough pad bytes of
value 0x00 to complete the current word as defined
by the WIDE bit in the System Configuration 0
register. For example, if a record ends on a byte
other than the last byte in a word, the final word
contains 1, 2 or 3 pad bytes. This applies to the 32bit data port only, not the VOD port. The VOD port
never outputs pad bytes since it is 8-bits wide.
3.7
VIDEO INTERFACE
3.7.1
VIDEO OUTPUT
The video output port is enabled by the VDOE
bit in the System Configuration 1 register. The port
uses VOREQN to indicate that the byte on
VOD[7:0] is valid. An 8-bit word is read each clock
when both VOREQN and VOACKN are sampled
low on a rising edge of CLOCK. Pad bytes at an end
of record are discarded by the video output port and
do not appear on VOD[7:0]. When the byte on
VOD[7:0] is the last byte in a record, the VOEORN
signal goes low. Unlike a DMA transfer, there are no
pad bytes after an End-of-Record.
VOEOTN operates similar to VOEORN. It flags
the end of an output transfer of one or more
decompressed records. VOEOTN is asserted when the
End-of-Record is at the output of the DO FIFO and the
decompression record count has decremented to zero.
The port requests whenever a valid byte is
present on the output. The values in OET and OFT
are all ignored. The decompression output FIFO is
16 bytes deep in this mode. The video output port
can output up to one byte per clock. The DMA
interface cannot access the decompression output
FIFO when VDOE is set.
Figure 14: Timing Diagram, Video Output
CLOCK
VOREQN
VOACKN
VOD[7:0]
0
1
2
3
4
5
VOEORN/
VOEOTN
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3.8
ALGORITHM
algorithm is available for evaluation.
Caveat: Changing the mode for the
decompressor between records or multiple-record
transfers must be done with the data of the following
record or transfer held off until the DEOR status bit
is true for the current record and the Decompression
Control registers have been reprogrammed. This
reprogramming can occur automatically with
prearming.
3.9
3.10 PREARMING
AHA3422 efficiently implements an algorithm
optimized for bitonal images. For some comparison
data refer to the AHA Application Note (ANDC13),
Compression Performance: StarLite: ENCODEB2
on Bitonal Images. A software emulation of the
DECOMPRESSION ENGINE
The decompression engine is enabled with the
DCOMP bit in the Decompression Control register.
When the engine is enabled, it takes data from the
DI FIFO as it becomes available. This data is either
decompressed by the engine or passed through
unaltered. Pass-through mode is selected with the
DPASS bit. DPASS may only be changed when
DCOMP is set to zero and DEMP is set to one. The
contents of the dictionary are preserved when
DCOMP is changed. However, when DPASS is
changed, the contents are lost. Consequently,
AHA3422 cannot be changed from pass-through
mode to decompression mode or vice versa without
losing the contents of the dictionary.
The decompressor can be instructed to halt at the
end of a record or an end of multiple-record transfer.
If the DPOR bit is set, the decompressor stops taking
data out of the DI FIFO immediately after the last
byte of a record, and the DCOMP bit is cleared. If
DPOT bit is set the decompressor halts at the end of
the multiple-record transfer. The DEMP bit indicates
the decompressor has emptied of all data. Decompression is restarted by setting the DCOMP bit. If
DPOR or DPOT is set and data from a second record
enters the FIFO immediately after the first record,
bytes from the second record will have entered the
decompressor prior to decoding the EOR. An implication of this is that bytes from the second record will
remain in the decompressor and prevent DEMP from
setting after all of the data from the first record has
left the decompressor. This differs from operation of
the compression engine. In either mode, a DEOR
interrupt is generated when the last byte of a decompressed record is read out of the chip, and DEOT
when the last byte of a transfer is read out of the chip.
The decompressor takes data from the
decompression input FIFO at a maximum rate of
16 MBytes/sec. AHA3422 can maintain this data
rate as long as the decompression input FIFO is not
empty or the decompression output FIFO is not full.
PS3422-0600
Prearming is the ability to write certain
registers that apply to the next record while the
device is processing the current record. These
registers may be prearmed for record boundaries.
Prearming is automatic, meaning there is no way to
disable it. If a prearmable register is written while
the part is busy processing a record, at the end of the
record the part takes its program from the register
value last written. Decompression Control register
has a corresponding prearm register.
The lower 3 bytes of Decompression Length
register are prearmable. If the most significant byte
of this register is written to, the counter is
immediately loaded with the current 4 byte value. if
the most significant byte is not written to the counter,
the counter gets reloaded at the end of the current
record.
3.11 INTERRUPTS
Five conditions are reported in the Interrupt
Status/Control 0 and Status/Control 1 registers as
individual bits. All interrupts are maskable by
setting the corresponding bits in the Interrupt Mask
register. A one in the Interrupt Mask register means
the corresponding bit in the Interrupt Status/Control
register is masked and does not affect the interrupt
pin (INTRN). The INTRN pin is active whenever
any unmasked interrupt bit is set to a one.
An End-of-Record interrupt is posted when a
word containing an end-of-record is strobed out of
the decompression output FIFO (DEOR). A DEOR
interrupt is also reported if an end-of-record is read
from the video output port. A decompression end of
transfer interrupt will be posted if this is the last
record of a transfer. End-of-Transfer interrupt
(DEOT) is posted when an EOR occurs that causes
the counter to decrement to zero.
Two FIFO error conditions are also reported.
Overflowing the input FIFO generates a DIOF
interrupt. An overflow can only be cleared by
resetting the FIFO via the Port Control register.
Underflowing the output FIFO (reading when it
is not ready) generates a DOUF. The underflow
interrupt is cleared by writing a one to DOUF. In the
event of an underflow, the FIFO must be reset.
Page 11 of 44
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3.12 DUPLEX PRINTING
3.14 LOW POWER MODE
Duplex Printing is the ability to print on both
sides of the page. AHA3422 supports this with
endian control.
During decompression of this reversed page the
BIG bit in this register must be programmed to the
same value used when this page of data was
compressed. Use of this feature has virtually no
effect on the decompression ratio when compared to
decompressing in forward order.
The device is a data-driven system. When no
data transfers are taking place, only the clock and
on-chip RAMs including the FIFOs require power.
To reduce power consumption to its absolute
minimum, the user can stop the clock when it is
high. With the system clock stopped and at a high
level, the current consumption is due to leakage.
Control and Status registers are preserved in this
mode. Reinitialization of Control registers are not
necessary when switching from Low Power to
Normal operating mode.
3.13 BLANK BANDS
Setting DBLANK in the Decompression
Control register causes the next record output from
the Decompressor to be comprised of a repeating 8bit pattern defined by the Pattern register.
DBLANK automatically clears at the end of the
next record. This command bit may be prearmed by
writing to the Decompression Control Prearm
register. When programming the device to generate
blank records the system must not send data to be
decompressed until the device has reached the end
of record for the blank record.
Page 12 of 44
3.15 TEST MODE
In order to facilitate board level testing, the
device provides the ability to tristate all outputs.
When the TEST0 pin is high, all outputs of the chip
are tristated. When TEST0 is low, the chip returns to
normal operation.
PS3422-0600
advancedhardwarearchitectures
4.0
REGISTER DESCRIPTIONS
The microprocessor configures, controls and monitors IC operation through the use of the registers
defined in this section. The bits labeled “res” are reserved and must be set to zero when writing to registers
unless otherwise noted.
Always program the control register (address 0x3F) with a value of 0x0E following power on and any
hard reset. This should be done prior to accessing any other registers.
A summary of registers is listed below.
Table 5:
Internal Registers
ADDRESS R/W
DESCRIPTION
0x00
R/W System Configuration 0
0x01
R/W System Configuration 1
0x02
R/W Input FIFO Thresholds
0x03
R/W Output FIFO Thresholds
0x04
R
Reserved
0x05
R
Decompression Ports Status
0x06
0x07
0x09
0x0A
R/W
R/W
R/W
R
0x0C
R/W
0x0D
R/W
0x0E
R/W
0x0F
R/W
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
R
R
R
R
R
R
R
R
0x18
PS3422-0600
Port Control 1
Interrupt Status/Control 0
Interrupt Mask 0
Version
Decompression Record
Length 0
Decompression Record
Length 1
Decompression Record
Length 2
Decompression Record
Length 3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
R/W Decompression Control
FUNCTION
DEFAULT
AFTER
RSTN
PREARM
Big Endian vs. Little Endian,
32-bit vs. 16-bit
Data Strobe Condition, EOR
Request Control, VDO Port
Enable
Input FIFO Empty Threshold,
Full Threshold
Output FIFO Empty
Threshold, Full Threshold
Reserved
FIFO Status, Request Status,
EOR Status
Reset Individual FIFOs
EOR, Overflow, Underflow
Interrupt Mask bits
Die Version Number
Undefined
No
0x0F
0x00
0xFF
0x21
No
No
No
No
Bytes Remaining, Byte 0
0xFF
Yes
Bytes Remaining, Byte 1
0xFF
Yes
Bytes Remaining, Byte 2
0xFF
Yes
Bytes Remaining, Byte 3
0xFF
No
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Pause on Record Boundaries,
Enable Decompression
Engine, Decompression
Engine Empty Status,
Dictionary Reset, Enable
Pass-Through Mode, Pause
End-of-Transfer, Generate
Blank Record, Enable Prearm
Undefined
Undefined
Undefined
Undefined
0x04
0x00
Undefined
Undefined
Undefined
No
0x00
No
Undefined
No
Undefined
No
Undefined
0x04
Yes
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ADDRESS R/W
0x1A
0x1C
0x1D
0x20
0x21
0x27
0x29
0x2C
0x2D
0x30
0x31
0x32
0x33
0x34
0x35
0x38
0x3A
0x3F
DESCRIPTION
R/W Decompression Reserved 1
FUNCTION
Reserved
Line Length Register Lower
R/W Decompression Line Length 0
8 bits
Line Length Register Upper
R/W Decompression Line Length 1
3 bits
R Reserved
Reserved
R Reserved
Reserved
R/W Interrupt Status/Control 1
Decompression EOT Interrupt
R/W Interrupt Mask 1
Interrupt Mask bit for DEOT
Decompressor number of
R/W Decompression Record Count 0
records in a transfer
Decompressor number of
R/W Decompression Record Count 1
records in a transfer
R Reserved
Reserved
R Reserved
Reserved
R Reserved
Reserved
R Reserved
Reserved
R Reserved
Reserved
8-bit pattern for blank record
R/W Pattern
generation
Prearm Register for
R/W Decompression Control Prearm
Decompression Control
R/W Decompression Reserved 2
Reserved
R/W Control
Program to 0x0E
Page 14 of 44
DEFAULT
AFTER
RSTN
0x00
No
Undefined
No
Undefined
No
FF
FF
0x00
0xFF
No
No
0xFF
No
0xFF
No
PREARM
0x00
0x00
0x00
0x00
0x00
Undefined
No
0x00
No
0x00
0x0F
No
No
PS3422-0600
advancedhardwarearchitectures
4.1
SYSTEM CONFIGURATION 0, ADDRESS 0x00 - READ/WRITE
Address
0x00
bit7
res
bit6
bit5
bit4
bit3
bit2
res
WIDE
bit1
bit0
BIG
res
After reset, its contents are undefined. It must be written before any input or output data movement may
be performed. After changing this register, reset FIFOs via the Port Control register.
BIG-
Selects between little or big endian byte order for the decompressor. See table.
res -
Bits must always be written with zeros.
WIDE -
Selects between 32 and 16-bit D buses.
COMP BIG or
WIDE
DECOMP BIG
0
0
0
1
1
0
1
4.2
1
DESCRIPTION
Little Endian data order
Little Endian data order
D[31:24]
Byte 3
D[23:16]
Byte 2
Big Endian data order
Big Endian data order
D[31:24]
Byte 0
D[23:16]
Byte 1
16-bit words
D[15:8]
Byte 1
D[7:0]
Byte 0
32-bit words
D[15:8]
Byte 1
D[7:0]
Byte 0
16-bit words
D[15:8]
Byte 0
D[7:0]
Byte 1
32-bit words
D[15:8]
Byte 2
D[7:0]
Byte 3
SYSTEM CONFIGURATION 1, ADDRESS 0x01 - READ/WRITE
Address
0x01
bit7
bit6
res
bit5
bit4
VDOE
ERC
bit3
res
bit2
bit1
bit0
DSC[2:0]
This register is cleared by reset.
DSC[2:0] - Data Strobe Condition. Control the condition used to strobe data into and out of the data ports
on the D bus. Table 4 shows the programming for the strobe condition for various DMA modes.
res -
Bits must always be written with zeros.
ERC -
EOR Request Control. Determines when DOREQN deasserts at an End-of-Record. If ERC=0,
then the request deasserts asynchronously during the clock when an EOR is strobed out. If
ERC=1, then the request deasserts synchronously the clock after an EOR is strobed out. See
Figure 17 through Figure 20.
VDOE -
VDO Port Enable. When this bit is set, the data from the decompression output FIFO goes to
the VDO port. When the bit is clear, the decompressed data is read by DMA on the D bus.
PS3422-0600
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4.3
INPUT FIFO THRESHOLDS, ADDRESS 0x02 - READ/WRITE
Address
0x02
bit7
bit6
bit5
bit4
bit3
IFT[3:0]
bit2
bit1
bit0
IET[3:0]
After reset, its contents are undefined. It must be written before any input or output data movement may
be performed.
IET[3:0] - Empty threshold for the input FIFO. If the number of words in the input FIFO (DI) is less than
or equal to this number, the request for that channel is asserted.
IFT[3:0] - Full threshold for the input FIFO. If the number of words in the input FIFO (DI) is greater than
or equal to this number, the request for the channel is deasserted.
4.4
OUTPUT FIFO THRESHOLDS, ADDRESS 0x03 - READ/WRITE
Address
0x03
bit7
bit6
bit5
bit4
bit3
OFT[3:0]
bit2
bit1
bit0
OET[3:0]
After reset, its contents are undefined. It must be written before any input or output data movement may
be performed.
OET[3:0] - Empty threshold for the output FIFO. If the number of words in the output FIFO (DO) is less
than or equal to this number, the request for the channel is deasserted (except in the case of an
End-of-Record).
OFT[3:0] - Full threshold for the output FIFO. If the number of words in the output FIFO (DO) is greater
than or equal to this number, the request for that channel is asserted.
4.5
DECOMPRESSION PORTS STATUS, ADDRESS 0x05 - READ ONLY
Address
0x05
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DOEMP
DIEMP
res
DEOR
DOREQ
DOET
DIREQ
DIFT
This is a read only register. Writing to this register has no effect. After reset, its contents are undefined.
DIFT -
Decompression input FIFO full threshold. This signal is active when the DI FIFO is at or above
the programmed FIFO full threshold. After reset and the Input FIFO Threshold register has
been written, this bit contains a zero.
DIREQ -
Decompression input request signal state. Reports the current state for the DIREQN pin. Notice
that this bit is active high while the pin is active low. Therefore, the value of this bit is always
the inverse of the value of the signal. After reset this bit contains a zero.
DOET -
Decompression output FIFO empty threshold. This bit is active when the DO FIFO is at or
below the programmed FIFO empty threshold. After reset and the Output FIFO Threshold
register has been written, this bit contains a one.
DOREQ - Decompression output request signal state. Reports the current state for the DOREQN pin.
Notice that this bit is active high while the pin is active low. Therefore, the value of this bit is
always the inverse of the value of the signal. After reset this bit contains a zero.
DEOR -
Decompression output end of record. This bit is active when the output FIFO contains the Endof-Record code. After reset this bit contains a zero.
res -
Bits must always be written with zeros.
Page 16 of 44
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DIEMP -
Decompression input empty. This bit is active when the DI FIFO is empty. After reset this bit
contains a one.
DOEMP - Decompression output empty. This bit is active when the DO FIFO is empty. After reset this bit
contains a one.
4.6
PORT CONTROL, ADDRESS 0x06 - READ/WRITE
Address
0x06
bit7
bit6
bit5
bit4
res
bit3
bit2
DORST
DIRST
bit1
bit0
res
This register is initialized to 0x0F after reset.
DIRST -
Decompression input reset. Setting this bit to a one resets the DI FIFO and clears the state
machines in the decompression input port. The reset condition remains active until the
microprocessor writes a zero to this bit.
DORST -
Decompression output reset. Setting this bit to a one resets the DO FIFO and clears the state
machines in the decompression output port. The reset condition remains active until the
microprocessor writes a zero to this bit.
res -
Bits must always be written with zeros.
4.7
INTERRUPT STATUS/CONTROL 0, ADDRESS 0x07 - READ/WRITE
Address
0x07
bit7
bit6
bit5
DOUF
res
DIOF
bit4
bit3
res
bit2
bit1
bit0
DERR
DEOR
res
This register is initialized to 0x00 after reset.
DEOR -
Decompression End-of-Record interrupt. This bit is set when the last byte of a record is strobed
out of the decompression DMA or video output port. The microprocessor must write a one to
this bit to clear this interrupt.
DERR -
Decompression Error. This bit is set if an EOR leaves the decompressor before DRLEN has
counted down to zero or if DRLEN counts to zero and the last byte is not an EOR. DERR is
only active in decompression mode (DPASS=0). The microprocessor must write a one to this
bit to clear this interrupt.
res -
Bits must always be written with zeros.
DIOF -
Decompression Input FIFO Overflow. This interrupt is generated when a write to an already
full DI FIFO is performed. Data written in this condition is lost. The only means of recovery
from this error is to reset the FIFO with the DIRST bit. Resetting the FIFO causes this interrupt
to clear. DIREQN is inactive while the interrupt is set.
DOUF -
Decompression Output FIFO underflow. This interrupt is generated when a read from an empty
DO FIFO is performed. Once this interrupt is set, the DO FIFO must be reset with the DORST
bit. The microprocessor must write a one to this bit to clear this interrupt. DOREQN is inactive
while the interrupt is set.
PS3422-0600
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4.8
INTERRUPT MASK 0, ADDRESS 0x09 - READ/WRITE
Address
0x09
bit7
bit6
bit5
DOUFM
res
DIOFM
bit4
bit3
res
bit2
bit1
bit0
DERRM
DEORM
res
This register is initialized to 0xFF after reset.
DEORM - Decompression End-of-Record Interrupt Mask. When set to a one, prevents Decompression
End-of-Record from causing INTRN to go active.
DERRM - Decompression Error Mask. When set to a one, prevents a decompression error (DERR) from
causing INTRN to go active.
res -
Bits must always be written with zeros.
DIOFM -
Decompression Input FIFO Overflow Mask. When set to a one, prevents a decompression
input FIFO overflow (DIOF) from causing INTRN to go active.
DOUFM - Decompression Output FIFO Underflow Mask. When set to a one, prevents a decompression
output FIFO underflow (DOUF) from causing INTRN to go active.
4.9
VERSION, ADDRESS 0x0A - READ ONLY
Address
0x0A
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
VERSION[7:0]
VERSION[7:0] - Contains version number of the die.
4.10 DECOMPRESSION RECORD LENGTH, ADDRESS 0x0C, 0x0D, 0x0E, 0x0F READ/WRITE
Address
0x0C
0x0D
0x0E
0x0F
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DRLEN[7:0]
DRLEN[15:8]
DRLEN[23:16]
DRLEN[31:24]
These registers are initialized to 0xFF after reset.
DRLEN[31:0]-Decompression Record Length. Contains the number of bytes in a decompressed record.
These registers provide different functions depending on whether the decompressor is in passthrough or decompression mode. In decompression mode, the data itself contains EOR
information and DRLEN is only used for error checking. DRLEN is decremented each time a
byte leaves the decompressor.
In decompression mode, a DERR interrupt is issued if an EOR is not read out of the
decompressor when the counter expires or if an EOR occurs before the counter expires (i.e.,
when the record lengths do not match). If the DERR interrupt is masked, use of the DRLEN
register is optional in decompression mode.
In pass-through mode, DRLEN determines the size of records read out of the decompressor.
The counter is decremented for each byte read into the decompressor.
In either mode, the counter reloads when it reaches zero or when DRLEN[31:24] is written.
Reading DRLEN returns the number of bytes left in the count. The lower three bytes of this
register may be prearmed since the counter is automatically reloaded at the end of a record
when the part is not programmed to pause on End-of-Record. The upper byte is not prearmable
since writing to this byte triggers an immediate reload to the counter.
Page 18 of 44
PS3422-0600
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4.11 DECOMPRESSION CONTROL, ADDRESS 0x18 - READ/WRITE
Address
bit7
bit6
0x18
DPREARM DBLANK
bit5
bit4
bit3
bit2
bit1
bit0
DPOT
DPASS
DDR
DEMP
DCOMP
DPOR
This register is initialized to 0x04 after reset. This register can be prearmed.
DPOR -
Decompression Pause on record boundaries. When this bit is set to one, the decompressor stops
taking data from the input FIFO once a record boundary is found. Upon finding the record
boundary, DCOMP is cleared. This bit may only be changed when DCOMP is set to zero. After
system reset or DDR, this bit is cleared.
DCOMP - Decompression. Setting this bit to a one enables the decompression engine (or pass-through
mode if DPASS is set) to take data from the decompression input FIFO. If this bit is cleared,
decompression stops. The bit is automatically cleared at the end of a record if DPOR is set.
Decompression can be restarted without loss of data by setting DCOMP. After system reset or
DDR, this bit is cleared.
DEMP -
Decompression engine empty. This bit is set when the decompression engine is cleared of data.
Writing to this bit has no effect. After system reset, this bit is set.
DDR -
Decompression Dictionary Reset. Setting this bit immediately resets the decompressor
including the decompression dictionary. The reset condition remains active until the
microprocessor writes a zero to this bit.
DPASS -
Decompression pass-through mode. While this bit is set, data is passed directly through the
decompression engine without any effect on the data. This bit may only be changed when
decompression is disabled (DCOMP=0) and the decompression engine is empty of data
(DEMP=1). The pass-through operation is started by setting DCOMP. To stop the pass-through
operation, DCOMP should be cleared (to pause operation) and then DPASS may be cleared.
DPOT -
Decompression Pause on Transfer Boundaries. When this bit is set the decompressor stops
taking data from the input FIFO once a decompression end of transfer boundary is found
indicated by the Decompression Record Counter decrementing to zero.
DBLANK - Decompression Blank record. The data in the next record output from the decompressor is a
repeating byte pattern using the 8-bit data defined in the PATTERN register. DBLANK
automatically clears at the end of the record when the Decompression Record Count
decrements to zero. When using DBLANK to generate a blank record the device must not
contain data to be decompressed and the system must not send data to be decompressed for any
future records until the part has reached the End-of-Record for the blank record. Also, the user
must not set the DCOMP bit when the DBLANK bit is set.
DPREARM -Prearm Enable. When this bit is set, Decompression Control Prearm register is loaded into the
Decompression Control register when the next end of record leaves the decompressor.
4.12 DECOMPRESSION RESERVED, ADDRESS 0x1A, 0X3A - READ/WRITE
Address
0x1A
0x3A
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
res
res
This register is used for production testing only. Initialized to 0x00 after reset.
PS3422-0600
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4.13 DECOMPRESSION LINE LENGTH, ADDRESS 0x1C, 0x1D - READ/WRITE
Address
0x1C
0x1D
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
LINE[7:0]
res
LINE[10:8]
This register contains information necessary for the decompression operation. It must be set prior to any
decompression operation. It should only be changed between records when DCOMP is cleared and DEMP
is set. These registers are undefined after reset.
res -
Bits must always be written with zeros.
LINE[10:0]-Line length. The number of bytes in the scan line. Minimum value is 16. For scan line lengths
larger than the maximum allowed, set to 16.
4.14 INTERRUPT STATUS/CONTROL 1, ADDRESS 0x27 - READ/WRITE
Address
0x27
bit7
bit6
bit5
bit4
bit3
bit2
res
bit1
bit0
DEOT
res
This register is initialized to 0x00 after reset.
DEOT -
Decompression End-of-Transfer Interrupt. This bit is set when a decompression end of transfer
condition is reached indicated by the Decompression Record Counter counting down to zero.
The microprocessor must write a one to this bit to clear this interrupt.
res -
Bits must always be written with zeros.
4.15 INTERRUPT MASK 1, ADDRESS 0x29 - READ/WRITE
Address
0x29
bit7
bit6
bit5
bit4
bit3
bit2
res
bit1
bit0
DEOTM
res
This register is initialized to 0xFF after reset.
DEOTM - Decompression End-of-Transfer Interrupt Mask. When set to a one, prevents Decompression
End-of-Transfer from causing INTRN to go active.
res -
Bits must always be written with zeros.
res -
Bits must always be written with zeros.
4.16 DECOMPRESSION RECORD COUNT, ADDRESS 0x2C, 0x2D - READ/WRITE
Address
0x2C
0x2D
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DRC[7:0]
DRC[15:8]
These registers are initialized to 0xFFFF after reset.
DRC[15:0] -Decompression Record Count is the number of records in the current transfer. The internal record
counter latches the value in this register when DRC[15:8] is written. The internal counter is
decremented as the last byte of the record is decompressed. At the End-of-Transfer, the value in
this register is reloaded into the internal record counter. Reading this register address returns the
internal record counter value. Expiration of this counter causes the DEOT interrupt to be posted.
Page 20 of 44
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4.17 PATTERN, ADDRESS 0x35 - READ/WRITE
Address
0x35
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
PATTERN[7:0]
This register is undefined after reset.
PATTERN[7:0]-Pattern is the 8-bit data used to generate blank bands or records. If DBLANK is set, the part
outputs this register value repeatedly for the entire record (or band).
4.18 DECOMPRESSION CONTROL PREARM, ADDRESS 0x38 - READ/WRITE
Address
bit7
bit6
bit5
0x38
NDPREARM NDBLANK NDPOT
bit4
bit3
bit2
NDPASS
NDDR
res
bit1
bit0
NDCOMP NDPOR
This register initializes to 0x00 after reset. This register is cleared when the prearm loads into the
Decompression Control register, thus providing a method for the user to verify that the prearm loaded.
Note, the user must not change modes of operation between decompression, pass-through and blank
when there is data in the decompressor. See Decompression Control register for bit descriptions. This
register is the prearm register for the Decompression Control register.
res -
Bits must always be written with zeros.
4.19 CONTROL, ADDRESS 0x3F - READ/WRITE
Address
0x3F
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CONTROL CODE
This register must be written with 0x0E before a decompression or pass-through operation begins.
Default after reset is 0x0F.
PS3422-0600
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5.0
SIGNAL DESCRIPTIONS
This section contains descriptions for all the pins. Each signal has a type code associated with it. The
type codes are described in the following table.
TYPE CODE
I
O
I/O
S
A
5.1
DESCRIPTION
Input only pin
Output only pin
Input/Output pin
Synchronous signal
Asynchronous signal
MICROPROCESSOR INTERFACE
SIGNAL
MICROPROCESSOR INTERFACE
TYPE
DESCRIPTION
PD[7:0]
I/O
S
PA[5:0]
I
S
I
S
CSN
DIR
I
S
RDYN
O
A,S
INTRN
O
S
PROCMODE[1:0]
I
S
Page 22 of 44
Processor Data. Data for all microprocessor reads and writes of
registers within AHA3422 are performed on this bus. This bus may
be tied to the Data bus, D[31:0], provided microprocessor accesses
do not occur at the same time as DMA accesses.
Processor Address Bus. Used to address internal registers within
AHA3422.
Chip Select. Selects AHA3422 as the source or destination of the
current microprocessor bus cycle. CSN needs only be active for one
clock cycle to start a microprocessor access.
Direction. This signal indicates whether the access to the register
specified by the PA bus is a read or a write. The polarity of this signal
is programmed with the PROCMODE0 pin.
Ready. Indicates valid data is on the data bus during read operation
and completion of write operation. Its operation depends on
PROCMODE[1:0] settings.
Interrupt. The compression and decompression processes generate
interrupts that are reported with this signal. INTRN is low whenever
any non-masked bits are set in the Interrupt Status/Control register.
Microprocessor Port Configuration Mode. Selects the polarity of the
DIR pin and operation of the CSN pin. Refer to Section 2.1
Microprocessor Interface for details. (Figure 2 through Figure 5)
PS3422-0600
advancedhardwarearchitectures
5.2
DATA INTERFACE
SIGNAL
D[31:0]
TYPE
I/O
S
DRIVEN
I
A
SD
I
S
DIREQN
O
S
I
S
DIACKN
DOREQN
DOACKN
5.3
O
A, S
I
S
DATA INTERFACE
DESCRIPTION
Data for all channels is transmitted on this bus. The ACKN is used to
distinguish between the four channels. Data being written to AHA3422 is
latched on the rising edge of CLOCK when the strobe condition is met.
Data setup and hold times are relative to CLOCK. If the bus is configured
to 16-bit transfers (WIDE=0), data is carried on D[15:0]. In this case,
D[31:16] should be terminated with pullup resistors.
Drive Enable. Active low output driver enable. This input must be low in
order to drive data onto D[31:0] in accordance with the current strobe
condition.
Strobe Delay. Active high. Allows insertion of wait states for DMA
access to the FIFOs. The strobe condition, as programmed in the DSC
field of System Configuration 1, enables this signal and selects its
polarity.
Decompression Input Data Request, active low. When this signal is
active, it indicates the ability of the DI port to accept data.
Decompression Input Data Acknowledge. Active low decompression
data input. When this signal is active, it indicates the data on D is for the
decompression input port. Data on D is latched on the rising edge of
CLOCK when the strobe condition is met.
Decompression Output Data Request, active low. When this signal is
active, it indicates the ability of the DO port to transmit data.
Decompression Output Data Acknowledge. The definition of DOACKN
varies with the data strobe condition in System Configuration 1. See
Table 4.
VIDEO INTERFACE
SIGNAL
VOREQN
VOACKN
VOD[7:0]
VOEORN
VOEOTN
PS3422-0600
TYPE
O
S
I
S
O
S
O
S
O
S
VIDEO INTERFACE
DESCRIPTION
Video Output Request. Active low output indicating that the byte on
VOD[7:0] is valid.
Video Output Acknowledge. Active low input indicating that the external
system is ready to read VOD[7:0].
Video Output Data. The value on this output bus is read when both
VOREQN and VOACKN are low.
Video Output End of Record is active low indicating the byte on
VOD[7:0] contains the last byte in a record.
Video Output End of Transfer is active low indicating the byte on
VOD[7:0] contains the last byte in a multi-record transfer.
Page 23 of 44
Advanced
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5.4
SYSTEM CONTROL
SIGNAL
TYPE
CLOCK
I
RSTN
I
A
TEST0
I
A
I
A
TEST1
Page 24 of 44
SYSTEM CONTROL
DESCRIPTION
System Clock. This signal is connected to the clock of the
microprocessor. The Intel i960Cx calls this pin PCLK.
Power on Reset. Active low reset signal. The device must be reset before
any DMA or microprocessor activity is attempted. RSTN should be a
minimum of 10 CLOCK periods.
Board Test mode. When TEST is high, all outputs are tristated. When
TEST is low, the chip performs normally.
Used for production tests. This input should always be tied low.
PS3422-0600
advancedhardwarearchitectures
6.0
PINOUT
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
SIGNAL
VDD or VSS*
VDD or VSS*
VDD or VSS*
VDD or VSS*
VDD or VSS*
INTRN
VSS
VDD
DRIVEN
SD
DOACKN
VDD
DIACKN
VDD
VSS
VDD
DOREQN
NC
DIREQN
NC
NC
D[0]
VSS
VSS
VDD
VDD
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]
D[10]
D[11]
VSS
VDD
D[12]
D[13]
D[14]
TEST1
PIN
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
SIGNAL
VSS
VSS
VDD
CLOCK
VSS
VDD
VDD
VSS
VDD
D[15]
D[16]
D[17]
D[18]
D[19]
D[20]
D[21]
D[22]
D[23]
D[24]
VSS
VDD
D[25]
D[26]
D[27]
D[28]
D[29]
D[30]
VDD
VDD
VSS
VSS
D[31]
VOREQN
VOEORN
VOD[0]
VOD[1]
VOD[2]
VDD
VSS
VOD[3]
VOD[4]
VOD[5]
VOD[6]
PIN
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
SIGNAL
VOD[7]
NC
VDD
VSS
VOACKN
TEST0
PA[0]
PA[1]
PA[2]
PA[3]
VDD
PA[5]
VSS
PA[4]
NC
VOEOTN
PROCMODE[1]
PROCMODE[0]
CSN
VDD
VSS
DIR
RSTN
PD[7]
PD[6]
PD[5]
VDD
VSS
PD[4]
PD[3]
PD[2]
PD[1]
PD[0]
VDD
VSS
RDYN
VDD
VDD or VSS*
VDD or VSS*
VDD or VSS*
VDD
VSS
*Note: the pins marked VDD or VSS can be connected to either VDD or VSS but should not be left unconnected.
PS3422-0600
Page 25 of 44
Advanced
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96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
PA[3]
PA[2]
PA[1]
PA[0]
TEST0
VOACKN
VSS
VDD
NC
VOD[7]
VOD[6]
VOD[5]
VOD[4]
VOD[3]
VSS
VDD
VOD[2]
VOD[1]
VOD[0]
VOEORN
VOREQN
D[31]
VSS
VSS
VDD
VDD
D[30]
D[29]
D[28]
D[27]
D[26]
D[25]
Figure 15: Pinout
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
AHA3422A-033 PQC
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDD
VSS
D[24]
D[23]
D[22]
D[21]
D[20]
D[19]
D[18]
D[17]
D[16]
D[15]
VDD
VSS
VDD
VDD
VSS
CLOCK
VDD
VSS
VSS
TEST1
D[14]
D[13]
D[12]
VDD
VSS
D[11]
D[10]
D[9]
D[8]
D[7]
*I
*I
*I
*I
*I
INTRN
VSS
VDD
DRIVEN
SD
DOACKN
VDD
DIACKN
VDD
VSS
VDD
DOREQN
NC
DIREQN
NC
NC
D[0]
VSS
VSS
VDD
VDD
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VDD
PA[5]
VSS
PA[4]
NC
VOEOTN
PROCMODE[1]
PROCMODE[0]
CSN
VDD
VSS
DIR
RSTN
PD[7]
PD[6]
PD[5]
VDD
VSS
PD[4]
PD[3]
PD[2]
PD[1]
PD[0]
VDD
VSS
RDYN
VDD
*I
*I
*I
VDD
VSS
NC = No Connect
*I = Connect to VDD or VSS
Page 26 of 44
PS3422-0600
advancedhardwarearchitectures
7.0
DC ELECTRICAL SPECIFICATIONS
7.1
OPERATING CONDITIONS
SYMBOL
Vdd
Idd
Idd
Idd
Ta
Vil
Vih
Iil
Vol
Voh
Voh
Iol
Ioh
Ioz
Ioz
Cin
Cout
Cio
Comax
OPERATING CONDITIONS
PARAMETER
MIN
Supply voltage
Supply current (active)
Supply current (standby)
Supply current (low power)
Ambient temperature
Input low voltage:
PROCMODE[1:0], TEST0, TEST1
Other signals
Input high voltage:
PROCMODE[1:0], TEST0, TEST1
Other signals
Input leakage current
Output low voltage (Iol=-4mA)
Output high voltage (Ioh=4mA)
Output high voltage (Ioh=100µA)
Output low current
Output high current
Output leakage current
High impedance leakage current
Input capacitance
Output capacitance
Input/Output capacitance
Maximum capacitance load for all
signals (including self loading)
MAX
UNITS
NOTES
V
mA
mA
mA
°C
4
1, 4
2, 4
0
5.25
300
80
1
70
Vss-0.5
Vss-0.5
0.3×Vdd
0.8
V
0.7×Vdd
2.0
-10
Vdd+0.5
Vdd+0.5
10
0.4
V
4.75
4
-4
10
10
5
7
7
µA
V
V
V
mA
mA
µA
µA
pF
pF
pF
50
pF
2.4
Vdd-0.8
-10
-10
3
Notes:
1) Dynamic current; no data transfers
2) Static current (clock high)
3) Timings referenced to this load
4) ILOAD = 0 mA
7.2
ABSOLUTE MAXIMUM STRESS RATINGS
SYMBOL
Tstg
Vdd
Vin
PS3422-0600
ABSOLUTE MAXIMUM STRESS RATINGS
PARAMETER
MIN
MAX
Storage temperature
Supply voltage
Input voltage
-50
-0.5
Vss-0.5
150
7
Vdd+0.5
UNITS
NOTES
°C
V
V
Page 27 of 44
Advanced
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8.0
AC ELECTRICAL SPECIFICATIONS
Notes:
1) Production test condition is 50 pF. Output delay is decreased 2 ns with 25 pF load guaranteed by design or
characterization.
2) All timings are referenced to 1.4 volts.
Figure 16: Data Interface Timing
CLOCK
1
2
3
4
ACKN/
SD
Valid
D
5
6
REQN
7
8
D/
COEORN
Table 6:
Valid 0
Valid 1
Data Port Timing Requirements
NUMBER
1
2
3
4
5
6
PARAMETER
MIN
DIACKN, DOACKN and SD setup time
DIACKN, DOACKN and SD hold time
D-bus input setup time
D-bus input hold time
REQN delay (non-EOR case)
REQN hold (non-EOR case)
MAX
8
2
8
2
18
2
UNITS
ns
ns
ns
ns
ns
ns
Figure 17: Request Deasserts at EOR, Strobe Condition of DSC=0-3, 6-15; ERC=0
CLOCK
SD
ACKN
1
2
REQN
D
Page 28 of 44
EOR-1
EOR
PS3422-0600
advancedhardwarearchitectures
Figure 18: Request Deasserts at EOR, Strobe Condition of DSC=0-3, 6-15; ERC=1
CLOCK
SD
ACKN
3
REQN
D
EOR-1
EOR
Figure 19: Request Deasserts at EOR, Strobe Condition of DSC=4 or 5; ERC=0
CLOCK
SD
ACKN
4
REQN
D
EOR-1
EOR
Figure 20: Request Deasserts at EOR, Strobe Condition of DSC=4 or 5; ERC=1
CLOCK
SD
ACKN
5
REQN
D
EOR-1
Table 7: Request vs. EOR Timing
NUMBER
PARAMETER
1
2
3
4
5
PS3422-0600
ACKN, SD to REQN ERC=0
CLOCK to REQN ERC=0
CLOCK to REQN DSC=0-3, 6, 7; ERC=1
CLOCK to REQN DSC=4, 5; ERC=0
CLOCK to REQN DSC=4, 5; ERC=1
EOR
MIN
MAX
UNITS
16
16
16
16
16
ns
ns
ns
ns
ns
Page 29 of 44
Advanced
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Figure 21: Output Enable Timing
CLOCK
ACKN
DRIVEN
D
1
Table 8:
4
5
Output Enable Timing Requirements
NUMBER
1
2
3
4
5
3
2
PARAMETER
MIN
DRIVEN to D valid
DRIVEN to D tristate
Signal to D valid
Signal to D tristate
CLOCK to D tristate (DSC=100, 101)
MAX
UNITS
15
10
15
10
15
ns
ns
ns
ns
ns
MAX
UNITS
16
ns
ns
ns
ns
ns
ns
ns
ns
Figure 22: Video Output Port Timing
CLOCK
VOREQN
1
2
VOACKN
3
4
VOD[7:0]
5
6
7
8
VOEORN
Table 9: Video Output Port Timing Requirements
NUMBER
PARAMETER
1
2
3
4
5
6
7
8
Page 30 of 44
VOREQN delay
VOREQN hold
VOACKN setup
VOACKN hold
VOD delay
VOD hold
VOEORN hold
VOEORN delay
MIN
2
8
2
16
2
2
16
PS3422-0600
advancedhardwarearchitectures
Figure 23: Microprocessor Interface Timing (PROCMODE[1]=0)
1
2
3
4
5
1
2
CLOCK
1
PA
2
1
2
4
3
4
Valid
3
CSN
7
6
8
RDYN
tristate
READ
9
9
10
10
DIR
12
13
PD
tristate
Valid
WRITE
9
10
9
10
DIR
15
14
PD
Valid
Figure 24: Microprocessor Interface Timing (PROCMODE[1]=1)
1
2
3
4
5
N
CLOCK
1
2
PA
A0
3
4
CSN
7
16
RDYN
17
READ
DIR
13
12
PD
tristate
Valid
14
WRITE
15
PD
Valid
9
10
DIR
PS3422-0600
Page 31 of 44
Advanced
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Hardware Architectures, Inc.
Table 10:
Microprocessor Interface Timing Requirements
NUMBER
1
2
3
4
6
7
8
9
10
12
13
14
15
16
17
PARAMETER
MIN
PA setup time
PA hold time
CSN setup time
CSN hold time
CSN to valid RDYN
RDYN valid delay
RDYN drive disable
DIR setup time
DIR hold time
PD valid delay
PD drive disable
PD setup time
PD hold time
CSN high to PD tristate
CSN high to RDYN high
MAX
8
2
8
2
UNITS
10
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MAX
UNITS
15
ns
ns
MAX
UNITS
2
2
ns
ns
ns
ns
ns
15
16
10
8
2
16
12
8
2
Figure 25: Interrupt Timing
CLOCK
INTRN
1
Table 11:
Interrupt Timing Requirements
NUMBER
1
2
2
PARAMETER
MIN
INTRN delay time
INTRN hold time
2
Figure 26: Clock Timing
1
2
2.0V
1.4V
0.8V
CLK
3
4
5
Table 12:
Clock Timing Requirements
NUMBER
1
2
3
4
5
Page 32 of 44
PARAMETER
CLOCK rise time
CLOCK fall time
CLOCK high time
CLOCK low time
CLOCK period
MIN
12
12
30
PS3422-0600
advancedhardwarearchitectures
Figure 27: Power On Reset Timing
CLOCK
2
3
RSTN
1
Table 13:
NUMBER
1
2
3
Power On Reset Timing Requirements
PARAMETER
RSTN low pulsewidth
RSTN setup to CLOCK rise
RSTN hold time
MIN
10
15
2
MAX
UNITS
clocks
ns
ns
Notes:
1) RSTN signal can be asynchronous to the CLOCK signal. It is internally synchronized to the rising edge of
CLOCK.
PS3422-0600
Page 33 of 44
Advanced
advancedhardwarearchitectures
Hardware Architectures, Inc.
9.0
PACKAGE SPECIFICATIONS
A
A2 A
L
DETAIL A
A1
D
D1
P
B
97
98
99
100
AHA3422A-033 PQC
(LCA)
E1 E
125
126
127
P
128
28 29 30 31 32
(LCB)
JEDEC outline is MO-108
Page 34 of 44
PS3422-0600
advancedhardwarearchitectures
PLASTIC QUAD FLAT PACK PACKAGE DIMENSIONS
NUMBER OF PIN AND SPECIFICATION DIMENSION
128
SB
NOM
32
32
3.7
0.33
3.37
31.2
28
31.2
28
0.88
0.8
0.35
SYMBOL
MIN
(LCA)
(LCB)
A
A1
A2
D
D1
E
E1
L
P
B
0.25
3.2
30.95
27.99
30.95
27.99
0.73
0.3
MAX
4.07
3.6
31.45
28.12
31.45
28.12
1.03
0.4
10.0 ORDERING INFORMATION
10.1 AVAILABLE PARTS
PART NUMBER
DESCRIPTION
AHA3422A-033 PQC 16 MBytes/sec Lossless Decompressor IC
10.2 PART NUMBERING
AHA
3422
A-
033
P
Q
C
Manufacturer
Device
Number
Revision
Level
Speed
Designation
Package
Material
Package
Type
Test
Specification
Device Number:
3422
Revision Letter:
A
Package Material Codes:
P
Plastic
Package Type Codes:
Q Quad Flat Pack
Test Specifications:
C Commercial 0°C to +70°C
PS3422-0600
Page 35 of 44
Advanced
advancedhardwarearchitectures
Hardware Architectures, Inc.
11.0 RELATED TECHNICAL PUBLICATIONS
DOCUMENT #
PS3410C
PS3411
PS3431
PB3410C
PB3411
PB3422
PB3431
ABDC18
ANDC12
ANDC13
ANDC14
ANDC15
ANDC16
ANDC17
GLGEN1
STARSW
Page 36 of 44
DESCRIPTION
AHA Product Specification – AHA3410C StarLite 25 MBytes/sec Simultaneous Lossless
Data Compression/Decompression Coprocessor IC
AHA Product Specification – AHA3411 StarLite 33 MBytes/sec Simultaneous
Compressor/Decompressor IC
AHA Product Specification – AHA3431 StarLite 40 MBytes/sec Simultaneous
Compressor/Decompressor IC, 3.3V
AHA Product Brief – AHA3410C StarLite 25 MBytes/sec Simultaneous Lossless Data
Compression/Decompression Coprocessor IC
AHA Product Brief – AHA3411 StarLite 33 MBytes/sec Simultaneous Compressor/
Decompressor IC
AHA Product Brief – AHA3422 StarLite 16 MBytes/sec Lossless Decompressor IC
AHA Product Brief – AHA3431 StarLite 40 MBytes/sec Simultaneous Compressor/
Decompressor IC, 3.3V
AHA Application Brief – AHA3410C, AHA3411 and AHA3431 Device Differences
AHA Application Note – AHA3410C StarLite Designer’s Guide
AHA Application Note – Compression Performance on Bitonal Images
AHA Application Note – StarLite Evaluation Software
AHA Application Note – ENCODEB2 Compression Algorithm Description
AHA Application Note – Designer’s Guide for StarLite Family Products: AHA3411,
AHA3422 and AHA3431
AHA Application Note – StarLite Compression on Continuous Tone Images
General Glossary of Terms
StarLite Evaluation Software (WindowsTM)
PS3422-0600
advancedhardwarearchitectures
APPENDIX A: ADDITIONAL TIMING DIAGRAMS FOR DMA MODE TRANSFERS
Figure A1:
DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=000
CLOCK
ACKN
SD
DRIVEN
D
Figure A2:
D0
D1
DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=000
CLOCK
ACKN
SD
DRIVEN
D
Figure A3:
D0
D1
DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition
of DSC=000
CLOCK
ACKN
SD
DRIVEN
D
PS3422-0600
D0
D1
D2
D3
Page 37 of 44
Advanced
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Figure A4:
DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition
of DSC=000
CLOCK
ACKN
SD
DRIVEN
D
Figure A5:
D0
D1
D2
D3
DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition
of DSC=000
CLOCK
ACKN
SD
DRIVEN
D
Figure A6:
D0
D1
D2
D3
D4
D5
D6
D7
DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition
of DSC=000
CLOCK
ACKN
SD
DRIVEN
D
Page 38 of 44
D0
D1
D2
D3
D4
D5
D6
D7
PS3422-0600
advancedhardwarearchitectures
Figure A7:
DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=010
CLOCK
ACKN
SD
DRIVEN
D
Figure A8:
D0
D1
DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=010
CLOCK
ACKN
SD
DRIVEN
D
Figure A9:
D0
D1
DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition
of DSC=010
CLOCK
ACKN
SD
DRIVEN
D
PS3422-0600
D0
D1
D2
D3
Page 39 of 44
Advanced
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Hardware Architectures, Inc.
Figure A10: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition
of DSC=010
CLOCK
ACKN
SD
DRIVEN
D
D0
D1
D2
D3
Figure A11: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition
of DSC=010
CLOCK
ACKN
SD
DRIVEN
D
D0
D1
D2
D3
D4
D5
D6
D7
Figure A12: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition
of DSC=010
CLOCK
ACKN
SD
DRIVEN
D
Page 40 of 44
D0
D1
D2
D3
D4
D5
D6
D7
PS3422-0600
advancedhardwarearchitectures
Figure A13: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=011
CLOCK
ACKN
SD
DRIVEN
D
D0
D1
Figure A14: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=011
CLOCK
ACKN
SD
DRIVEN
D
D0
D1
Figure A15: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition
of DSC=011
CLOCK
ACKN
SD
DRIVEN
D
PS3422-0600
D0
D1
D2
D3
Page 41 of 44
Advanced
advancedhardwarearchitectures
Hardware Architectures, Inc.
Figure A16: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition
of DSC=011
CLOCK
ACKN
SD
DRIVEN
D
D0
D1
D2
D3
Figure A17: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition
of DSC=011
CLOCK
ACKN
SD
DRIVEN
D
D0
D1
D2
D3
D4
D5
D6
D7
Figure A18: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition
of DSC=011
CLOCK
ACKN
SD
DRIVEN
D
Page 42 of 44
D0
D1
D2
D3
D4
D5
D6
D7
PS3422-0600
advancedhardwarearchitectures
Figure A19: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=111
CLOCK
ACKN
SD
DRIVEN
D
D0
D1
D2
Figure A20: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=111
CLOCK
ACKN
SD
DRIVEN
D
PS3422-0600
D0
D1
D2
Page 43 of 44
Advanced
advancedhardwarearchitectures
Hardware Architectures, Inc.
APPENDIX B: SEQUENTIAL REGISTER TABLE
ADDRESS
00
01
02
03
04
05
06
07
09
0A
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
1A
1C
1D
20
21
27
29
2C
2D
30
31
32
33
34
35
38
3F
Page 44 of 44
DESCRIPTION
System Configuration 0
System Configuration 1
Input FIFO Thresholds
Output FIFO Thresholds
Reserved
Decompression Ports Status
Port Control
Interrupt Status/Control 0
Interrupt Mask 0
Version
Decompression Record Length 0
Decompression Record Length 1
Decompression Record Length 2
Decompression Record Length 3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Decompression Control
Decompression Reserved 1
Decompression Line Length 0
Decompression Line Length 1
Reserved
Reserved
Interrupt Status/Control 1
Interrupt Mask 1
Decompression Record Count 0
Decompression Record Count 1
Reserved
Reserved
Reserved
Reserved
Reserved
Pattern
Decompression Control Prearm
Control
PS3422-0600