ETC PI90LV3810

PI90LV3810/PI90LVR3810
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High-Speed Differential
Line Receivers
Features
Description
• Ten line receivers meet or exceed the requirements of the
ANSI TIA/EIA-644-1995 Standard
• Designed for signaling rates up to 660 Mbps
• 0V to 3V common-mode input voltage range
• Operates from a single 3.3V supply
• Typical propagation delay time: 2.6ns
• Output skew 100ps (typical)
• Part-to-part skew is less than 1ns
• PI90LVR3810
Set up time: typical 1ns
Max. clock to output: 1ns
• Integrated 110-ohm termination on PI90LVT386
• Low Voltage TTL (LVTTL) levels are 5V tolerant
• Open-circuit fail safe
• Flow-through pin out
• Packaging:
48-Pin Thin Shrink Small Output TSSOP (A)
The PI90LVx3810 family consists of ten differential line receivers
with 3-state outputs that implement Low-Voltage Differential Signaling (LVDS). The PI90LVR3810 has integrated edge-triggered
D-type flops. Any of the differential receivers will provide a valid
logical output state with a ±100mV differential input voltage within
the input common-mode voltage range that allows 0 to 3V of ground
potential difference between two LVDS nodes. The independent EN
pins can be used to place the outputs in either a normal logic state
(high or low logic levels) or a high-impedance state. In highimpedance state, outputs neither load nor drive the bus lines.
The intended application of these devices, and their signaling
techniques, is for point-to-point baseband data transmission over
controlled impedance media of approximately 100-Ohms with a 100Ohm termination resistor. The transmission media may be printed
circuit board traces, backplanes, or cables. The PI90LV3810’s 10
receivers integrated into the same substrate allow precise timing
alignment. In addition, the PI90LVR3810's integrated registers
resynchronize the data to the system clock, for additional signal
deskew.
The integrated registers in the PI90LVR3810 are particularly suitable
for interfacing with LVDS drivers such as the PI90LV3811 over long
distances where signal-to-signal skew may be a problem. On the
positive transition of the differential clock (CLK±) input, the Q
outputs of the flip-flop take on the logic levels set up at the
differential data (RIN±) inputs.
PI90LV3810
Old data can be retained or new data can be entered while the
outputs are in the high-impedance state. The EN pins do not affect
the internal operation of the flip-flops.
PI90LVR3810 Truth Table
1
SET
ROUT
0
Q=D
1
Q=1
PS8664
02/21/03
PI90LV3810/PI90LVR3810
High-Speed
Differential
Line Receivers
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PI90LV3810 Block Diagram
PI90LV3810 Pin Configuration
PI90LVR3810 Block Diagram
PI90LVR3810 Pin Configuration
2
PS8664
02/21/03
PI90LV3810/PI90LVR3810
High-Speed
Differential
Line Receivers
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Absolute Maximum Ratings
Over Operating Free-Air Temperature
(unless otherwise noted)†
Function Table
Supply Voltage Range, VDD(1) ....................................... –0.5V to 4V
Voltage Range :
Enables or ROUT ................................................... –0.5V to VDD +2V
RIN+ or RIN– ........................................................................... –0.5V to 4V
Electrostatic Discharge(2):
RIN+, RIN–, and GND .......................... Class 3, A: 10kV, B:700V
All Pins ................................................. Class 3, A: 8kV, B:600V
Storage Temperature Range ............................. –65°C to 150°C
Lead Temperature 1, 6mm (1/16 inch)
from case for 10 seconds .................................................... 260°C
Diffe re ntial Input
Enable s
Output
EN
ROUT
H
H
H
?
H
L
CLK±
LVR
only
RIN±
VID _> 100mV
–100mV > VID _> 100mV
↑
_ 100mV
VID <
† Stresses beyond those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated under
"Recommended Operating Conditions" is not implied.
Exposure to Absolute-Maximum-Rated conditions for extended
periods may affect device reliability.
X
X
L
Z
Open
↑
H
H
X
H or L
H
ROUT0
H = High level
L = Low level
X = Irrelevent
Z = High-impedance (off)
? = Indeterminate
↑= Rising edge of clock
Notes:
1. All voltage values, except differential I/O bus voltages, are
with respect to ground terminal.
2. Tested in accordance with MIL-STD-883C Method 3015.7
Recommended Operating Conditions
M in.
Nom.
M ax.
Supply Voltage, VCC
3.0
3.3
3.6
High- Level Input Voltage, VIH
2.0
Units
0.8
Low- Level Input Voltage, VIL
Magnitude of Differential Input Voltage VID
Common- Mode input Voltage, VIC
V
0.1
0.6
VID
2
2.4 –VID
2
VCC –0.8
Operating free- air temperature, TA
–40
3
85
°C
PS8664
02/21/03
PI90LV3810/PI90LVR3810
High-Speed
Differential
Line Receivers
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Electrical Characteristics Over Recommended Operating Conditions (unless otherwise noted)
Symbol
VITH+
Parameter
Test Conditions
Min.
Typ.(1)
Positive-going differential input voltage threshold
Max.
100
VITH-
Negative-going differential input voltage threshold
VOH
High-level output voltage
IOH = -8mA
VOL
Low-level output voltage
IOL = 8mA
0.2
0.4
ICC
Supply current
Enabled, No load
22
40
II
II(OFF)
-100
VI = 2.4V
IIL
VCC = 0V, VI = 2.4V
-13
-1.2
± 20
VIL = 0.8V
10
Low-level input current (enables)
VO = 0V
±1
IOZ
High-impedance output current
VO= 3.6V
10
CIN
Input capacitance (RIN+ or RIN- inputs to GND
5
mA
µA
VIH = 2V
VID = 0.4 sin 2.5E09t V
mV
-20
-3
12
mV
V
3
VI = 0V
Power-off input current (RIN+ or RIN-inputs)
High-level input current (enables)
3
Disabled
Input current (RIN + or RIN-inputs)
IIH
2.4
Units
10
mA
µA
pF
Note: 1. All typical values are at 25°C and with a 3.3V supply.
4
PS8664
02/21/03
PI90LV3810/PI90LVR3810
High-Speed
Differential
Line Receivers
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Switching Characteristics Over Recommended Operating Conditions (unless otherwise noted)
Symbol
Parame te r
tPLH
Propagation delay time, low- to- high- level output
tPHL
Propagation delay time, high- to- low- level output
tr
Differential output signal rise time
tf
Differential output signal fall time
Te s t Conditions
M in.
1
See Figure 2
(PI90LV3810)
500
Typ.(1)
M ax.
Units
4
ns
2.6
2.5
800
1400
tsk(p)
Pulse skew (tPHL – tPLH)
150
600
tsk(o)
Output skew(2)
100
450
tsk(pp)
Part- to- part skew(3)
tPZH
Propagation delay time, high- impedance- to- high- level output
tPZL
Propagation delay time, high- impedance- to- low- level output
tPHZ
Propagation delay time, high- level- to- high- impedance output
tPLZ
Propagation delay time, low- level- to- high- impedance output
tSU
Set- up time, data before CLK ↑
1. 2
tH
Hold- up time, data after CLK ↑
1.0
tW
Pulse Duration, CLK HIGH or LOW
1
See Figure 3(4)
7
15
ns
PI90LVR3810
1.2
tPLH, tPHL Propagation delay time, CLK to ROUT
0.2
Maximum Clock frequency
300
fMAX
ps
3.5
MHz
Notes:
1. All typical values are at 25°C and with a 3.3V supply
2. tsk(o) is the magnitude of the time difference between the tPLH or tPHL of all drivers of a single device with all of their inputs
connected together.
3. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both
devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
4. ROUT0 disable time is 1 nanosecond greater.
5
PS8664
02/21/03
PI90LV3810/PI90LVR3810
High-Speed
Differential
Line Receivers
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Parameter Measurement Information
Figure 1. Voltage Definitions
Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages
Applie d Voltage s
Re s ulting Diffe re ntial
Input Voltage
Re s ulting CommonM ode Input Voltage
VIRIN+
VIRIN–
VID
VIC
1.25V
1.15V
100mV
1.2V
1.15V
1.25V
–100mV
1.2V
2.4V
2.3V
100mV
2.35V
2.3V
2.4V
–100mV
2.35V
0 . 1V
0V
100mV
0.05V
0V
0.1V
–100mV
0.05V
1.5V
0.9V
600mV
1.2V
0.9V
1.5V
–600mV
1.2V
2.4V
1.8V
600mV
2.1V
1.8V
2.4V
–600mV
2.1V
0.6V
0V
600mV
0.3V
0V
0.6V
–600mV
0.3V
6
PS8664
02/21/03
PI90LV3810/PI90LVR3810
High-Speed
Differential
Line Receivers
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Parameter Measurement Information
Note:
1. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1ns, Pulse Repetition
Rate (PRR) = 50 Mpps, Pulse width = 10 ±0.2ns. C L includes instrumentation and fixture capacitance within 0.06m
of the D.U.T.
Figure 2. Timing Test Circuit and Waveforms
7
PS8664
02/21/03
PI90LV3810/PI90LVR3810
High-Speed
Differential
Line Receivers
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Parameter Measurement Information
Note:
1. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1ns, Pulse Repetition
Rate (PRR) = 0.5 Mpps, pulse width = 500 ±10ns. CL includes instrumentation and fixture capacitance within 0.06m
of the D.U.T.
Figure 3. Enable/Disable Test Circuit and Waveforms
8
PS8664
02/21/03
PI90LV3810/PI90LVR3810
High-Speed
Differential
Line Receivers
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Typical Characteristics
Figure 4. Common-Mode Input Voltage
vs.
Differential Input Voltage
200
Max at VCC >3.15V
180
ICC – Supply Current – mA
VIC – Common-Moce Input Voltate – V
2.5
Max at VCC = 3V
2.0
1.5
1.0
0.5
160
VCC = 3.6V
140
120
VCC = 3V
100
80
VCC = 3.3V
60
40
Minimum
20
0
0
0
0.1
VID
0.2
0.3
0.4
0.5
0.6
0 20 40 60 80 100 120 140 160 180 200
– Differential Input Voltage – V
f – Switching Frequency – MHz
Figure 6. High-Level Output Voltage
vs.
High-Level Output Current
Figure 7. Low-Level Output Voltage
vs.
Low-Level Output Current
5.0
VOL – Low-Level Output Voltage – V
4.0
VOH – High-Level Output Voltate – V
Figure 5. Supply Current
vs.
Switching Frequency
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–70
–60
–50
–40
–30
–20
–10
0
0
I OH – High-Level Output Current – mA
10
20
30
40
50
60
70
80
I OL – Low-Level Output Current – mA
9
PS8664
02/21/03
PI90LV3810/PI90LVR3810
High-Speed
Differential
Line Receivers
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Typical Characteristics
Figure 8. Low-to-High Propagation Delay Time
vs.
Free-Air Temperature
Figure 9. High-to-Low Propagation Delay Time
vs.
Free-Air Temperature
3.0
tPHL – High-to-Low Propagation Delay Time – ns
tPLH – Low-to-High Propagation Delay Time – ns
3.0
2.9
2.8
VCC = 3V
2.7
2.6
VCC = 3.6V
2.5
VCC = 3.3V
2.4
2.3
2.2
2.1
2
–50
–30
–10
10
30
50
70
90
Ta – Free-Air Temperature – ˚C
2.9
2.8
2.7
2.6
VCC = 3V
2.5
2.4
VCC = 3.6V
2.3
VCC = 3.3V
2.2
2.1
2
–50
–30
–10
10
30
50
70
90
Ta – Free-Air Temperature – ˚C
10
PS8664
02/21/03
PI90LV3810/PI90LVR3810
High-Speed
Differential
Line Receivers
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Packaging Mechanical: 48-Pin TSSOP (A)
48
.236
.244
1
6.0
6.2
.488 12.4
.496 12.6
.047
1.20 Max
SEATING PLANE
.004 0.09
.008 0.20
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
.007
.010
.0197
BSC
0.50
0.45 .018
0.75 .030
.002
.006
0.05
0.15
0.17
0.27
.319
BSC
8.1
Ordering Information
Orde ring Code
Package Name
Package Type
Ope rating Range
PI90LV3810A
A48
48- pin
TSSOP (A)
–40°C to 85°C
PI90LVR3810A
A48
48- pin
TSSOP (A)
–40°C to 85°C
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
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PS8664
02/21/03